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From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: patches@groups.riscv.org, Michael Clark <mjc@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-devel] [PATCH v8 05/35] RISC-V: Remove unused class definitions
Date: Thu, 26 Apr 2018 11:45:08 +1200	[thread overview]
Message-ID: <1524699938-6764-6-git-send-email-mjc@sifive.com> (raw)
In-Reply-To: <1524699938-6764-1-git-send-email-mjc@sifive.com>

Removes a whole lot of unnecessary boilerplate code. Machines
don't need to be objects. The expansion of the SOC object model
for the RISC-V machines will happen in the future as SiFive
plans to add their FE310 and FU540 SOCs to QEMU. However, it
seems that this present boilerplate is complete unnecessary.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/riscv/riscv_hart.c       |  6 ------
 hw/riscv/sifive_e.c         | 25 -------------------------
 hw/riscv/sifive_u.c         | 25 -------------------------
 hw/riscv/spike.c            | 20 --------------------
 hw/riscv/virt.c             | 25 -------------------------
 include/hw/riscv/sifive_e.h |  5 -----
 include/hw/riscv/sifive_u.h |  5 -----
 include/hw/riscv/spike.h    |  7 -------
 include/hw/riscv/virt.h     |  5 -----
 9 files changed, 123 deletions(-)

diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index 14e3c18..75ba7ed 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -68,16 +68,10 @@ static void riscv_harts_class_init(ObjectClass *klass, void *data)
     dc->realize = riscv_harts_realize;
 }
 
-static void riscv_harts_init(Object *obj)
-{
-    /* RISCVHartArrayState *s = SIFIVE_COREPLEX(obj); */
-}
-
 static const TypeInfo riscv_harts_info = {
     .name          = TYPE_RISCV_HART_ARRAY,
     .parent        = TYPE_SYS_BUS_DEVICE,
     .instance_size = sizeof(RISCVHartArrayState),
-    .instance_init = riscv_harts_init,
     .class_init    = riscv_harts_class_init,
 };
 
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 09c9d49..4872b68 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -194,24 +194,6 @@ static void riscv_sifive_e_init(MachineState *machine)
     }
 }
 
-static int riscv_sifive_e_sysbus_device_init(SysBusDevice *sysbusdev)
-{
-    return 0;
-}
-
-static void riscv_sifive_e_class_init(ObjectClass *klass, void *data)
-{
-    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
-    k->init = riscv_sifive_e_sysbus_device_init;
-}
-
-static const TypeInfo riscv_sifive_e_device = {
-    .name          = TYPE_SIFIVE_E,
-    .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(SiFiveEState),
-    .class_init    = riscv_sifive_e_class_init,
-};
-
 static void riscv_sifive_e_machine_init(MachineClass *mc)
 {
     mc->desc = "RISC-V Board compatible with SiFive E SDK";
@@ -220,10 +202,3 @@ static void riscv_sifive_e_machine_init(MachineClass *mc)
 }
 
 DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
-
-static void riscv_sifive_e_register_types(void)
-{
-    type_register_static(&riscv_sifive_e_device);
-}
-
-type_init(riscv_sifive_e_register_types);
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 6116c38..2412b5d 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -301,31 +301,6 @@ static void riscv_sifive_u_init(MachineState *machine)
         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
 }
 
-static int riscv_sifive_u_sysbus_device_init(SysBusDevice *sysbusdev)
-{
-    return 0;
-}
-
-static void riscv_sifive_u_class_init(ObjectClass *klass, void *data)
-{
-    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
-    k->init = riscv_sifive_u_sysbus_device_init;
-}
-
-static const TypeInfo riscv_sifive_u_device = {
-    .name          = TYPE_SIFIVE_U,
-    .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(SiFiveUState),
-    .class_init    = riscv_sifive_u_class_init,
-};
-
-static void riscv_sifive_u_register_types(void)
-{
-    type_register_static(&riscv_sifive_u_device);
-}
-
-type_init(riscv_sifive_u_register_types);
-
 static void riscv_sifive_u_machine_init(MachineClass *mc)
 {
     mc->desc = "RISC-V Board compatible with SiFive U SDK";
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 7710333..f370f12 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -334,18 +334,6 @@ static void spike_v1_09_1_board_init(MachineState *machine)
         smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
 }
 
-static const TypeInfo spike_v_1_09_1_device = {
-    .name          = TYPE_RISCV_SPIKE_V1_09_1_BOARD,
-    .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(SpikeState),
-};
-
-static const TypeInfo spike_v_1_10_0_device = {
-    .name          = TYPE_RISCV_SPIKE_V1_10_0_BOARD,
-    .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(SpikeState),
-};
-
 static void spike_v1_09_1_machine_init(MachineClass *mc)
 {
     mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)";
@@ -363,11 +351,3 @@ static void spike_v1_10_0_machine_init(MachineClass *mc)
 
 DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init)
 DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
-
-static void riscv_spike_board_register_types(void)
-{
-    type_register_static(&spike_v_1_09_1_device);
-    type_register_static(&spike_v_1_10_0_device);
-}
-
-type_init(riscv_spike_board_register_types);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 6311675..782996c 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -382,24 +382,6 @@ static void riscv_virt_board_init(MachineState *machine)
         serial_hds[0], DEVICE_LITTLE_ENDIAN);
 }
 
-static int riscv_virt_board_sysbus_device_init(SysBusDevice *sysbusdev)
-{
-    return 0;
-}
-
-static void riscv_virt_board_class_init(ObjectClass *klass, void *data)
-{
-    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
-    k->init = riscv_virt_board_sysbus_device_init;
-}
-
-static const TypeInfo riscv_virt_board_device = {
-    .name          = TYPE_RISCV_VIRT_BOARD,
-    .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(RISCVVirtState),
-    .class_init    = riscv_virt_board_class_init,
-};
-
 static void riscv_virt_board_machine_init(MachineClass *mc)
 {
     mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)";
@@ -408,10 +390,3 @@ static void riscv_virt_board_machine_init(MachineClass *mc)
 }
 
 DEFINE_MACHINE("virt", riscv_virt_board_machine_init)
-
-static void riscv_virt_board_register_types(void)
-{
-    type_register_static(&riscv_virt_board_device);
-}
-
-type_init(riscv_virt_board_register_types);
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 0aebc57..12ad6d2 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -19,11 +19,6 @@
 #ifndef HW_SIFIVE_E_H
 #define HW_SIFIVE_E_H
 
-#define TYPE_SIFIVE_E "riscv.sifive_e"
-
-#define SIFIVE_E(obj) \
-    OBJECT_CHECK(SiFiveEState, (obj), TYPE_SIFIVE_E)
-
 typedef struct SiFiveEState {
     /*< private >*/
     SysBusDevice parent_obj;
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index be38aa0..94a3905 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -19,11 +19,6 @@
 #ifndef HW_SIFIVE_U_H
 #define HW_SIFIVE_U_H
 
-#define TYPE_SIFIVE_U "riscv.sifive_u"
-
-#define SIFIVE_U(obj) \
-    OBJECT_CHECK(SiFiveUState, (obj), TYPE_SIFIVE_U)
-
 typedef struct SiFiveUState {
     /*< private >*/
     SysBusDevice parent_obj;
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
index d85a64e..8410430 100644
--- a/include/hw/riscv/spike.h
+++ b/include/hw/riscv/spike.h
@@ -19,12 +19,6 @@
 #ifndef HW_SPIKE_H
 #define HW_SPIKE_H
 
-#define TYPE_RISCV_SPIKE_V1_09_1_BOARD "riscv.spike_v1_9_1"
-#define TYPE_RISCV_SPIKE_V1_10_0_BOARD "riscv.spike_v1_10"
-
-#define SPIKE(obj) \
-    OBJECT_CHECK(SpikeState, (obj), TYPE_RISCV_SPIKE_BOARD)
-
 typedef struct {
     /*< private >*/
     SysBusDevice parent_obj;
@@ -35,7 +29,6 @@ typedef struct {
     int fdt_size;
 } SpikeState;
 
-
 enum {
     SPIKE_MROM,
     SPIKE_CLINT,
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 655e85d..b91a412 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -19,10 +19,6 @@
 #ifndef HW_VIRT_H
 #define HW_VIRT_H
 
-#define TYPE_RISCV_VIRT_BOARD "riscv.virt"
-#define VIRT(obj) \
-    OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_BOARD)
-
 typedef struct {
     /*< private >*/
     SysBusDevice parent_obj;
@@ -45,7 +41,6 @@ enum {
     VIRT_DRAM
 };
 
-
 enum {
     UART0_IRQ = 10,
     VIRTIO_IRQ = 1, /* 1 to 8 */
-- 
2.7.0

  parent reply	other threads:[~2018-04-25 23:47 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-25 23:45 [Qemu-devel] [PATCH v8 00/35] QEMU 2.13 Privileged ISA emulation updates Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 01/35] RISC-V: Replace hardcoded constants with enum values Michael Clark
2018-04-26 16:37   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 02/35] RISC-V: Make virt board description match spike Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 03/35] RISC-V: Use ROM base address and size from memmap Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 04/35] RISC-V: Remove identity_translate from load_elf Michael Clark
2018-04-25 23:45 ` Michael Clark [this message]
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 06/35] RISC-V: Include instruction hex in disassembly Michael Clark
2018-04-26 17:05   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 07/35] RISC-V: Make some header guards more specific Michael Clark
2018-04-26 16:43   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 08/35] RISC-V: Make virt header comment title consistent Michael Clark
2018-04-26 16:42   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 09/35] RISC-V: Remove EM_RISCV ELF_MACHINE indirection Michael Clark
2018-04-26 16:42   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 10/35] RISC-V: Remove erroneous comment from translate.c Michael Clark
2018-04-25 23:51   ` [Qemu-devel] [patches] " Palmer Dabbelt
2018-04-26 16:48   ` [Qemu-devel] " Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 11/35] RISC-V: Mark ROM read-only after copying in code Michael Clark
2018-04-26 16:48   ` Alistair Francis
2018-04-27  5:22     ` Michael Clark
2018-04-27  5:34       ` Michael Clark
2018-04-27 16:17         ` Alistair Francis
2018-05-04  1:45           ` Michael Clark
2018-05-04 23:44             ` Alistair Francis
2018-05-04 23:54               ` Alistair Francis
2018-05-05  2:02                 ` Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 12/35] RISC-V: Update address bits to support sv39 and sv48 Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 13/35] RISC-V: Improve page table walker spec compliance Michael Clark
2018-05-03 20:49   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 14/35] RISC-V: Update E order and I extension order Michael Clark
2018-04-26 17:11   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 15/35] RISC-V: Hardwire satp to 0 for no-mmu case Michael Clark
2018-04-26 17:21   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 16/35] RISC-V: Make mtvec/stvec ignore vectored traps Michael Clark
2018-04-26 17:27   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 17/35] RISC-V: No traps on writes to misa, minstret, mcycle Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 18/35] RISC-V: Clear mtval/stval on exceptions without info Michael Clark
2018-04-26 17:36   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 19/35] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10 Michael Clark
2018-04-26 20:02   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 20/35] RISC-V: Use [ms]counteren CSRs " Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 21/35] RISC-V: Add mcycle/minstret support for -icount auto Michael Clark
2018-04-26 20:05   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 22/35] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps Michael Clark
2018-04-27  0:14   ` Richard Henderson
2018-04-27  7:18     ` Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 23/35] RISC-V: Simplify riscv_cpu_local_irqs_pending Michael Clark
2018-04-27 22:33   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 24/35] RISC-V: Allow setting and clearing multiple irqs Michael Clark
2018-05-03 20:54   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 25/35] RISC-V: Move non-ops from op_helper to cpu_helper Michael Clark
2018-04-26 17:42   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 26/35] RISC-V: Update CSR and interrupt definitions Michael Clark
2018-05-03 20:56   ` Alistair Francis
2018-05-04  4:21     ` Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 27/35] RISC-V: Implement modular CSR helper interface Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 28/35] RISC-V: Implement atomic mip/sip CSR updates Michael Clark
2018-05-03 21:11   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 29/35] RISC-V: Implement existential predicates for CSRs Michael Clark
2018-05-03 21:21   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 30/35] RISC-V: Split out mstatus_fs from tb_flags Michael Clark
2018-05-03 21:22   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 31/35] RISC-V: Mark mstatus.fs dirty Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 32/35] RISC-V: Implement mstatus.TSR/TW/TVM Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 33/35] RISC-V: Add public API for the CSR dispatch table Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 34/35] RISC-V: Add hartid and \n to interrupt logging Michael Clark
2018-05-03 21:25   ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 35/35] RISC-V: Use riscv prefix consistently on cpu helpers Michael Clark
2018-04-26  1:42 ` [Qemu-devel] [PATCH v8 00/35] QEMU 2.13 Privileged ISA emulation updates Michael Clark
2018-04-26  2:01   ` Michael Clark
2018-04-26 18:22     ` Alistair Francis
2018-04-27  0:34       ` Michael Clark
2018-04-27 10:19         ` Peter Maydell
2018-04-27  0:35       ` Richard Henderson
2018-04-27  5:00         ` Michael Clark

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