* [PATCH 0/6] pinctrl: imx: add imx8qxp pinctrl support
@ 2018-04-27 19:01 ` Dong Aisheng
0 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2018-04-27 19:01 UTC (permalink / raw)
To: linux-gpio
Cc: aisheng.dong, dongas86, linus.walleij, stefan, linux-imx, kernel,
fabio.estevam, shawnguo, linux-arm-kernel
This patch series adds i.MX8QXP pinctrl support which is based
on the pad service provided by SCU firmware.
It depends on SCU APIs patch set.
The first three are minor preparation cleanups.
Dong Aisheng (6):
pinctrl: imx: fix unsigned check if nfuncs with less than or equal
zero
pinctrl: pinctrl-imx: improve the code comments of PIN_FUNC_ID
pinctrl: imx: use seq_puts() instead of seq_printf()
pinctrl: fsl: add scu based pinctrl support
dt-bindings: pinctrl: add imx8qxp pinctrl binding doc
pinctrl: imx: add imx8qxp driver
.../bindings/pinctrl/fsl,imx8qxp-pinctrl.txt | 39 ++
drivers/pinctrl/freescale/Kconfig | 11 +
drivers/pinctrl/freescale/Makefile | 2 +
drivers/pinctrl/freescale/pinctrl-imx.c | 421 +++++++-----
drivers/pinctrl/freescale/pinctrl-imx.h | 40 +-
drivers/pinctrl/freescale/pinctrl-imx8qxp.c | 232 +++++++
drivers/pinctrl/freescale/pinctrl-scu.c | 84 +++
include/dt-bindings/pinctrl/pads-imx8qxp.h | 751 +++++++++++++++++++++
8 files changed, 1412 insertions(+), 168 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt
create mode 100644 drivers/pinctrl/freescale/pinctrl-imx8qxp.c
create mode 100644 drivers/pinctrl/freescale/pinctrl-scu.c
create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h
--
2.7.4
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 0/6] pinctrl: imx: add imx8qxp pinctrl support
@ 2018-04-27 19:01 ` Dong Aisheng
0 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2018-04-27 19:01 UTC (permalink / raw)
To: linux-arm-kernel
This patch series adds i.MX8QXP pinctrl support which is based
on the pad service provided by SCU firmware.
It depends on SCU APIs patch set.
The first three are minor preparation cleanups.
Dong Aisheng (6):
pinctrl: imx: fix unsigned check if nfuncs with less than or equal
zero
pinctrl: pinctrl-imx: improve the code comments of PIN_FUNC_ID
pinctrl: imx: use seq_puts() instead of seq_printf()
pinctrl: fsl: add scu based pinctrl support
dt-bindings: pinctrl: add imx8qxp pinctrl binding doc
pinctrl: imx: add imx8qxp driver
.../bindings/pinctrl/fsl,imx8qxp-pinctrl.txt | 39 ++
drivers/pinctrl/freescale/Kconfig | 11 +
drivers/pinctrl/freescale/Makefile | 2 +
drivers/pinctrl/freescale/pinctrl-imx.c | 421 +++++++-----
drivers/pinctrl/freescale/pinctrl-imx.h | 40 +-
drivers/pinctrl/freescale/pinctrl-imx8qxp.c | 232 +++++++
drivers/pinctrl/freescale/pinctrl-scu.c | 84 +++
include/dt-bindings/pinctrl/pads-imx8qxp.h | 751 +++++++++++++++++++++
8 files changed, 1412 insertions(+), 168 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt
create mode 100644 drivers/pinctrl/freescale/pinctrl-imx8qxp.c
create mode 100644 drivers/pinctrl/freescale/pinctrl-scu.c
create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h
--
2.7.4
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 1/6] pinctrl: imx: fix unsigned check if nfuncs with less than or equal zero
2018-04-27 19:01 ` Dong Aisheng
@ 2018-04-27 19:01 ` Dong Aisheng
-1 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2018-04-27 19:01 UTC (permalink / raw)
To: linux-gpio
Cc: aisheng.dong, dongas86, linus.walleij, stefan, linux-imx, kernel,
fabio.estevam, shawnguo, linux-arm-kernel
The unsigned integer nfuncs is being error checked with a value less
or equal to zero; this is always false if of_get_child_count returns a
-ve for an error condition since nfuncs is not signed. Fix this by
making variables nfuncs and i signed integers.
Detected with Coccinelle:
drivers/pinctrl/freescale/pinctrl-imx.c:620:6-12: WARNING: Unsigned
expression compared with zero: nfuncs <= 0
Cc: Linus Walleij <linus.walleij@linaro.org>
Reported-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
drivers/pinctrl/freescale/pinctrl-imx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 24aaddd..77cd364 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -617,7 +617,7 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev,
nfuncs = 1;
} else {
nfuncs = of_get_child_count(np);
- if (nfuncs <= 0) {
+ if (nfuncs == 0) {
dev_err(&pdev->dev, "no functions defined\n");
return -EINVAL;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 1/6] pinctrl: imx: fix unsigned check if nfuncs with less than or equal zero
@ 2018-04-27 19:01 ` Dong Aisheng
0 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2018-04-27 19:01 UTC (permalink / raw)
To: linux-arm-kernel
The unsigned integer nfuncs is being error checked with a value less
or equal to zero; this is always false if of_get_child_count returns a
-ve for an error condition since nfuncs is not signed. Fix this by
making variables nfuncs and i signed integers.
Detected with Coccinelle:
drivers/pinctrl/freescale/pinctrl-imx.c:620:6-12: WARNING: Unsigned
expression compared with zero: nfuncs <= 0
Cc: Linus Walleij <linus.walleij@linaro.org>
Reported-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
drivers/pinctrl/freescale/pinctrl-imx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 24aaddd..77cd364 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -617,7 +617,7 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev,
nfuncs = 1;
} else {
nfuncs = of_get_child_count(np);
- if (nfuncs <= 0) {
+ if (nfuncs == 0) {
dev_err(&pdev->dev, "no functions defined\n");
return -EINVAL;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 2/6] pinctrl: pinctrl-imx: improve the code comments of PIN_FUNC_ID
2018-04-27 19:01 ` Dong Aisheng
@ 2018-04-27 19:01 ` Dong Aisheng
-1 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2018-04-27 19:01 UTC (permalink / raw)
To: linux-gpio
Cc: aisheng.dong, dongas86, Fabio Estevam, linus.walleij, stefan,
linux-imx, kernel, fabio.estevam, shawnguo, linux-arm-kernel
The current code comments of PIN_FUNC_ID actually is not true for
SHARE_MUX_CONF_REG case which should be a 4 u32 PIN_FUNC_ID.
Fix the comments and re-org it a bit for better extendibility
as we may add a different size for SCU based PIN_FUNC_ID later.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
drivers/pinctrl/freescale/pinctrl-imx.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 77cd364..ff6ca6a4 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -414,11 +414,18 @@ static const struct pinconf_ops imx_pinconf_ops = {
};
/*
- * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
- * 1 u32 CONFIG, so 24 types in total for each pin.
+ * Each pin represented in fsl,pins consists of a number of u32 PIN_FUNC_ID
+ * and 1 u32 CONFIG, the total size is PIN_FUNC_ID + CONFIG for each pin.
+ * For generic_pinconf case, there's no extra u32 CONFIG.
+ *
+ * PIN_FUNC_ID format:
+ * Default:
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ * SHARE_MUX_CONF_REG:
+ * <mux_conf_reg input_reg mux_mode input_val>
*/
#define FSL_PIN_SIZE 24
-#define SHARE_FSL_PIN_SIZE 20
+#define FSL_PIN_SHARE_SIZE 20
static int imx_pinctrl_parse_groups(struct device_node *np,
struct group_desc *grp,
@@ -434,7 +441,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
dev_dbg(ipctl->dev, "group(%d): %s\n", index, np->name);
if (info->flags & SHARE_MUX_CONF_REG)
- pin_size = SHARE_FSL_PIN_SIZE;
+ pin_size = FSL_PIN_SHARE_SIZE;
else
pin_size = FSL_PIN_SIZE;
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 2/6] pinctrl: pinctrl-imx: improve the code comments of PIN_FUNC_ID
@ 2018-04-27 19:01 ` Dong Aisheng
0 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2018-04-27 19:01 UTC (permalink / raw)
To: linux-arm-kernel
The current code comments of PIN_FUNC_ID actually is not true for
SHARE_MUX_CONF_REG case which should be a 4 u32 PIN_FUNC_ID.
Fix the comments and re-org it a bit for better extendibility
as we may add a different size for SCU based PIN_FUNC_ID later.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
drivers/pinctrl/freescale/pinctrl-imx.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 77cd364..ff6ca6a4 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -414,11 +414,18 @@ static const struct pinconf_ops imx_pinconf_ops = {
};
/*
- * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
- * 1 u32 CONFIG, so 24 types in total for each pin.
+ * Each pin represented in fsl,pins consists of a number of u32 PIN_FUNC_ID
+ * and 1 u32 CONFIG, the total size is PIN_FUNC_ID + CONFIG for each pin.
+ * For generic_pinconf case, there's no extra u32 CONFIG.
+ *
+ * PIN_FUNC_ID format:
+ * Default:
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ * SHARE_MUX_CONF_REG:
+ * <mux_conf_reg input_reg mux_mode input_val>
*/
#define FSL_PIN_SIZE 24
-#define SHARE_FSL_PIN_SIZE 20
+#define FSL_PIN_SHARE_SIZE 20
static int imx_pinctrl_parse_groups(struct device_node *np,
struct group_desc *grp,
@@ -434,7 +441,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
dev_dbg(ipctl->dev, "group(%d): %s\n", index, np->name);
if (info->flags & SHARE_MUX_CONF_REG)
- pin_size = SHARE_FSL_PIN_SIZE;
+ pin_size = FSL_PIN_SHARE_SIZE;
else
pin_size = FSL_PIN_SIZE;
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 3/6] pinctrl: imx: use seq_puts() instead of seq_printf()
2018-04-27 19:01 ` Dong Aisheng
@ 2018-04-27 19:01 ` Dong Aisheng
-1 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2018-04-27 19:01 UTC (permalink / raw)
To: linux-gpio
Cc: aisheng.dong, dongas86, Fabio Estevam, linus.walleij, stefan,
linux-imx, kernel, fabio.estevam, shawnguo, linux-arm-kernel
For a constant format without additional arguments, use seq_puts()
instead of seq_printf(). Also, it fixes the following checkpatch
warning.
WARNING: Prefer seq_puts to seq_printf
+ seq_printf(s, "N/A");
WARNING: Prefer seq_puts to seq_printf
+ seq_printf(s, "\n");
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
drivers/pinctrl/freescale/pinctrl-imx.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index ff6ca6a4..4e730c3 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -371,7 +371,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
unsigned long config;
if (!pin_reg || pin_reg->conf_reg == -1) {
- seq_printf(s, "N/A");
+ seq_puts(s, "N/A");
return;
}
@@ -390,7 +390,7 @@ static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
if (group > pctldev->num_groups)
return;
- seq_printf(s, "\n");
+ seq_puts(s, "\n");
grp = pinctrl_generic_get_group(pctldev, group);
if (!grp)
return;
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 3/6] pinctrl: imx: use seq_puts() instead of seq_printf()
@ 2018-04-27 19:01 ` Dong Aisheng
0 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2018-04-27 19:01 UTC (permalink / raw)
To: linux-arm-kernel
For a constant format without additional arguments, use seq_puts()
instead of seq_printf(). Also, it fixes the following checkpatch
warning.
WARNING: Prefer seq_puts to seq_printf
+ seq_printf(s, "N/A");
WARNING: Prefer seq_puts to seq_printf
+ seq_printf(s, "\n");
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
drivers/pinctrl/freescale/pinctrl-imx.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index ff6ca6a4..4e730c3 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -371,7 +371,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
unsigned long config;
if (!pin_reg || pin_reg->conf_reg == -1) {
- seq_printf(s, "N/A");
+ seq_puts(s, "N/A");
return;
}
@@ -390,7 +390,7 @@ static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
if (group > pctldev->num_groups)
return;
- seq_printf(s, "\n");
+ seq_puts(s, "\n");
grp = pinctrl_generic_get_group(pctldev, group);
if (!grp)
return;
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 4/6] pinctrl: fsl: add scu based pinctrl support
2018-04-27 19:01 ` Dong Aisheng
@ 2018-04-27 19:01 ` Dong Aisheng
-1 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2018-04-27 19:01 UTC (permalink / raw)
To: linux-gpio
Cc: aisheng.dong, dongas86, Fabio Estevam, linus.walleij, stefan,
linux-imx, kernel, fabio.estevam, shawnguo, linux-arm-kernel
Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller
that is responsible for controlling the pad setting of the IPs that
are present. Communication between the host processor running an OS
and the system controller happens through a SCU protocol.
This patch adds SCU protocol based pinctrl drivers.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
drivers/pinctrl/freescale/Kconfig | 4 +
drivers/pinctrl/freescale/Makefile | 1 +
drivers/pinctrl/freescale/pinctrl-imx.c | 402 +++++++++++++++++++-------------
drivers/pinctrl/freescale/pinctrl-imx.h | 40 +++-
drivers/pinctrl/freescale/pinctrl-scu.c | 84 +++++++
5 files changed, 369 insertions(+), 162 deletions(-)
create mode 100644 drivers/pinctrl/freescale/pinctrl-scu.c
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index 0d8ba1e..329e1a4 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -5,6 +5,10 @@ config PINCTRL_IMX
select GENERIC_PINCONF
select REGMAP
+config PINCTRL_IMX_SCU
+ bool
+ select PINCTRL_IMX
+
config PINCTRL_IMX1_CORE
bool
select PINMUX
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index 368be8c..1acd569 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
# Freescale pin control drivers
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
+obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
obj-$(CONFIG_PINCTRL_IMX21) += pinctrl-imx21.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 4e730c3..070b08c 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -62,9 +62,11 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
struct pinctrl_map **map, unsigned *num_maps)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct group_desc *grp;
struct pinctrl_map *new_map;
struct device_node *parent;
+ struct imx_pin *pin;
int map_num = 1;
int i, j;
@@ -79,11 +81,14 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
return -EINVAL;
}
- for (i = 0; i < grp->num_pins; i++) {
- struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
-
- if (!(pin->config & IMX_NO_PAD_CTL))
- map_num++;
+ if (info->flags & IMX_USE_SCU) {
+ map_num += grp->num_pins;
+ } else {
+ for (i = 0; i < grp->num_pins; i++) {
+ pin = &((struct imx_pin *)(grp->data))[i];
+ if (!(pin->config & IMX_NO_PAD_CTL))
+ map_num++;
+ }
}
new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
@@ -107,9 +112,8 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
/* create config map */
new_map++;
for (i = j = 0; i < grp->num_pins; i++) {
- struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
-
- if (!(pin->config & IMX_NO_PAD_CTL)) {
+ pin = &((struct imx_pin *)(grp->data))[i];
+ if (!(pin->config & IMX_NO_PAD_CTL) || (info->flags & IMX_USE_SCU)) {
new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
new_map[j].data.configs.group_or_pin =
pin_get_name(pctldev, pin->pin);
@@ -138,19 +142,95 @@ static const struct pinctrl_ops imx_pctrl_ops = {
.pin_dbg_show = imx_pin_dbg_show,
.dt_node_to_map = imx_dt_node_to_map,
.dt_free_map = imx_dt_free_map,
-
};
+static int imx_pmx_set_one_pin_mmio(struct imx_pinctrl *ipctl,
+ struct imx_pin *pin)
+{
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ const struct imx_pin_reg *pin_reg;
+ unsigned int pin_id;
+
+ pin_id = pin->pin;
+ pin_reg = &ipctl->pin_regs[pin_id];
+
+ if (pin_reg->mux_reg == -1) {
+ dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
+ info->pins[pin_id].name);
+ return 0;
+ }
+
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ u32 reg;
+
+ reg = readl(ipctl->base + pin_reg->mux_reg);
+ reg &= ~info->mux_mask;
+ reg |= (pin->mux_mode << info->mux_shift);
+ writel(reg, ipctl->base + pin_reg->mux_reg);
+ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+ pin_reg->mux_reg, reg);
+ } else {
+ writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
+ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+ pin_reg->mux_reg, pin->mux_mode);
+ }
+
+ /*
+ * If the select input value begins with 0xff, it's a quirky
+ * select input and the value should be interpreted as below.
+ * 31 23 15 7 0
+ * | 0xff | shift | width | select |
+ * It's used to work around the problem that the select
+ * input for some pin is not implemented in the select
+ * input register but in some general purpose register.
+ * We encode the select input value, width and shift of
+ * the bit field into input_val cell of pin function ID
+ * in device tree, and then decode them here for setting
+ * up the select input bits in general purpose register.
+ */
+ if (pin->input_val >> 24 == 0xff) {
+ u32 val = pin->input_val;
+ u8 select = val & 0xff;
+ u8 width = (val >> 8) & 0xff;
+ u8 shift = (val >> 16) & 0xff;
+ u32 mask = ((1 << width) - 1) << shift;
+ /*
+ * The input_reg[i] here is actually some IOMUXC general
+ * purpose register, not regular select input register.
+ */
+ val = readl(ipctl->base + pin->input_reg);
+ val &= ~mask;
+ val |= select << shift;
+ writel(val, ipctl->base + pin->input_reg);
+ } else if (pin->input_reg) {
+ /*
+ * Regular select input register can never be at offset
+ * 0, and we only print register value for regular case.
+ */
+ if (ipctl->input_sel_base)
+ writel(pin->input_val, ipctl->input_sel_base +
+ pin->input_reg);
+ else
+ writel(pin->input_val, ipctl->base +
+ pin->input_reg);
+ dev_dbg(ipctl->dev,
+ "==>select_input: offset 0x%x val 0x%x\n",
+ pin->input_reg, pin->input_val);
+ }
+
+ return 0;
+}
+
static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
- const struct imx_pin_reg *pin_reg;
- unsigned int npins, pin_id;
- int i;
- struct group_desc *grp = NULL;
- struct function_desc *func = NULL;
+ struct function_desc *func;
+ struct group_desc *grp;
+ struct imx_pin *pin;
+ unsigned int npins;
+ int i, err;
/*
* Configure the mux mode for each pin in the group for a specific
@@ -170,72 +250,16 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
func->name, grp->name);
for (i = 0; i < npins; i++) {
- struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
-
- pin_id = pin->pin;
- pin_reg = &ipctl->pin_regs[pin_id];
-
- if (pin_reg->mux_reg == -1) {
- dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
- info->pins[pin_id].name);
- continue;
- }
-
- if (info->flags & SHARE_MUX_CONF_REG) {
- u32 reg;
- reg = readl(ipctl->base + pin_reg->mux_reg);
- reg &= ~info->mux_mask;
- reg |= (pin->mux_mode << info->mux_shift);
- writel(reg, ipctl->base + pin_reg->mux_reg);
- dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
- pin_reg->mux_reg, reg);
- } else {
- writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
- dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
- pin_reg->mux_reg, pin->mux_mode);
- }
-
/*
- * If the select input value begins with 0xff, it's a quirky
- * select input and the value should be interpreted as below.
- * 31 23 15 7 0
- * | 0xff | shift | width | select |
- * It's used to work around the problem that the select
- * input for some pin is not implemented in the select
- * input register but in some general purpose register.
- * We encode the select input value, width and shift of
- * the bit field into input_val cell of pin function ID
- * in device tree, and then decode them here for setting
- * up the select input bits in general purpose register.
+ * For IMX_USE_SCU case, we postpone the mux setting
+ * until config is set as we can set them together
+ * in one IPC call
*/
- if (pin->input_val >> 24 == 0xff) {
- u32 val = pin->input_val;
- u8 select = val & 0xff;
- u8 width = (val >> 8) & 0xff;
- u8 shift = (val >> 16) & 0xff;
- u32 mask = ((1 << width) - 1) << shift;
- /*
- * The input_reg[i] here is actually some IOMUXC general
- * purpose register, not regular select input register.
- */
- val = readl(ipctl->base + pin->input_reg);
- val &= ~mask;
- val |= select << shift;
- writel(val, ipctl->base + pin->input_reg);
- } else if (pin->input_reg) {
- /*
- * Regular select input register can never be at offset
- * 0, and we only print register value for regular case.
- */
- if (ipctl->input_sel_base)
- writel(pin->input_val, ipctl->input_sel_base +
- pin->input_reg);
- else
- writel(pin->input_val, ipctl->base +
- pin->input_reg);
- dev_dbg(ipctl->dev,
- "==>select_input: offset 0x%x val 0x%x\n",
- pin->input_reg, pin->input_val);
+ pin = &((struct imx_pin *)(grp->data))[i];
+ if (!(info->flags & IMX_USE_SCU)) {
+ err = imx_pmx_set_one_pin_mmio(ipctl, pin);
+ if (err)
+ return err;
}
}
@@ -305,8 +329,8 @@ static u32 imx_pinconf_parse_generic_config(struct device_node *np,
return imx_pinconf_decode_generic_config(ipctl, configs, num_configs);
}
-static int imx_pinconf_get(struct pinctrl_dev *pctldev,
- unsigned pin_id, unsigned long *config)
+static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *config)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
@@ -326,9 +350,21 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
return 0;
}
-static int imx_pinconf_set(struct pinctrl_dev *pctldev,
- unsigned pin_id, unsigned long *configs,
- unsigned num_configs)
+static int imx_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *config)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+ if (info->flags & IMX_USE_SCU)
+ return imx_pinconf_get_scu(pctldev, pin_id, config);
+ else
+ return imx_pinconf_get_mmio(pctldev, pin_id, config);
+}
+
+static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
@@ -363,19 +399,48 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
return 0;
}
+static int imx_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+ if (info->flags & IMX_USE_SCU)
+ return imx_pinconf_set_scu(pctldev, pin_id,
+ configs, num_configs);
+ else
+ return imx_pinconf_set_mmio(pctldev, pin_id,
+ configs, num_configs);
+}
+
static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned pin_id)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ const struct imx_pin_reg *pin_reg;
unsigned long config;
+ int ret;
- if (!pin_reg || pin_reg->conf_reg == -1) {
- seq_puts(s, "N/A");
- return;
+ if (info->flags & IMX_USE_SCU) {
+ ret = imx_pinconf_get_scu(pctldev, pin_id, &config);
+ if (ret) {
+ dev_err(ipctl->dev, "failed to get %s pinconf\n",
+ pin_get_name(pctldev, pin_id));
+ seq_puts(s, "N/A");
+ return;
+ }
+ } else {
+ pin_reg = &ipctl->pin_regs[pin_id];
+ if (!pin_reg || pin_reg->conf_reg == -1) {
+ seq_puts(s, "N/A");
+ return;
+ }
+
+ config = readl(ipctl->base + pin_reg->conf_reg);
}
- config = readl(ipctl->base + pin_reg->conf_reg);
seq_printf(s, "0x%lx", config);
}
@@ -423,9 +488,62 @@ static const struct pinconf_ops imx_pinconf_ops = {
* <mux_reg conf_reg input_reg mux_mode input_val>
* SHARE_MUX_CONF_REG:
* <mux_conf_reg input_reg mux_mode input_val>
+ * IMX_USE_SCU:
+ * <pin_id mux_mode>
*/
#define FSL_PIN_SIZE 24
#define FSL_PIN_SHARE_SIZE 20
+#define FSL_SCU_PIN_SIZE 12
+
+static void imx_pinctrl_parse_pin_mmio(struct imx_pinctrl *ipctl,
+ unsigned int *pin_id, struct imx_pin *pin,
+ const __be32 **list_p,
+ struct device_node *np)
+{
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ struct imx_pin_reg *pin_reg;
+ const __be32 *list = *list_p;
+ u32 mux_reg, conf_reg;
+ u32 config;
+
+ mux_reg = be32_to_cpu(*list++);
+
+ if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
+ mux_reg = -1;
+
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ conf_reg = mux_reg;
+ } else {
+ conf_reg = be32_to_cpu(*list++);
+ if (!conf_reg)
+ conf_reg = -1;
+ }
+
+ *pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
+ pin_reg = &ipctl->pin_regs[*pin_id];
+ pin->pin = *pin_id;
+ pin_reg->mux_reg = mux_reg;
+ pin_reg->conf_reg = conf_reg;
+ pin->input_reg = be32_to_cpu(*list++);
+ pin->mux_mode = be32_to_cpu(*list++);
+ pin->input_val = be32_to_cpu(*list++);
+
+ if (info->generic_pinconf) {
+ /* generic pin config decoded */
+ pin->config = imx_pinconf_parse_generic_config(np, ipctl);
+ } else {
+ /* legacy pin config read from devicetree */
+ config = be32_to_cpu(*list++);
+
+ /* SION bit is in mux register */
+ if (config & IMX_PAD_SION)
+ pin->mux_mode |= IOMUXC_CONFIG_SION;
+ pin->config = config & ~IMX_PAD_SION;
+ }
+
+ dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name,
+ pin->mux_mode, pin->config);
+}
static int imx_pinctrl_parse_groups(struct device_node *np,
struct group_desc *grp,
@@ -433,14 +551,16 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
u32 index)
{
const struct imx_pinctrl_soc_info *info = ipctl->info;
+ struct imx_pin *pin;
int size, pin_size;
const __be32 *list;
int i;
- u32 config;
dev_dbg(ipctl->dev, "group(%d): %s\n", index, np->name);
- if (info->flags & SHARE_MUX_CONF_REG)
+ if (info->flags & IMX_USE_SCU)
+ pin_size = FSL_SCU_PIN_SIZE;
+ else if (info->flags & SHARE_MUX_CONF_REG)
pin_size = FSL_PIN_SHARE_SIZE;
else
pin_size = FSL_PIN_SIZE;
@@ -477,9 +597,6 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
return -EINVAL;
}
- /* first try to parse the generic pin config */
- config = imx_pinconf_parse_generic_config(np, ipctl);
-
grp->num_pins = size / pin_size;
grp->data = devm_kzalloc(ipctl->dev, grp->num_pins *
sizeof(struct imx_pin), GFP_KERNEL);
@@ -489,48 +606,13 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
return -ENOMEM;
for (i = 0; i < grp->num_pins; i++) {
- u32 mux_reg = be32_to_cpu(*list++);
- u32 conf_reg;
- unsigned int pin_id;
- struct imx_pin_reg *pin_reg;
- struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
-
- if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
- mux_reg = -1;
-
- if (info->flags & SHARE_MUX_CONF_REG) {
- conf_reg = mux_reg;
- } else {
- conf_reg = be32_to_cpu(*list++);
- if (!conf_reg)
- conf_reg = -1;
- }
-
- pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
- pin_reg = &ipctl->pin_regs[pin_id];
- pin->pin = pin_id;
- grp->pins[i] = pin_id;
- pin_reg->mux_reg = mux_reg;
- pin_reg->conf_reg = conf_reg;
- pin->input_reg = be32_to_cpu(*list++);
- pin->mux_mode = be32_to_cpu(*list++);
- pin->input_val = be32_to_cpu(*list++);
-
- if (info->generic_pinconf) {
- /* generic pin config decoded */
- pin->config = config;
- } else {
- /* legacy pin config read from devicetree */
- config = be32_to_cpu(*list++);
-
- /* SION bit is in mux register */
- if (config & IMX_PAD_SION)
- pin->mux_mode |= IOMUXC_CONFIG_SION;
- pin->config = config & ~IMX_PAD_SION;
- }
-
- dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
- pin->mux_mode, pin->config);
+ pin = &((struct imx_pin *)(grp->data))[i];
+ if (info->flags & IMX_USE_SCU)
+ imx_pinctrl_parse_pin_scu(ipctl, &grp->pins[i],
+ pin, &list);
+ else
+ imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i],
+ pin, &list, np);
}
return 0;
@@ -702,34 +784,36 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (!ipctl)
return -ENOMEM;
- ipctl->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*ipctl->pin_regs) *
- info->npins, GFP_KERNEL);
- if (!ipctl->pin_regs)
- return -ENOMEM;
+ if (!(info->flags & IMX_USE_SCU)) {
+ ipctl->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*ipctl->pin_regs) *
+ info->npins, GFP_KERNEL);
+ if (!ipctl->pin_regs)
+ return -ENOMEM;
- for (i = 0; i < info->npins; i++) {
- ipctl->pin_regs[i].mux_reg = -1;
- ipctl->pin_regs[i].conf_reg = -1;
- }
+ for (i = 0; i < info->npins; i++) {
+ ipctl->pin_regs[i].mux_reg = -1;
+ ipctl->pin_regs[i].conf_reg = -1;
+ }
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- ipctl->base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(ipctl->base))
- return PTR_ERR(ipctl->base);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ ipctl->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(ipctl->base))
+ return PTR_ERR(ipctl->base);
- if (of_property_read_bool(dev_np, "fsl,input-sel")) {
- np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
- if (!np) {
- dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
- return -EINVAL;
- }
+ if (of_property_read_bool(dev_np, "fsl,input-sel")) {
+ np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
+ if (!np) {
+ dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
+ return -EINVAL;
+ }
- ipctl->input_sel_base = of_iomap(np, 0);
- of_node_put(np);
- if (!ipctl->input_sel_base) {
- dev_err(&pdev->dev,
- "iomuxc input select base address not found\n");
- return -ENOMEM;
+ ipctl->input_sel_base = of_iomap(np, 0);
+ of_node_put(np);
+ if (!ipctl->input_sel_base) {
+ dev_err(&pdev->dev,
+ "iomuxc input select base address not found\n");
+ return -ENOMEM;
+ }
}
}
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
index 038e8c0..3313e0b 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -58,7 +58,7 @@ struct imx_cfg_params_decode {
};
struct imx_pinctrl_soc_info {
- const struct pinctrl_pin_desc *pins;
+ struct pinctrl_pin_desc *pins;
unsigned int npins;
unsigned int flags;
const char *gpr_compatible;
@@ -103,8 +103,9 @@ struct imx_pinctrl {
#define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \
{ .param = p, .mask = m, .shift = o, .invert = true, }
-#define SHARE_MUX_CONF_REG 0x1
-#define ZERO_OFFSET_VALID 0x2
+#define SHARE_MUX_CONF_REG BIT(0)
+#define ZERO_OFFSET_VALID BIT(1)
+#define IMX_USE_SCU BIT(2)
#define NO_MUX 0x0
#define NO_PAD 0x0
@@ -117,4 +118,37 @@ struct imx_pinctrl {
int imx_pinctrl_probe(struct platform_device *pdev,
const struct imx_pinctrl_soc_info *info);
+
+#ifdef CONFIG_PINCTRL_IMX_SCU
+#define BM_PAD_CTL_GP_ENABLE BIT(30)
+#define BM_PAD_CTL_IFMUX_ENABLE BIT(31)
+#define BP_PAD_CTL_IFMUX 27
+
+int imx_pinctrl_sc_ipc_init(struct platform_device *pdev);
+int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *config);
+int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *configs, unsigned num_configs);
+void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
+ unsigned int *pin_id, struct imx_pin *pin,
+ const __be32 **list_p);
+#else
+static inline int imx_pinconf_get_scu(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *config)
+{
+ return -EINVAL;
+}
+static inline int imx_pinconf_set_scu(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
+{
+ return -EINVAL;
+}
+static inline void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
+ unsigned int *pin_id,
+ struct imx_pin *pin,
+ const __be32 **list_p)
+{
+}
+#endif
#endif /* __DRIVERS_PINCTRL_IMX_H */
diff --git a/drivers/pinctrl/freescale/pinctrl-scu.c b/drivers/pinctrl/freescale/pinctrl-scu.c
new file mode 100644
index 0000000..ef43dc1
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-scu.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <linux/err.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+#include <soc/imx/sc/sci.h>
+
+#include "../core.h"
+#include "pinctrl-imx.h"
+
+sc_ipc_t pinctrl_ipc_handle;
+
+int imx_pinctrl_sc_ipc_init(struct platform_device *pdev)
+{
+ sc_err_t sci_err;
+
+ sci_err = sc_ipc_get_handle(&pinctrl_ipc_handle);
+ if (sci_err != SC_ERR_NONE) {
+ dev_err(&pdev->dev, "can't get sc ipc handle\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *config)
+{
+ sc_err_t err;
+
+ err = sc_pad_get(pinctrl_ipc_handle, pin_id, (unsigned int *)config);
+
+ if (err != SC_ERR_NONE)
+ return -EIO;
+
+ return 0;
+}
+
+int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *configs, unsigned num_configs)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ struct imx_pin *pin = info->pins[pin_id].drv_data;
+ sc_err_t err = SC_ERR_NONE;
+ uint32_t val;
+
+ WARN_ON(num_configs != 1);
+
+ val = *configs | BM_PAD_CTL_IFMUX_ENABLE | BM_PAD_CTL_GP_ENABLE;
+ val |= pin->mux_mode << BP_PAD_CTL_IFMUX;
+ err = sc_pad_set(pinctrl_ipc_handle, pin_id, val);
+
+ dev_dbg(ipctl->dev, "write: pin_id %u config 0x%lx val 0x%x\n",
+ pin_id, *configs, val);
+
+ if (err != SC_ERR_NONE)
+ return -EIO;
+
+ return 0;
+}
+
+void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
+ unsigned int *pin_id, struct imx_pin *pin,
+ const __be32 **list_p)
+{
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ const __be32 *list = *list_p;
+
+ pin->pin = be32_to_cpu(*list++);
+ *pin_id = pin->pin;
+ pin->mux_mode = be32_to_cpu(*list++);
+ pin->config = be32_to_cpu(*list++);
+ info->pins[pin->pin].drv_data = pin;
+ *list_p = list;
+
+ dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin->pin].name,
+ pin->mux_mode, pin->config);
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 4/6] pinctrl: fsl: add scu based pinctrl support
@ 2018-04-27 19:01 ` Dong Aisheng
0 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2018-04-27 19:01 UTC (permalink / raw)
To: linux-arm-kernel
Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller
that is responsible for controlling the pad setting of the IPs that
are present. Communication between the host processor running an OS
and the system controller happens through a SCU protocol.
This patch adds SCU protocol based pinctrl drivers.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
drivers/pinctrl/freescale/Kconfig | 4 +
drivers/pinctrl/freescale/Makefile | 1 +
drivers/pinctrl/freescale/pinctrl-imx.c | 402 +++++++++++++++++++-------------
drivers/pinctrl/freescale/pinctrl-imx.h | 40 +++-
drivers/pinctrl/freescale/pinctrl-scu.c | 84 +++++++
5 files changed, 369 insertions(+), 162 deletions(-)
create mode 100644 drivers/pinctrl/freescale/pinctrl-scu.c
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index 0d8ba1e..329e1a4 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -5,6 +5,10 @@ config PINCTRL_IMX
select GENERIC_PINCONF
select REGMAP
+config PINCTRL_IMX_SCU
+ bool
+ select PINCTRL_IMX
+
config PINCTRL_IMX1_CORE
bool
select PINMUX
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index 368be8c..1acd569 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
# Freescale pin control drivers
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
+obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
obj-$(CONFIG_PINCTRL_IMX21) += pinctrl-imx21.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 4e730c3..070b08c 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -62,9 +62,11 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
struct pinctrl_map **map, unsigned *num_maps)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct group_desc *grp;
struct pinctrl_map *new_map;
struct device_node *parent;
+ struct imx_pin *pin;
int map_num = 1;
int i, j;
@@ -79,11 +81,14 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
return -EINVAL;
}
- for (i = 0; i < grp->num_pins; i++) {
- struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
-
- if (!(pin->config & IMX_NO_PAD_CTL))
- map_num++;
+ if (info->flags & IMX_USE_SCU) {
+ map_num += grp->num_pins;
+ } else {
+ for (i = 0; i < grp->num_pins; i++) {
+ pin = &((struct imx_pin *)(grp->data))[i];
+ if (!(pin->config & IMX_NO_PAD_CTL))
+ map_num++;
+ }
}
new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
@@ -107,9 +112,8 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
/* create config map */
new_map++;
for (i = j = 0; i < grp->num_pins; i++) {
- struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
-
- if (!(pin->config & IMX_NO_PAD_CTL)) {
+ pin = &((struct imx_pin *)(grp->data))[i];
+ if (!(pin->config & IMX_NO_PAD_CTL) || (info->flags & IMX_USE_SCU)) {
new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
new_map[j].data.configs.group_or_pin =
pin_get_name(pctldev, pin->pin);
@@ -138,19 +142,95 @@ static const struct pinctrl_ops imx_pctrl_ops = {
.pin_dbg_show = imx_pin_dbg_show,
.dt_node_to_map = imx_dt_node_to_map,
.dt_free_map = imx_dt_free_map,
-
};
+static int imx_pmx_set_one_pin_mmio(struct imx_pinctrl *ipctl,
+ struct imx_pin *pin)
+{
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ const struct imx_pin_reg *pin_reg;
+ unsigned int pin_id;
+
+ pin_id = pin->pin;
+ pin_reg = &ipctl->pin_regs[pin_id];
+
+ if (pin_reg->mux_reg == -1) {
+ dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
+ info->pins[pin_id].name);
+ return 0;
+ }
+
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ u32 reg;
+
+ reg = readl(ipctl->base + pin_reg->mux_reg);
+ reg &= ~info->mux_mask;
+ reg |= (pin->mux_mode << info->mux_shift);
+ writel(reg, ipctl->base + pin_reg->mux_reg);
+ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+ pin_reg->mux_reg, reg);
+ } else {
+ writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
+ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+ pin_reg->mux_reg, pin->mux_mode);
+ }
+
+ /*
+ * If the select input value begins with 0xff, it's a quirky
+ * select input and the value should be interpreted as below.
+ * 31 23 15 7 0
+ * | 0xff | shift | width | select |
+ * It's used to work around the problem that the select
+ * input for some pin is not implemented in the select
+ * input register but in some general purpose register.
+ * We encode the select input value, width and shift of
+ * the bit field into input_val cell of pin function ID
+ * in device tree, and then decode them here for setting
+ * up the select input bits in general purpose register.
+ */
+ if (pin->input_val >> 24 == 0xff) {
+ u32 val = pin->input_val;
+ u8 select = val & 0xff;
+ u8 width = (val >> 8) & 0xff;
+ u8 shift = (val >> 16) & 0xff;
+ u32 mask = ((1 << width) - 1) << shift;
+ /*
+ * The input_reg[i] here is actually some IOMUXC general
+ * purpose register, not regular select input register.
+ */
+ val = readl(ipctl->base + pin->input_reg);
+ val &= ~mask;
+ val |= select << shift;
+ writel(val, ipctl->base + pin->input_reg);
+ } else if (pin->input_reg) {
+ /*
+ * Regular select input register can never be at offset
+ * 0, and we only print register value for regular case.
+ */
+ if (ipctl->input_sel_base)
+ writel(pin->input_val, ipctl->input_sel_base +
+ pin->input_reg);
+ else
+ writel(pin->input_val, ipctl->base +
+ pin->input_reg);
+ dev_dbg(ipctl->dev,
+ "==>select_input: offset 0x%x val 0x%x\n",
+ pin->input_reg, pin->input_val);
+ }
+
+ return 0;
+}
+
static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
- const struct imx_pin_reg *pin_reg;
- unsigned int npins, pin_id;
- int i;
- struct group_desc *grp = NULL;
- struct function_desc *func = NULL;
+ struct function_desc *func;
+ struct group_desc *grp;
+ struct imx_pin *pin;
+ unsigned int npins;
+ int i, err;
/*
* Configure the mux mode for each pin in the group for a specific
@@ -170,72 +250,16 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
func->name, grp->name);
for (i = 0; i < npins; i++) {
- struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
-
- pin_id = pin->pin;
- pin_reg = &ipctl->pin_regs[pin_id];
-
- if (pin_reg->mux_reg == -1) {
- dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
- info->pins[pin_id].name);
- continue;
- }
-
- if (info->flags & SHARE_MUX_CONF_REG) {
- u32 reg;
- reg = readl(ipctl->base + pin_reg->mux_reg);
- reg &= ~info->mux_mask;
- reg |= (pin->mux_mode << info->mux_shift);
- writel(reg, ipctl->base + pin_reg->mux_reg);
- dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
- pin_reg->mux_reg, reg);
- } else {
- writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
- dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
- pin_reg->mux_reg, pin->mux_mode);
- }
-
/*
- * If the select input value begins with 0xff, it's a quirky
- * select input and the value should be interpreted as below.
- * 31 23 15 7 0
- * | 0xff | shift | width | select |
- * It's used to work around the problem that the select
- * input for some pin is not implemented in the select
- * input register but in some general purpose register.
- * We encode the select input value, width and shift of
- * the bit field into input_val cell of pin function ID
- * in device tree, and then decode them here for setting
- * up the select input bits in general purpose register.
+ * For IMX_USE_SCU case, we postpone the mux setting
+ * until config is set as we can set them together
+ * in one IPC call
*/
- if (pin->input_val >> 24 == 0xff) {
- u32 val = pin->input_val;
- u8 select = val & 0xff;
- u8 width = (val >> 8) & 0xff;
- u8 shift = (val >> 16) & 0xff;
- u32 mask = ((1 << width) - 1) << shift;
- /*
- * The input_reg[i] here is actually some IOMUXC general
- * purpose register, not regular select input register.
- */
- val = readl(ipctl->base + pin->input_reg);
- val &= ~mask;
- val |= select << shift;
- writel(val, ipctl->base + pin->input_reg);
- } else if (pin->input_reg) {
- /*
- * Regular select input register can never be at offset
- * 0, and we only print register value for regular case.
- */
- if (ipctl->input_sel_base)
- writel(pin->input_val, ipctl->input_sel_base +
- pin->input_reg);
- else
- writel(pin->input_val, ipctl->base +
- pin->input_reg);
- dev_dbg(ipctl->dev,
- "==>select_input: offset 0x%x val 0x%x\n",
- pin->input_reg, pin->input_val);
+ pin = &((struct imx_pin *)(grp->data))[i];
+ if (!(info->flags & IMX_USE_SCU)) {
+ err = imx_pmx_set_one_pin_mmio(ipctl, pin);
+ if (err)
+ return err;
}
}
@@ -305,8 +329,8 @@ static u32 imx_pinconf_parse_generic_config(struct device_node *np,
return imx_pinconf_decode_generic_config(ipctl, configs, num_configs);
}
-static int imx_pinconf_get(struct pinctrl_dev *pctldev,
- unsigned pin_id, unsigned long *config)
+static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *config)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
@@ -326,9 +350,21 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
return 0;
}
-static int imx_pinconf_set(struct pinctrl_dev *pctldev,
- unsigned pin_id, unsigned long *configs,
- unsigned num_configs)
+static int imx_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *config)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+ if (info->flags & IMX_USE_SCU)
+ return imx_pinconf_get_scu(pctldev, pin_id, config);
+ else
+ return imx_pinconf_get_mmio(pctldev, pin_id, config);
+}
+
+static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
@@ -363,19 +399,48 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
return 0;
}
+static int imx_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+ if (info->flags & IMX_USE_SCU)
+ return imx_pinconf_set_scu(pctldev, pin_id,
+ configs, num_configs);
+ else
+ return imx_pinconf_set_mmio(pctldev, pin_id,
+ configs, num_configs);
+}
+
static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned pin_id)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ const struct imx_pin_reg *pin_reg;
unsigned long config;
+ int ret;
- if (!pin_reg || pin_reg->conf_reg == -1) {
- seq_puts(s, "N/A");
- return;
+ if (info->flags & IMX_USE_SCU) {
+ ret = imx_pinconf_get_scu(pctldev, pin_id, &config);
+ if (ret) {
+ dev_err(ipctl->dev, "failed to get %s pinconf\n",
+ pin_get_name(pctldev, pin_id));
+ seq_puts(s, "N/A");
+ return;
+ }
+ } else {
+ pin_reg = &ipctl->pin_regs[pin_id];
+ if (!pin_reg || pin_reg->conf_reg == -1) {
+ seq_puts(s, "N/A");
+ return;
+ }
+
+ config = readl(ipctl->base + pin_reg->conf_reg);
}
- config = readl(ipctl->base + pin_reg->conf_reg);
seq_printf(s, "0x%lx", config);
}
@@ -423,9 +488,62 @@ static const struct pinconf_ops imx_pinconf_ops = {
* <mux_reg conf_reg input_reg mux_mode input_val>
* SHARE_MUX_CONF_REG:
* <mux_conf_reg input_reg mux_mode input_val>
+ * IMX_USE_SCU:
+ * <pin_id mux_mode>
*/
#define FSL_PIN_SIZE 24
#define FSL_PIN_SHARE_SIZE 20
+#define FSL_SCU_PIN_SIZE 12
+
+static void imx_pinctrl_parse_pin_mmio(struct imx_pinctrl *ipctl,
+ unsigned int *pin_id, struct imx_pin *pin,
+ const __be32 **list_p,
+ struct device_node *np)
+{
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ struct imx_pin_reg *pin_reg;
+ const __be32 *list = *list_p;
+ u32 mux_reg, conf_reg;
+ u32 config;
+
+ mux_reg = be32_to_cpu(*list++);
+
+ if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
+ mux_reg = -1;
+
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ conf_reg = mux_reg;
+ } else {
+ conf_reg = be32_to_cpu(*list++);
+ if (!conf_reg)
+ conf_reg = -1;
+ }
+
+ *pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
+ pin_reg = &ipctl->pin_regs[*pin_id];
+ pin->pin = *pin_id;
+ pin_reg->mux_reg = mux_reg;
+ pin_reg->conf_reg = conf_reg;
+ pin->input_reg = be32_to_cpu(*list++);
+ pin->mux_mode = be32_to_cpu(*list++);
+ pin->input_val = be32_to_cpu(*list++);
+
+ if (info->generic_pinconf) {
+ /* generic pin config decoded */
+ pin->config = imx_pinconf_parse_generic_config(np, ipctl);
+ } else {
+ /* legacy pin config read from devicetree */
+ config = be32_to_cpu(*list++);
+
+ /* SION bit is in mux register */
+ if (config & IMX_PAD_SION)
+ pin->mux_mode |= IOMUXC_CONFIG_SION;
+ pin->config = config & ~IMX_PAD_SION;
+ }
+
+ dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name,
+ pin->mux_mode, pin->config);
+}
static int imx_pinctrl_parse_groups(struct device_node *np,
struct group_desc *grp,
@@ -433,14 +551,16 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
u32 index)
{
const struct imx_pinctrl_soc_info *info = ipctl->info;
+ struct imx_pin *pin;
int size, pin_size;
const __be32 *list;
int i;
- u32 config;
dev_dbg(ipctl->dev, "group(%d): %s\n", index, np->name);
- if (info->flags & SHARE_MUX_CONF_REG)
+ if (info->flags & IMX_USE_SCU)
+ pin_size = FSL_SCU_PIN_SIZE;
+ else if (info->flags & SHARE_MUX_CONF_REG)
pin_size = FSL_PIN_SHARE_SIZE;
else
pin_size = FSL_PIN_SIZE;
@@ -477,9 +597,6 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
return -EINVAL;
}
- /* first try to parse the generic pin config */
- config = imx_pinconf_parse_generic_config(np, ipctl);
-
grp->num_pins = size / pin_size;
grp->data = devm_kzalloc(ipctl->dev, grp->num_pins *
sizeof(struct imx_pin), GFP_KERNEL);
@@ -489,48 +606,13 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
return -ENOMEM;
for (i = 0; i < grp->num_pins; i++) {
- u32 mux_reg = be32_to_cpu(*list++);
- u32 conf_reg;
- unsigned int pin_id;
- struct imx_pin_reg *pin_reg;
- struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
-
- if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
- mux_reg = -1;
-
- if (info->flags & SHARE_MUX_CONF_REG) {
- conf_reg = mux_reg;
- } else {
- conf_reg = be32_to_cpu(*list++);
- if (!conf_reg)
- conf_reg = -1;
- }
-
- pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
- pin_reg = &ipctl->pin_regs[pin_id];
- pin->pin = pin_id;
- grp->pins[i] = pin_id;
- pin_reg->mux_reg = mux_reg;
- pin_reg->conf_reg = conf_reg;
- pin->input_reg = be32_to_cpu(*list++);
- pin->mux_mode = be32_to_cpu(*list++);
- pin->input_val = be32_to_cpu(*list++);
-
- if (info->generic_pinconf) {
- /* generic pin config decoded */
- pin->config = config;
- } else {
- /* legacy pin config read from devicetree */
- config = be32_to_cpu(*list++);
-
- /* SION bit is in mux register */
- if (config & IMX_PAD_SION)
- pin->mux_mode |= IOMUXC_CONFIG_SION;
- pin->config = config & ~IMX_PAD_SION;
- }
-
- dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
- pin->mux_mode, pin->config);
+ pin = &((struct imx_pin *)(grp->data))[i];
+ if (info->flags & IMX_USE_SCU)
+ imx_pinctrl_parse_pin_scu(ipctl, &grp->pins[i],
+ pin, &list);
+ else
+ imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i],
+ pin, &list, np);
}
return 0;
@@ -702,34 +784,36 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (!ipctl)
return -ENOMEM;
- ipctl->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*ipctl->pin_regs) *
- info->npins, GFP_KERNEL);
- if (!ipctl->pin_regs)
- return -ENOMEM;
+ if (!(info->flags & IMX_USE_SCU)) {
+ ipctl->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*ipctl->pin_regs) *
+ info->npins, GFP_KERNEL);
+ if (!ipctl->pin_regs)
+ return -ENOMEM;
- for (i = 0; i < info->npins; i++) {
- ipctl->pin_regs[i].mux_reg = -1;
- ipctl->pin_regs[i].conf_reg = -1;
- }
+ for (i = 0; i < info->npins; i++) {
+ ipctl->pin_regs[i].mux_reg = -1;
+ ipctl->pin_regs[i].conf_reg = -1;
+ }
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- ipctl->base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(ipctl->base))
- return PTR_ERR(ipctl->base);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ ipctl->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(ipctl->base))
+ return PTR_ERR(ipctl->base);
- if (of_property_read_bool(dev_np, "fsl,input-sel")) {
- np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
- if (!np) {
- dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
- return -EINVAL;
- }
+ if (of_property_read_bool(dev_np, "fsl,input-sel")) {
+ np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
+ if (!np) {
+ dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
+ return -EINVAL;
+ }
- ipctl->input_sel_base = of_iomap(np, 0);
- of_node_put(np);
- if (!ipctl->input_sel_base) {
- dev_err(&pdev->dev,
- "iomuxc input select base address not found\n");
- return -ENOMEM;
+ ipctl->input_sel_base = of_iomap(np, 0);
+ of_node_put(np);
+ if (!ipctl->input_sel_base) {
+ dev_err(&pdev->dev,
+ "iomuxc input select base address not found\n");
+ return -ENOMEM;
+ }
}
}
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
index 038e8c0..3313e0b 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -58,7 +58,7 @@ struct imx_cfg_params_decode {
};
struct imx_pinctrl_soc_info {
- const struct pinctrl_pin_desc *pins;
+ struct pinctrl_pin_desc *pins;
unsigned int npins;
unsigned int flags;
const char *gpr_compatible;
@@ -103,8 +103,9 @@ struct imx_pinctrl {
#define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \
{ .param = p, .mask = m, .shift = o, .invert = true, }
-#define SHARE_MUX_CONF_REG 0x1
-#define ZERO_OFFSET_VALID 0x2
+#define SHARE_MUX_CONF_REG BIT(0)
+#define ZERO_OFFSET_VALID BIT(1)
+#define IMX_USE_SCU BIT(2)
#define NO_MUX 0x0
#define NO_PAD 0x0
@@ -117,4 +118,37 @@ struct imx_pinctrl {
int imx_pinctrl_probe(struct platform_device *pdev,
const struct imx_pinctrl_soc_info *info);
+
+#ifdef CONFIG_PINCTRL_IMX_SCU
+#define BM_PAD_CTL_GP_ENABLE BIT(30)
+#define BM_PAD_CTL_IFMUX_ENABLE BIT(31)
+#define BP_PAD_CTL_IFMUX 27
+
+int imx_pinctrl_sc_ipc_init(struct platform_device *pdev);
+int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *config);
+int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *configs, unsigned num_configs);
+void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
+ unsigned int *pin_id, struct imx_pin *pin,
+ const __be32 **list_p);
+#else
+static inline int imx_pinconf_get_scu(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *config)
+{
+ return -EINVAL;
+}
+static inline int imx_pinconf_set_scu(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
+{
+ return -EINVAL;
+}
+static inline void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
+ unsigned int *pin_id,
+ struct imx_pin *pin,
+ const __be32 **list_p)
+{
+}
+#endif
#endif /* __DRIVERS_PINCTRL_IMX_H */
diff --git a/drivers/pinctrl/freescale/pinctrl-scu.c b/drivers/pinctrl/freescale/pinctrl-scu.c
new file mode 100644
index 0000000..ef43dc1
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-scu.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <linux/err.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+#include <soc/imx/sc/sci.h>
+
+#include "../core.h"
+#include "pinctrl-imx.h"
+
+sc_ipc_t pinctrl_ipc_handle;
+
+int imx_pinctrl_sc_ipc_init(struct platform_device *pdev)
+{
+ sc_err_t sci_err;
+
+ sci_err = sc_ipc_get_handle(&pinctrl_ipc_handle);
+ if (sci_err != SC_ERR_NONE) {
+ dev_err(&pdev->dev, "can't get sc ipc handle\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *config)
+{
+ sc_err_t err;
+
+ err = sc_pad_get(pinctrl_ipc_handle, pin_id, (unsigned int *)config);
+
+ if (err != SC_ERR_NONE)
+ return -EIO;
+
+ return 0;
+}
+
+int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *configs, unsigned num_configs)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ struct imx_pin *pin = info->pins[pin_id].drv_data;
+ sc_err_t err = SC_ERR_NONE;
+ uint32_t val;
+
+ WARN_ON(num_configs != 1);
+
+ val = *configs | BM_PAD_CTL_IFMUX_ENABLE | BM_PAD_CTL_GP_ENABLE;
+ val |= pin->mux_mode << BP_PAD_CTL_IFMUX;
+ err = sc_pad_set(pinctrl_ipc_handle, pin_id, val);
+
+ dev_dbg(ipctl->dev, "write: pin_id %u config 0x%lx val 0x%x\n",
+ pin_id, *configs, val);
+
+ if (err != SC_ERR_NONE)
+ return -EIO;
+
+ return 0;
+}
+
+void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
+ unsigned int *pin_id, struct imx_pin *pin,
+ const __be32 **list_p)
+{
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ const __be32 *list = *list_p;
+
+ pin->pin = be32_to_cpu(*list++);
+ *pin_id = pin->pin;
+ pin->mux_mode = be32_to_cpu(*list++);
+ pin->config = be32_to_cpu(*list++);
+ info->pins[pin->pin].drv_data = pin;
+ *list_p = list;
+
+ dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin->pin].name,
+ pin->mux_mode, pin->config);
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5/6] dt-bindings: pinctrl: add imx8qxp pinctrl binding doc
2018-04-27 19:01 ` Dong Aisheng
@ 2018-04-27 19:01 ` Dong Aisheng
-1 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2018-04-27 19:01 UTC (permalink / raw)
To: linux-gpio
Cc: aisheng.dong, Mark Rutland, dongas86, devicetree, Fabio Estevam,
linus.walleij, stefan, Rob Herring, linux-imx, kernel,
fabio.estevam, shawnguo, linux-arm-kernel
Add imx8qxp pinctrl binding doc.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
Note: there's a checkpatch error as follows:
ERROR: Macros with complex values should be enclosed in parentheses
+#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0
However, this is the intended format. Seems checkpatch did not recognize
it well. Not sure if we could accept it.
---
.../bindings/pinctrl/fsl,imx8qxp-pinctrl.txt | 39 ++
include/dt-bindings/pinctrl/pads-imx8qxp.h | 751 +++++++++++++++++++++
2 files changed, 790 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt
create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt
new file mode 100644
index 0000000..62c0f55
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt
@@ -0,0 +1,39 @@
+* NXP i.MX8QXP IOMUX Controller
+
+MX8QXP contains a system controller that is responsible for controlling
+the pad setting of the IPs that are present. Communication between the
+host processor running an OS and the system controller happens through
+a SCU protocol.
+
+Please also refer to fsl,imx-pinctrl.txt in this directory for i.MX common
+pinctrl binding.
+
+=== Pin Controller Node ===
+
+Required properties:
+- compatible: "fsl,imx8qxp-iomuxc"
+
+=== Pin Configuration Node ===
+- fsl,pins: Each entry consists of 3 integers which represents the mux and
+ config setting for one pin. The first 2 integers <pin_id mux_mode>
+ are specified using a PIN_FUNC_ID macro, which can be found
+ in <dt-bindings/pinctrl/pads-imx8qxp.h>. The last integer CONFIG
+ is the pad setting value like pull-up on this pin.
+ Please refer to i.MX8QXP Reference Manual for detailed
+ CONFIG settings.
+
+Examples:
+#include <dt-bindings/pinctrl/pads-imx8qxp.h>
+
+/* Pin Controller Node */
+iomuxc: iomuxc {
+ compatible = "fsl,imx8qxp-iomuxc";
+
+ /* Pin Configuration Node */
+ pinctrl_lpuart0: lpuart0grp {
+ fsl,pins = <
+ SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
+ SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
+ >;
+ };
+};
diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h
new file mode 100644
index 0000000..8f477c3
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h
@@ -0,0 +1,751 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ */
+
+#ifndef _SC_PADS_H
+#define _SC_PADS_H
+
+/* pin id */
+#define SC_P_PCIE_CTRL0_PERST_B 0
+#define SC_P_PCIE_CTRL0_CLKREQ_B 1
+#define SC_P_PCIE_CTRL0_WAKE_B 2
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3
+#define SC_P_USB_SS3_TC0 4
+#define SC_P_USB_SS3_TC1 5
+#define SC_P_USB_SS3_TC2 6
+#define SC_P_USB_SS3_TC3 7
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8
+#define SC_P_EMMC0_CLK 9
+#define SC_P_EMMC0_CMD 10
+#define SC_P_EMMC0_DATA0 11
+#define SC_P_EMMC0_DATA1 12
+#define SC_P_EMMC0_DATA2 13
+#define SC_P_EMMC0_DATA3 14
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15
+#define SC_P_EMMC0_DATA4 16
+#define SC_P_EMMC0_DATA5 17
+#define SC_P_EMMC0_DATA6 18
+#define SC_P_EMMC0_DATA7 19
+#define SC_P_EMMC0_STROBE 20
+#define SC_P_EMMC0_RESET_B 21
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22
+#define SC_P_USDHC1_RESET_B 23
+#define SC_P_USDHC1_VSELECT 24
+#define SC_P_CTL_NAND_RE_P_N 25
+#define SC_P_USDHC1_WP 26
+#define SC_P_USDHC1_CD_B 27
+#define SC_P_CTL_NAND_DQS_P_N 28
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29
+#define SC_P_USDHC1_CLK 30
+#define SC_P_USDHC1_CMD 31
+#define SC_P_USDHC1_DATA0 32
+#define SC_P_USDHC1_DATA1 33
+#define SC_P_USDHC1_DATA2 34
+#define SC_P_USDHC1_DATA3 35
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36
+#define SC_P_ENET0_RGMII_TXC 37
+#define SC_P_ENET0_RGMII_TX_CTL 38
+#define SC_P_ENET0_RGMII_TXD0 39
+#define SC_P_ENET0_RGMII_TXD1 40
+#define SC_P_ENET0_RGMII_TXD2 41
+#define SC_P_ENET0_RGMII_TXD3 42
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43
+#define SC_P_ENET0_RGMII_RXC 44
+#define SC_P_ENET0_RGMII_RX_CTL 45
+#define SC_P_ENET0_RGMII_RXD0 46
+#define SC_P_ENET0_RGMII_RXD1 47
+#define SC_P_ENET0_RGMII_RXD2 48
+#define SC_P_ENET0_RGMII_RXD3 49
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50
+#define SC_P_ENET0_REFCLK_125M_25M 51
+#define SC_P_ENET0_MDIO 52
+#define SC_P_ENET0_MDC 53
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54
+#define SC_P_ESAI0_FSR 55
+#define SC_P_ESAI0_FST 56
+#define SC_P_ESAI0_SCKR 57
+#define SC_P_ESAI0_SCKT 58
+#define SC_P_ESAI0_TX0 59
+#define SC_P_ESAI0_TX1 60
+#define SC_P_ESAI0_TX2_RX3 61
+#define SC_P_ESAI0_TX3_RX2 62
+#define SC_P_ESAI0_TX4_RX1 63
+#define SC_P_ESAI0_TX5_RX0 64
+#define SC_P_SPDIF0_RX 65
+#define SC_P_SPDIF0_TX 66
+#define SC_P_SPDIF0_EXT_CLK 67
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68
+#define SC_P_SPI3_SCK 69
+#define SC_P_SPI3_SDO 70
+#define SC_P_SPI3_SDI 71
+#define SC_P_SPI3_CS0 72
+#define SC_P_SPI3_CS1 73
+#define SC_P_MCLK_IN1 74
+#define SC_P_MCLK_IN0 75
+#define SC_P_MCLK_OUT0 76
+#define SC_P_UART1_TX 77
+#define SC_P_UART1_RX 78
+#define SC_P_UART1_RTS_B 79
+#define SC_P_UART1_CTS_B 80
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81
+#define SC_P_SAI0_TXD 82
+#define SC_P_SAI0_TXC 83
+#define SC_P_SAI0_RXD 84
+#define SC_P_SAI0_TXFS 85
+#define SC_P_SAI1_RXD 86
+#define SC_P_SAI1_RXC 87
+#define SC_P_SAI1_RXFS 88
+#define SC_P_SPI2_CS0 89
+#define SC_P_SPI2_SDO 90
+#define SC_P_SPI2_SDI 91
+#define SC_P_SPI2_SCK 92
+#define SC_P_SPI0_SCK 93
+#define SC_P_SPI0_SDI 94
+#define SC_P_SPI0_SDO 95
+#define SC_P_SPI0_CS1 96
+#define SC_P_SPI0_CS0 97
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98
+#define SC_P_ADC_IN1 99
+#define SC_P_ADC_IN0 100
+#define SC_P_ADC_IN3 101
+#define SC_P_ADC_IN2 102
+#define SC_P_ADC_IN5 103
+#define SC_P_ADC_IN4 104
+#define SC_P_FLEXCAN0_RX 105
+#define SC_P_FLEXCAN0_TX 106
+#define SC_P_FLEXCAN1_RX 107
+#define SC_P_FLEXCAN1_TX 108
+#define SC_P_FLEXCAN2_RX 109
+#define SC_P_FLEXCAN2_TX 110
+#define SC_P_UART0_RX 111
+#define SC_P_UART0_TX 112
+#define SC_P_UART2_TX 113
+#define SC_P_UART2_RX 114
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115
+#define SC_P_MIPI_DSI0_I2C0_SCL 116
+#define SC_P_MIPI_DSI0_I2C0_SDA 117
+#define SC_P_MIPI_DSI0_GPIO0_00 118
+#define SC_P_MIPI_DSI0_GPIO0_01 119
+#define SC_P_MIPI_DSI1_I2C0_SCL 120
+#define SC_P_MIPI_DSI1_I2C0_SDA 121
+#define SC_P_MIPI_DSI1_GPIO0_00 122
+#define SC_P_MIPI_DSI1_GPIO0_01 123
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124
+#define SC_P_JTAG_TRST_B 125
+#define SC_P_PMIC_I2C_SCL 126
+#define SC_P_PMIC_I2C_SDA 127
+#define SC_P_PMIC_INT_B 128
+#define SC_P_SCU_GPIO0_00 129
+#define SC_P_SCU_GPIO0_01 130
+#define SC_P_SCU_PMIC_STANDBY 131
+#define SC_P_SCU_BOOT_MODE0 132
+#define SC_P_SCU_BOOT_MODE1 133
+#define SC_P_SCU_BOOT_MODE2 134
+#define SC_P_SCU_BOOT_MODE3 135
+#define SC_P_CSI_D00 136
+#define SC_P_CSI_D01 137
+#define SC_P_CSI_D02 138
+#define SC_P_CSI_D03 139
+#define SC_P_CSI_D04 140
+#define SC_P_CSI_D05 141
+#define SC_P_CSI_D06 142
+#define SC_P_CSI_D07 143
+#define SC_P_CSI_HSYNC 144
+#define SC_P_CSI_VSYNC 145
+#define SC_P_CSI_PCLK 146
+#define SC_P_CSI_MCLK 147
+#define SC_P_CSI_EN 148
+#define SC_P_CSI_RESET 149
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150
+#define SC_P_MIPI_CSI0_MCLK_OUT 151
+#define SC_P_MIPI_CSI0_I2C0_SCL 152
+#define SC_P_MIPI_CSI0_I2C0_SDA 153
+#define SC_P_MIPI_CSI0_GPIO0_01 154
+#define SC_P_MIPI_CSI0_GPIO0_00 155
+#define SC_P_QSPI0A_DATA0 156
+#define SC_P_QSPI0A_DATA1 157
+#define SC_P_QSPI0A_DATA2 158
+#define SC_P_QSPI0A_DATA3 159
+#define SC_P_QSPI0A_DQS 160
+#define SC_P_QSPI0A_SS0_B 161
+#define SC_P_QSPI0A_SS1_B 162
+#define SC_P_QSPI0A_SCLK 163
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164
+#define SC_P_QSPI0B_SCLK 165
+#define SC_P_QSPI0B_DATA0 166
+#define SC_P_QSPI0B_DATA1 167
+#define SC_P_QSPI0B_DATA2 168
+#define SC_P_QSPI0B_DATA3 169
+#define SC_P_QSPI0B_DQS 170
+#define SC_P_QSPI0B_SS0_B 171
+#define SC_P_QSPI0B_SS1_B 172
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173
+
+/*
+ * format: <pin_id mux_mode>
+ */
+#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0
+#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 SC_P_PCIE_CTRL0_PERST_B 4
+#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B SC_P_PCIE_CTRL0_CLKREQ_B 0
+#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 SC_P_PCIE_CTRL0_CLKREQ_B 4
+#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B SC_P_PCIE_CTRL0_WAKE_B 0
+#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 SC_P_PCIE_CTRL0_WAKE_B 4
+#define SC_P_USB_SS3_TC0_ADMA_I2C1_SCL SC_P_USB_SS3_TC0 0
+#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR SC_P_USB_SS3_TC0 1
+#define SC_P_USB_SS3_TC0_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC0 2
+#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 SC_P_USB_SS3_TC0 4
+#define SC_P_USB_SS3_TC1_ADMA_I2C1_SCL SC_P_USB_SS3_TC1 0
+#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC1 1
+#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 SC_P_USB_SS3_TC1 4
+#define SC_P_USB_SS3_TC2_ADMA_I2C1_SDA SC_P_USB_SS3_TC2 0
+#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC SC_P_USB_SS3_TC2 1
+#define SC_P_USB_SS3_TC2_CONN_USB_OTG2_OC SC_P_USB_SS3_TC2 2
+#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 SC_P_USB_SS3_TC2 4
+#define SC_P_USB_SS3_TC3_ADMA_I2C1_SDA SC_P_USB_SS3_TC3 0
+#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC SC_P_USB_SS3_TC3 1
+#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 SC_P_USB_SS3_TC3 4
+#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK SC_P_EMMC0_CLK 0
+#define SC_P_EMMC0_CLK_CONN_NAND_READY_B SC_P_EMMC0_CLK 1
+#define SC_P_EMMC0_CLK_LSIO_GPIO4_IO07 SC_P_EMMC0_CLK 4
+#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD SC_P_EMMC0_CMD 0
+#define SC_P_EMMC0_CMD_CONN_NAND_DQS SC_P_EMMC0_CMD 1
+#define SC_P_EMMC0_CMD_LSIO_GPIO4_IO08 SC_P_EMMC0_CMD 4
+#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 SC_P_EMMC0_DATA0 0
+#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 SC_P_EMMC0_DATA0 1
+#define SC_P_EMMC0_DATA0_LSIO_GPIO4_IO09 SC_P_EMMC0_DATA0 4
+#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 SC_P_EMMC0_DATA1 0
+#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 SC_P_EMMC0_DATA1 1
+#define SC_P_EMMC0_DATA1_LSIO_GPIO4_IO10 SC_P_EMMC0_DATA1 4
+#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 SC_P_EMMC0_DATA2 0
+#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 SC_P_EMMC0_DATA2 1
+#define SC_P_EMMC0_DATA2_LSIO_GPIO4_IO11 SC_P_EMMC0_DATA2 4
+#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 SC_P_EMMC0_DATA3 0
+#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 SC_P_EMMC0_DATA3 1
+#define SC_P_EMMC0_DATA3_LSIO_GPIO4_IO12 SC_P_EMMC0_DATA3 4
+#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 SC_P_EMMC0_DATA4 0
+#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 SC_P_EMMC0_DATA4 1
+#define SC_P_EMMC0_DATA4_CONN_EMMC0_WP SC_P_EMMC0_DATA4 3
+#define SC_P_EMMC0_DATA4_LSIO_GPIO4_IO13 SC_P_EMMC0_DATA4 4
+#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 SC_P_EMMC0_DATA5 0
+#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 SC_P_EMMC0_DATA5 1
+#define SC_P_EMMC0_DATA5_CONN_EMMC0_VSELECT SC_P_EMMC0_DATA5 3
+#define SC_P_EMMC0_DATA5_LSIO_GPIO4_IO14 SC_P_EMMC0_DATA5 4
+#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 SC_P_EMMC0_DATA6 0
+#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 SC_P_EMMC0_DATA6 1
+#define SC_P_EMMC0_DATA6_CONN_MLB_CLK SC_P_EMMC0_DATA6 3
+#define SC_P_EMMC0_DATA6_LSIO_GPIO4_IO15 SC_P_EMMC0_DATA6 4
+#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 SC_P_EMMC0_DATA7 0
+#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 SC_P_EMMC0_DATA7 1
+#define SC_P_EMMC0_DATA7_CONN_MLB_SIG SC_P_EMMC0_DATA7 3
+#define SC_P_EMMC0_DATA7_LSIO_GPIO4_IO16 SC_P_EMMC0_DATA7 4
+#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE SC_P_EMMC0_STROBE 0
+#define SC_P_EMMC0_STROBE_CONN_NAND_CLE SC_P_EMMC0_STROBE 1
+#define SC_P_EMMC0_STROBE_CONN_MLB_DATA SC_P_EMMC0_STROBE 3
+#define SC_P_EMMC0_STROBE_LSIO_GPIO4_IO17 SC_P_EMMC0_STROBE 4
+#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B SC_P_EMMC0_RESET_B 0
+#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B SC_P_EMMC0_RESET_B 1
+#define SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18 SC_P_EMMC0_RESET_B 4
+#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B SC_P_USDHC1_RESET_B 0
+#define SC_P_USDHC1_RESET_B_CONN_NAND_RE_N SC_P_USDHC1_RESET_B 1
+#define SC_P_USDHC1_RESET_B_ADMA_SPI2_SCK SC_P_USDHC1_RESET_B 2
+#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 SC_P_USDHC1_RESET_B 4
+#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT SC_P_USDHC1_VSELECT 0
+#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_P SC_P_USDHC1_VSELECT 1
+#define SC_P_USDHC1_VSELECT_ADMA_SPI2_SDO SC_P_USDHC1_VSELECT 2
+#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_B SC_P_USDHC1_VSELECT 3
+#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO20 SC_P_USDHC1_VSELECT 4
+#define SC_P_USDHC1_WP_CONN_USDHC1_WP SC_P_USDHC1_WP 0
+#define SC_P_USDHC1_WP_CONN_NAND_DQS_N SC_P_USDHC1_WP 1
+#define SC_P_USDHC1_WP_ADMA_SPI2_SDI SC_P_USDHC1_WP 2
+#define SC_P_USDHC1_WP_LSIO_GPIO4_IO21 SC_P_USDHC1_WP 4
+#define SC_P_USDHC1_CD_B_CONN_USDHC1_CD_B SC_P_USDHC1_CD_B 0
+#define SC_P_USDHC1_CD_B_CONN_NAND_DQS_P SC_P_USDHC1_CD_B 1
+#define SC_P_USDHC1_CD_B_ADMA_SPI2_CS0 SC_P_USDHC1_CD_B 2
+#define SC_P_USDHC1_CD_B_CONN_NAND_DQS SC_P_USDHC1_CD_B 3
+#define SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 SC_P_USDHC1_CD_B 4
+#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK SC_P_USDHC1_CLK 0
+#define SC_P_USDHC1_CLK_ADMA_UART3_RX SC_P_USDHC1_CLK 2
+#define SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 SC_P_USDHC1_CLK 4
+#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD SC_P_USDHC1_CMD 0
+#define SC_P_USDHC1_CMD_CONN_NAND_CE0_B SC_P_USDHC1_CMD 1
+#define SC_P_USDHC1_CMD_ADMA_MQS_R SC_P_USDHC1_CMD 2
+#define SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 SC_P_USDHC1_CMD 4
+#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 SC_P_USDHC1_DATA0 0
+#define SC_P_USDHC1_DATA0_CONN_NAND_CE1_B SC_P_USDHC1_DATA0 1
+#define SC_P_USDHC1_DATA0_ADMA_MQS_L SC_P_USDHC1_DATA0 2
+#define SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 SC_P_USDHC1_DATA0 4
+#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 SC_P_USDHC1_DATA1 0
+#define SC_P_USDHC1_DATA1_CONN_NAND_RE_B SC_P_USDHC1_DATA1 1
+#define SC_P_USDHC1_DATA1_ADMA_UART3_TX SC_P_USDHC1_DATA1 2
+#define SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 SC_P_USDHC1_DATA1 4
+#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 SC_P_USDHC1_DATA2 0
+#define SC_P_USDHC1_DATA2_CONN_NAND_WE_B SC_P_USDHC1_DATA2 1
+#define SC_P_USDHC1_DATA2_ADMA_UART3_CTS_B SC_P_USDHC1_DATA2 2
+#define SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 SC_P_USDHC1_DATA2 4
+#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 SC_P_USDHC1_DATA3 0
+#define SC_P_USDHC1_DATA3_CONN_NAND_ALE SC_P_USDHC1_DATA3 1
+#define SC_P_USDHC1_DATA3_ADMA_UART3_RTS_B SC_P_USDHC1_DATA3 2
+#define SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 SC_P_USDHC1_DATA3 4
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC SC_P_ENET0_RGMII_TXC 0
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT SC_P_ENET0_RGMII_TXC 1
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN SC_P_ENET0_RGMII_TXC 2
+#define SC_P_ENET0_RGMII_TXC_CONN_NAND_CE1_B SC_P_ENET0_RGMII_TXC 3
+#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 SC_P_ENET0_RGMII_TXC 4
+#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL SC_P_ENET0_RGMII_TX_CTL 0
+#define SC_P_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B SC_P_ENET0_RGMII_TX_CTL 3
+#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 SC_P_ENET0_RGMII_TX_CTL 4
+#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 SC_P_ENET0_RGMII_TXD0 0
+#define SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT SC_P_ENET0_RGMII_TXD0 3
+#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 SC_P_ENET0_RGMII_TXD0 4
+#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 SC_P_ENET0_RGMII_TXD1 0
+#define SC_P_ENET0_RGMII_TXD1_CONN_USDHC1_WP SC_P_ENET0_RGMII_TXD1 3
+#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 SC_P_ENET0_RGMII_TXD1 4
+#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 SC_P_ENET0_RGMII_TXD2 0
+#define SC_P_ENET0_RGMII_TXD2_CONN_MLB_CLK SC_P_ENET0_RGMII_TXD2 1
+#define SC_P_ENET0_RGMII_TXD2_CONN_NAND_CE0_B SC_P_ENET0_RGMII_TXD2 2
+#define SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B SC_P_ENET0_RGMII_TXD2 3
+#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 SC_P_ENET0_RGMII_TXD2 4
+#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 SC_P_ENET0_RGMII_TXD3 0
+#define SC_P_ENET0_RGMII_TXD3_CONN_MLB_SIG SC_P_ENET0_RGMII_TXD3 1
+#define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B SC_P_ENET0_RGMII_TXD3 2
+#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 SC_P_ENET0_RGMII_TXD3 4
+#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0
+#define SC_P_ENET0_RGMII_RXC_CONN_MLB_DATA SC_P_ENET0_RGMII_RXC 1
+#define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B SC_P_ENET0_RGMII_RXC 2
+#define SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK SC_P_ENET0_RGMII_RXC 3
+#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 SC_P_ENET0_RGMII_RXC 4
+#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL SC_P_ENET0_RGMII_RX_CTL 0
+#define SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD SC_P_ENET0_RGMII_RX_CTL 3
+#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 SC_P_ENET0_RGMII_RX_CTL 4
+#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 SC_P_ENET0_RGMII_RXD0 0
+#define SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 SC_P_ENET0_RGMII_RXD0 3
+#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 SC_P_ENET0_RGMII_RXD0 4
+#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 SC_P_ENET0_RGMII_RXD1 0
+#define SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 SC_P_ENET0_RGMII_RXD1 3
+#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 SC_P_ENET0_RGMII_RXD1 4
+#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 SC_P_ENET0_RGMII_RXD2 0
+#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER SC_P_ENET0_RGMII_RXD2 1
+#define SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 SC_P_ENET0_RGMII_RXD2 3
+#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 SC_P_ENET0_RGMII_RXD2 4
+#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 SC_P_ENET0_RGMII_RXD3 0
+#define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE SC_P_ENET0_RGMII_RXD3 2
+#define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 SC_P_ENET0_RGMII_RXD3 3
+#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 SC_P_ENET0_RGMII_RXD3 4
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET0_REFCLK_125M_25M 2
+#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 SC_P_ENET0_REFCLK_125M_25M 4
+#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO SC_P_ENET0_MDIO 0
+#define SC_P_ENET0_MDIO_ADMA_I2C3_SDA SC_P_ENET0_MDIO 1
+#define SC_P_ENET0_MDIO_CONN_ENET1_MDIO SC_P_ENET0_MDIO 2
+#define SC_P_ENET0_MDIO_LSIO_GPIO5_IO10 SC_P_ENET0_MDIO 4
+#define SC_P_ENET0_MDC_CONN_ENET0_MDC SC_P_ENET0_MDC 0
+#define SC_P_ENET0_MDC_ADMA_I2C3_SCL SC_P_ENET0_MDC 1
+#define SC_P_ENET0_MDC_CONN_ENET1_MDC SC_P_ENET0_MDC 2
+#define SC_P_ENET0_MDC_LSIO_GPIO5_IO11 SC_P_ENET0_MDC 4
+#define SC_P_ESAI0_FSR_ADMA_ESAI0_FSR SC_P_ESAI0_FSR 0
+#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT SC_P_ESAI0_FSR 1
+#define SC_P_ESAI0_FSR_ADMA_LCDIF_D00 SC_P_ESAI0_FSR 2
+#define SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC SC_P_ESAI0_FSR 3
+#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN SC_P_ESAI0_FSR 4
+#define SC_P_ESAI0_FST_ADMA_ESAI0_FST SC_P_ESAI0_FST 0
+#define SC_P_ESAI0_FST_CONN_MLB_CLK SC_P_ESAI0_FST 1
+#define SC_P_ESAI0_FST_ADMA_LCDIF_D01 SC_P_ESAI0_FST 2
+#define SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 SC_P_ESAI0_FST 3
+#define SC_P_ESAI0_FST_LSIO_GPIO0_IO01 SC_P_ESAI0_FST 4
+#define SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR SC_P_ESAI0_SCKR 0
+#define SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 SC_P_ESAI0_SCKR 2
+#define SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL SC_P_ESAI0_SCKR 3
+#define SC_P_ESAI0_SCKR_LSIO_GPIO0_IO02 SC_P_ESAI0_SCKR 4
+#define SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT SC_P_ESAI0_SCKT 0
+#define SC_P_ESAI0_SCKT_CONN_MLB_SIG SC_P_ESAI0_SCKT 1
+#define SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 SC_P_ESAI0_SCKT 2
+#define SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 SC_P_ESAI0_SCKT 3
+#define SC_P_ESAI0_SCKT_LSIO_GPIO0_IO03 SC_P_ESAI0_SCKT 4
+#define SC_P_ESAI0_TX0_ADMA_ESAI0_TX0 SC_P_ESAI0_TX0 0
+#define SC_P_ESAI0_TX0_CONN_MLB_DATA SC_P_ESAI0_TX0 1
+#define SC_P_ESAI0_TX0_ADMA_LCDIF_D04 SC_P_ESAI0_TX0 2
+#define SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC SC_P_ESAI0_TX0 3
+#define SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 SC_P_ESAI0_TX0 4
+#define SC_P_ESAI0_TX1_ADMA_ESAI0_TX1 SC_P_ESAI0_TX1 0
+#define SC_P_ESAI0_TX1_ADMA_LCDIF_D05 SC_P_ESAI0_TX1 2
+#define SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 SC_P_ESAI0_TX1 3
+#define SC_P_ESAI0_TX1_LSIO_GPIO0_IO05 SC_P_ESAI0_TX1 4
+#define SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 SC_P_ESAI0_TX2_RX3 0
+#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER SC_P_ESAI0_TX2_RX3 1
+#define SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 SC_P_ESAI0_TX2_RX3 2
+#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 SC_P_ESAI0_TX2_RX3 3
+#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 SC_P_ESAI0_TX2_RX3 4
+#define SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 SC_P_ESAI0_TX3_RX2 0
+#define SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 SC_P_ESAI0_TX3_RX2 2
+#define SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 SC_P_ESAI0_TX3_RX2 3
+#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 SC_P_ESAI0_TX3_RX2 4
+#define SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 SC_P_ESAI0_TX4_RX1 0
+#define SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 SC_P_ESAI0_TX4_RX1 2
+#define SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 SC_P_ESAI0_TX4_RX1 3
+#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO0_IO08 SC_P_ESAI0_TX4_RX1 4
+#define SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 SC_P_ESAI0_TX5_RX0 0
+#define SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 SC_P_ESAI0_TX5_RX0 2
+#define SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 SC_P_ESAI0_TX5_RX0 3
+#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO0_IO09 SC_P_ESAI0_TX5_RX0 4
+#define SC_P_SPDIF0_RX_ADMA_SPDIF0_RX SC_P_SPDIF0_RX 0
+#define SC_P_SPDIF0_RX_ADMA_MQS_R SC_P_SPDIF0_RX 1
+#define SC_P_SPDIF0_RX_ADMA_LCDIF_D10 SC_P_SPDIF0_RX 2
+#define SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 SC_P_SPDIF0_RX 3
+#define SC_P_SPDIF0_RX_LSIO_GPIO0_IO10 SC_P_SPDIF0_RX 4
+#define SC_P_SPDIF0_TX_ADMA_SPDIF0_TX SC_P_SPDIF0_TX 0
+#define SC_P_SPDIF0_TX_ADMA_MQS_L SC_P_SPDIF0_TX 1
+#define SC_P_SPDIF0_TX_ADMA_LCDIF_D11 SC_P_SPDIF0_TX 2
+#define SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL SC_P_SPDIF0_TX 3
+#define SC_P_SPDIF0_TX_LSIO_GPIO0_IO11 SC_P_SPDIF0_TX 4
+#define SC_P_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK SC_P_SPDIF0_EXT_CLK 0
+#define SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 SC_P_SPDIF0_EXT_CLK 2
+#define SC_P_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M SC_P_SPDIF0_EXT_CLK 3
+#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 SC_P_SPDIF0_EXT_CLK 4
+#define SC_P_SPI3_SCK_ADMA_SPI3_SCK SC_P_SPI3_SCK 0
+#define SC_P_SPI3_SCK_ADMA_LCDIF_D13 SC_P_SPI3_SCK 2
+#define SC_P_SPI3_SCK_LSIO_GPIO0_IO13 SC_P_SPI3_SCK 4
+#define SC_P_SPI3_SDO_ADMA_SPI3_SDO SC_P_SPI3_SDO 0
+#define SC_P_SPI3_SDO_ADMA_LCDIF_D14 SC_P_SPI3_SDO 2
+#define SC_P_SPI3_SDO_LSIO_GPIO0_IO14 SC_P_SPI3_SDO 4
+#define SC_P_SPI3_SDI_ADMA_SPI3_SDI SC_P_SPI3_SDI 0
+#define SC_P_SPI3_SDI_ADMA_LCDIF_D15 SC_P_SPI3_SDI 2
+#define SC_P_SPI3_SDI_LSIO_GPIO0_IO15 SC_P_SPI3_SDI 4
+#define SC_P_SPI3_CS0_ADMA_SPI3_CS0 SC_P_SPI3_CS0 0
+#define SC_P_SPI3_CS0_ADMA_ACM_MCLK_OUT1 SC_P_SPI3_CS0 1
+#define SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC SC_P_SPI3_CS0 2
+#define SC_P_SPI3_CS0_LSIO_GPIO0_IO16 SC_P_SPI3_CS0 4
+#define SC_P_SPI3_CS1_ADMA_SPI3_CS1 SC_P_SPI3_CS1 0
+#define SC_P_SPI3_CS1_ADMA_I2C3_SCL SC_P_SPI3_CS1 1
+#define SC_P_SPI3_CS1_ADMA_LCDIF_RESET SC_P_SPI3_CS1 2
+#define SC_P_SPI3_CS1_ADMA_SPI2_CS0 SC_P_SPI3_CS1 3
+#define SC_P_SPI3_CS1_ADMA_LCDIF_D16 SC_P_SPI3_CS1 4
+#define SC_P_MCLK_IN1_ADMA_ACM_MCLK_IN1 SC_P_MCLK_IN1 0
+#define SC_P_MCLK_IN1_ADMA_I2C3_SDA SC_P_MCLK_IN1 1
+#define SC_P_MCLK_IN1_ADMA_LCDIF_EN SC_P_MCLK_IN1 2
+#define SC_P_MCLK_IN1_ADMA_SPI2_SCK SC_P_MCLK_IN1 3
+#define SC_P_MCLK_IN1_ADMA_LCDIF_D17 SC_P_MCLK_IN1 4
+#define SC_P_MCLK_IN0_ADMA_ACM_MCLK_IN0 SC_P_MCLK_IN0 0
+#define SC_P_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK SC_P_MCLK_IN0 1
+#define SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC SC_P_MCLK_IN0 2
+#define SC_P_MCLK_IN0_ADMA_SPI2_SDI SC_P_MCLK_IN0 3
+#define SC_P_MCLK_IN0_LSIO_GPIO0_IO19 SC_P_MCLK_IN0 4
+#define SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 SC_P_MCLK_OUT0 0
+#define SC_P_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK SC_P_MCLK_OUT0 1
+#define SC_P_MCLK_OUT0_ADMA_LCDIF_CLK SC_P_MCLK_OUT0 2
+#define SC_P_MCLK_OUT0_ADMA_SPI2_SDO SC_P_MCLK_OUT0 3
+#define SC_P_MCLK_OUT0_LSIO_GPIO0_IO20 SC_P_MCLK_OUT0 4
+#define SC_P_UART1_TX_ADMA_UART1_TX SC_P_UART1_TX 0
+#define SC_P_UART1_TX_LSIO_PWM0_OUT SC_P_UART1_TX 1
+#define SC_P_UART1_TX_LSIO_GPT0_CAPTURE SC_P_UART1_TX 2
+#define SC_P_UART1_TX_LSIO_GPIO0_IO21 SC_P_UART1_TX 4
+#define SC_P_UART1_RX_ADMA_UART1_RX SC_P_UART1_RX 0
+#define SC_P_UART1_RX_LSIO_PWM1_OUT SC_P_UART1_RX 1
+#define SC_P_UART1_RX_LSIO_GPT0_COMPARE SC_P_UART1_RX 2
+#define SC_P_UART1_RX_LSIO_GPT1_CLK SC_P_UART1_RX 3
+#define SC_P_UART1_RX_LSIO_GPIO0_IO22 SC_P_UART1_RX 4
+#define SC_P_UART1_RTS_B_ADMA_UART1_RTS_B SC_P_UART1_RTS_B 0
+#define SC_P_UART1_RTS_B_LSIO_PWM2_OUT SC_P_UART1_RTS_B 1
+#define SC_P_UART1_RTS_B_ADMA_LCDIF_D16 SC_P_UART1_RTS_B 2
+#define SC_P_UART1_RTS_B_LSIO_GPT1_CAPTURE SC_P_UART1_RTS_B 3
+#define SC_P_UART1_RTS_B_LSIO_GPT0_CLK SC_P_UART1_RTS_B 4
+#define SC_P_UART1_CTS_B_ADMA_UART1_CTS_B SC_P_UART1_CTS_B 0
+#define SC_P_UART1_CTS_B_LSIO_PWM3_OUT SC_P_UART1_CTS_B 1
+#define SC_P_UART1_CTS_B_ADMA_LCDIF_D17 SC_P_UART1_CTS_B 2
+#define SC_P_UART1_CTS_B_LSIO_GPT1_COMPARE SC_P_UART1_CTS_B 3
+#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO24 SC_P_UART1_CTS_B 4
+#define SC_P_SAI0_TXD_ADMA_SAI0_TXD SC_P_SAI0_TXD 0
+#define SC_P_SAI0_TXD_ADMA_SAI1_RXC SC_P_SAI0_TXD 1
+#define SC_P_SAI0_TXD_ADMA_SPI1_SDO SC_P_SAI0_TXD 2
+#define SC_P_SAI0_TXD_ADMA_LCDIF_D18 SC_P_SAI0_TXD 3
+#define SC_P_SAI0_TXD_LSIO_GPIO0_IO25 SC_P_SAI0_TXD 4
+#define SC_P_SAI0_TXC_ADMA_SAI0_TXC SC_P_SAI0_TXC 0
+#define SC_P_SAI0_TXC_ADMA_SAI1_TXD SC_P_SAI0_TXC 1
+#define SC_P_SAI0_TXC_ADMA_SPI1_SDI SC_P_SAI0_TXC 2
+#define SC_P_SAI0_TXC_ADMA_LCDIF_D19 SC_P_SAI0_TXC 3
+#define SC_P_SAI0_TXC_LSIO_GPIO0_IO26 SC_P_SAI0_TXC 4
+#define SC_P_SAI0_RXD_ADMA_SAI0_RXD SC_P_SAI0_RXD 0
+#define SC_P_SAI0_RXD_ADMA_SAI1_RXFS SC_P_SAI0_RXD 1
+#define SC_P_SAI0_RXD_ADMA_SPI1_CS0 SC_P_SAI0_RXD 2
+#define SC_P_SAI0_RXD_ADMA_LCDIF_D20 SC_P_SAI0_RXD 3
+#define SC_P_SAI0_RXD_LSIO_GPIO0_IO27 SC_P_SAI0_RXD 4
+#define SC_P_SAI0_TXFS_ADMA_SAI0_TXFS SC_P_SAI0_TXFS 0
+#define SC_P_SAI0_TXFS_ADMA_SPI2_CS1 SC_P_SAI0_TXFS 1
+#define SC_P_SAI0_TXFS_ADMA_SPI1_SCK SC_P_SAI0_TXFS 2
+#define SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 SC_P_SAI0_TXFS 4
+#define SC_P_SAI1_RXD_ADMA_SAI1_RXD SC_P_SAI1_RXD 0
+#define SC_P_SAI1_RXD_ADMA_SAI0_RXFS SC_P_SAI1_RXD 1
+#define SC_P_SAI1_RXD_ADMA_SPI1_CS1 SC_P_SAI1_RXD 2
+#define SC_P_SAI1_RXD_ADMA_LCDIF_D21 SC_P_SAI1_RXD 3
+#define SC_P_SAI1_RXD_LSIO_GPIO0_IO29 SC_P_SAI1_RXD 4
+#define SC_P_SAI1_RXC_ADMA_SAI1_RXC SC_P_SAI1_RXC 0
+#define SC_P_SAI1_RXC_ADMA_SAI1_TXC SC_P_SAI1_RXC 1
+#define SC_P_SAI1_RXC_ADMA_LCDIF_D22 SC_P_SAI1_RXC 3
+#define SC_P_SAI1_RXC_LSIO_GPIO0_IO30 SC_P_SAI1_RXC 4
+#define SC_P_SAI1_RXFS_ADMA_SAI1_RXFS SC_P_SAI1_RXFS 0
+#define SC_P_SAI1_RXFS_ADMA_SAI1_TXFS SC_P_SAI1_RXFS 1
+#define SC_P_SAI1_RXFS_ADMA_LCDIF_D23 SC_P_SAI1_RXFS 3
+#define SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 SC_P_SAI1_RXFS 4
+#define SC_P_SPI2_CS0_ADMA_SPI2_CS0 SC_P_SPI2_CS0 0
+#define SC_P_SPI2_CS0_LSIO_GPIO1_IO00 SC_P_SPI2_CS0 4
+#define SC_P_SPI2_SDO_ADMA_SPI2_SDO SC_P_SPI2_SDO 0
+#define SC_P_SPI2_SDO_LSIO_GPIO1_IO01 SC_P_SPI2_SDO 4
+#define SC_P_SPI2_SDI_ADMA_SPI2_SDI SC_P_SPI2_SDI 0
+#define SC_P_SPI2_SDI_LSIO_GPIO1_IO02 SC_P_SPI2_SDI 4
+#define SC_P_SPI2_SCK_ADMA_SPI2_SCK SC_P_SPI2_SCK 0
+#define SC_P_SPI2_SCK_LSIO_GPIO1_IO03 SC_P_SPI2_SCK 4
+#define SC_P_SPI0_SCK_ADMA_SPI0_SCK SC_P_SPI0_SCK 0
+#define SC_P_SPI0_SCK_ADMA_SAI0_TXC SC_P_SPI0_SCK 1
+#define SC_P_SPI0_SCK_M40_I2C0_SCL SC_P_SPI0_SCK 2
+#define SC_P_SPI0_SCK_M40_GPIO0_IO00 SC_P_SPI0_SCK 3
+#define SC_P_SPI0_SCK_LSIO_GPIO1_IO04 SC_P_SPI0_SCK 4
+#define SC_P_SPI0_SDI_ADMA_SPI0_SDI SC_P_SPI0_SDI 0
+#define SC_P_SPI0_SDI_ADMA_SAI0_TXD SC_P_SPI0_SDI 1
+#define SC_P_SPI0_SDI_M40_TPM0_CH0 SC_P_SPI0_SDI 2
+#define SC_P_SPI0_SDI_M40_GPIO0_IO02 SC_P_SPI0_SDI 3
+#define SC_P_SPI0_SDI_LSIO_GPIO1_IO05 SC_P_SPI0_SDI 4
+#define SC_P_SPI0_SDO_ADMA_SPI0_SDO SC_P_SPI0_SDO 0
+#define SC_P_SPI0_SDO_ADMA_SAI0_TXFS SC_P_SPI0_SDO 1
+#define SC_P_SPI0_SDO_M40_I2C0_SDA SC_P_SPI0_SDO 2
+#define SC_P_SPI0_SDO_M40_GPIO0_IO01 SC_P_SPI0_SDO 3
+#define SC_P_SPI0_SDO_LSIO_GPIO1_IO06 SC_P_SPI0_SDO 4
+#define SC_P_SPI0_CS1_ADMA_SPI0_CS1 SC_P_SPI0_CS1 0
+#define SC_P_SPI0_CS1_ADMA_SAI0_RXC SC_P_SPI0_CS1 1
+#define SC_P_SPI0_CS1_ADMA_SAI1_TXD SC_P_SPI0_CS1 2
+#define SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT SC_P_SPI0_CS1 3
+#define SC_P_SPI0_CS1_LSIO_GPIO1_IO07 SC_P_SPI0_CS1 4
+#define SC_P_SPI0_CS0_ADMA_SPI0_CS0 SC_P_SPI0_CS0 0
+#define SC_P_SPI0_CS0_ADMA_SAI0_RXD SC_P_SPI0_CS0 1
+#define SC_P_SPI0_CS0_M40_TPM0_CH1 SC_P_SPI0_CS0 2
+#define SC_P_SPI0_CS0_M40_GPIO0_IO03 SC_P_SPI0_CS0 3
+#define SC_P_SPI0_CS0_LSIO_GPIO1_IO08 SC_P_SPI0_CS0 4
+#define SC_P_ADC_IN1_ADMA_ADC_IN1 SC_P_ADC_IN1 0
+#define SC_P_ADC_IN1_M40_I2C0_SDA SC_P_ADC_IN1 1
+#define SC_P_ADC_IN1_M40_GPIO0_IO01 SC_P_ADC_IN1 2
+#define SC_P_ADC_IN1_LSIO_GPIO1_IO09 SC_P_ADC_IN1 4
+#define SC_P_ADC_IN0_ADMA_ADC_IN0 SC_P_ADC_IN0 0
+#define SC_P_ADC_IN0_M40_I2C0_SCL SC_P_ADC_IN0 1
+#define SC_P_ADC_IN0_M40_GPIO0_IO00 SC_P_ADC_IN0 2
+#define SC_P_ADC_IN0_LSIO_GPIO1_IO10 SC_P_ADC_IN0 4
+#define SC_P_ADC_IN3_ADMA_ADC_IN3 SC_P_ADC_IN3 0
+#define SC_P_ADC_IN3_M40_UART0_TX SC_P_ADC_IN3 1
+#define SC_P_ADC_IN3_M40_GPIO0_IO03 SC_P_ADC_IN3 2
+#define SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0 SC_P_ADC_IN3 3
+#define SC_P_ADC_IN3_LSIO_GPIO1_IO11 SC_P_ADC_IN3 4
+#define SC_P_ADC_IN2_ADMA_ADC_IN2 SC_P_ADC_IN2 0
+#define SC_P_ADC_IN2_M40_UART0_RX SC_P_ADC_IN2 1
+#define SC_P_ADC_IN2_M40_GPIO0_IO02 SC_P_ADC_IN2 2
+#define SC_P_ADC_IN2_ADMA_ACM_MCLK_IN0 SC_P_ADC_IN2 3
+#define SC_P_ADC_IN2_LSIO_GPIO1_IO12 SC_P_ADC_IN2 4
+#define SC_P_ADC_IN5_ADMA_ADC_IN5 SC_P_ADC_IN5 0
+#define SC_P_ADC_IN5_M40_TPM0_CH1 SC_P_ADC_IN5 1
+#define SC_P_ADC_IN5_M40_GPIO0_IO05 SC_P_ADC_IN5 2
+#define SC_P_ADC_IN5_LSIO_GPIO1_IO13 SC_P_ADC_IN5 4
+#define SC_P_ADC_IN4_ADMA_ADC_IN4 SC_P_ADC_IN4 0
+#define SC_P_ADC_IN4_M40_TPM0_CH0 SC_P_ADC_IN4 1
+#define SC_P_ADC_IN4_M40_GPIO0_IO04 SC_P_ADC_IN4 2
+#define SC_P_ADC_IN4_LSIO_GPIO1_IO14 SC_P_ADC_IN4 4
+#define SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX SC_P_FLEXCAN0_RX 0
+#define SC_P_FLEXCAN0_RX_ADMA_SAI2_RXC SC_P_FLEXCAN0_RX 1
+#define SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B SC_P_FLEXCAN0_RX 2
+#define SC_P_FLEXCAN0_RX_ADMA_SAI1_TXC SC_P_FLEXCAN0_RX 3
+#define SC_P_FLEXCAN0_RX_LSIO_GPIO1_IO15 SC_P_FLEXCAN0_RX 4
+#define SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX SC_P_FLEXCAN0_TX 0
+#define SC_P_FLEXCAN0_TX_ADMA_SAI2_RXD SC_P_FLEXCAN0_TX 1
+#define SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B SC_P_FLEXCAN0_TX 2
+#define SC_P_FLEXCAN0_TX_ADMA_SAI1_TXFS SC_P_FLEXCAN0_TX 3
+#define SC_P_FLEXCAN0_TX_LSIO_GPIO1_IO16 SC_P_FLEXCAN0_TX 4
+#define SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX SC_P_FLEXCAN1_RX 0
+#define SC_P_FLEXCAN1_RX_ADMA_SAI2_RXFS SC_P_FLEXCAN1_RX 1
+#define SC_P_FLEXCAN1_RX_ADMA_FTM_CH2 SC_P_FLEXCAN1_RX 2
+#define SC_P_FLEXCAN1_RX_ADMA_SAI1_TXD SC_P_FLEXCAN1_RX 3
+#define SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 SC_P_FLEXCAN1_RX 4
+#define SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX SC_P_FLEXCAN1_TX 0
+#define SC_P_FLEXCAN1_TX_ADMA_SAI3_RXC SC_P_FLEXCAN1_TX 1
+#define SC_P_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 SC_P_FLEXCAN1_TX 2
+#define SC_P_FLEXCAN1_TX_ADMA_SAI1_RXD SC_P_FLEXCAN1_TX 3
+#define SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 SC_P_FLEXCAN1_TX 4
+#define SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX SC_P_FLEXCAN2_RX 0
+#define SC_P_FLEXCAN2_RX_ADMA_SAI3_RXD SC_P_FLEXCAN2_RX 1
+#define SC_P_FLEXCAN2_RX_ADMA_UART3_RX SC_P_FLEXCAN2_RX 2
+#define SC_P_FLEXCAN2_RX_ADMA_SAI1_RXFS SC_P_FLEXCAN2_RX 3
+#define SC_P_FLEXCAN2_RX_LSIO_GPIO1_IO19 SC_P_FLEXCAN2_RX 4
+#define SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX SC_P_FLEXCAN2_TX 0
+#define SC_P_FLEXCAN2_TX_ADMA_SAI3_RXFS SC_P_FLEXCAN2_TX 1
+#define SC_P_FLEXCAN2_TX_ADMA_UART3_TX SC_P_FLEXCAN2_TX 2
+#define SC_P_FLEXCAN2_TX_ADMA_SAI1_RXC SC_P_FLEXCAN2_TX 3
+#define SC_P_FLEXCAN2_TX_LSIO_GPIO1_IO20 SC_P_FLEXCAN2_TX 4
+#define SC_P_UART0_RX_ADMA_UART0_RX SC_P_UART0_RX 0
+#define SC_P_UART0_RX_ADMA_MQS_R SC_P_UART0_RX 1
+#define SC_P_UART0_RX_ADMA_FLEXCAN0_RX SC_P_UART0_RX 2
+#define SC_P_UART0_RX_LSIO_GPIO1_IO21 SC_P_UART0_RX 4
+#define SC_P_UART0_TX_ADMA_UART0_TX SC_P_UART0_TX 0
+#define SC_P_UART0_TX_ADMA_MQS_L SC_P_UART0_TX 1
+#define SC_P_UART0_TX_ADMA_FLEXCAN0_TX SC_P_UART0_TX 2
+#define SC_P_UART0_TX_LSIO_GPIO1_IO22 SC_P_UART0_TX 4
+#define SC_P_UART2_TX_ADMA_UART2_TX SC_P_UART2_TX 0
+#define SC_P_UART2_TX_ADMA_FTM_CH1 SC_P_UART2_TX 1
+#define SC_P_UART2_TX_ADMA_FLEXCAN1_TX SC_P_UART2_TX 2
+#define SC_P_UART2_TX_LSIO_GPIO1_IO23 SC_P_UART2_TX 4
+#define SC_P_UART2_RX_ADMA_UART2_RX SC_P_UART2_RX 0
+#define SC_P_UART2_RX_ADMA_FTM_CH0 SC_P_UART2_RX 1
+#define SC_P_UART2_RX_ADMA_FLEXCAN1_RX SC_P_UART2_RX 2
+#define SC_P_UART2_RX_LSIO_GPIO1_IO24 SC_P_UART2_RX 4
+#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL SC_P_MIPI_DSI0_I2C0_SCL 0
+#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02 SC_P_MIPI_DSI0_I2C0_SCL 1
+#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 SC_P_MIPI_DSI0_I2C0_SCL 4
+#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA SC_P_MIPI_DSI0_I2C0_SDA 0
+#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03 SC_P_MIPI_DSI0_I2C0_SDA 1
+#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 SC_P_MIPI_DSI0_I2C0_SDA 4
+#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 SC_P_MIPI_DSI0_GPIO0_00 0
+#define SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL SC_P_MIPI_DSI0_GPIO0_00 1
+#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT SC_P_MIPI_DSI0_GPIO0_00 2
+#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 SC_P_MIPI_DSI0_GPIO0_00 4
+#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 SC_P_MIPI_DSI0_GPIO0_01 0
+#define SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA SC_P_MIPI_DSI0_GPIO0_01 1
+#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 SC_P_MIPI_DSI0_GPIO0_01 4
+#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL SC_P_MIPI_DSI1_I2C0_SCL 0
+#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02 SC_P_MIPI_DSI1_I2C0_SCL 1
+#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29 SC_P_MIPI_DSI1_I2C0_SCL 4
+#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA SC_P_MIPI_DSI1_I2C0_SDA 0
+#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03 SC_P_MIPI_DSI1_I2C0_SDA 1
+#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 SC_P_MIPI_DSI1_I2C0_SDA 4
+#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 SC_P_MIPI_DSI1_GPIO0_00 0
+#define SC_P_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL SC_P_MIPI_DSI1_GPIO0_00 1
+#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT SC_P_MIPI_DSI1_GPIO0_00 2
+#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 SC_P_MIPI_DSI1_GPIO0_00 4
+#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 SC_P_MIPI_DSI1_GPIO0_01 0
+#define SC_P_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA SC_P_MIPI_DSI1_GPIO0_01 1
+#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 SC_P_MIPI_DSI1_GPIO0_01 4
+#define SC_P_JTAG_TRST_B_SCU_JTAG_TRST_B SC_P_JTAG_TRST_B 0
+#define SC_P_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT SC_P_JTAG_TRST_B 1
+#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL SC_P_PMIC_I2C_SCL 0
+#define SC_P_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON SC_P_PMIC_I2C_SCL 1
+#define SC_P_PMIC_I2C_SCL_LSIO_GPIO2_IO01 SC_P_PMIC_I2C_SCL 4
+#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA SC_P_PMIC_I2C_SDA 0
+#define SC_P_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON SC_P_PMIC_I2C_SDA 1
+#define SC_P_PMIC_I2C_SDA_LSIO_GPIO2_IO02 SC_P_PMIC_I2C_SDA 4
+#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B SC_P_PMIC_INT_B 0
+#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 SC_P_SCU_GPIO0_00 0
+#define SC_P_SCU_GPIO0_00_SCU_UART0_RX SC_P_SCU_GPIO0_00 1
+#define SC_P_SCU_GPIO0_00_M40_UART0_RX SC_P_SCU_GPIO0_00 2
+#define SC_P_SCU_GPIO0_00_ADMA_UART3_RX SC_P_SCU_GPIO0_00 3
+#define SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03 SC_P_SCU_GPIO0_00 4
+#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 SC_P_SCU_GPIO0_01 0
+#define SC_P_SCU_GPIO0_01_SCU_UART0_TX SC_P_SCU_GPIO0_01 1
+#define SC_P_SCU_GPIO0_01_M40_UART0_TX SC_P_SCU_GPIO0_01 2
+#define SC_P_SCU_GPIO0_01_ADMA_UART3_TX SC_P_SCU_GPIO0_01 3
+#define SC_P_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT SC_P_SCU_GPIO0_01 4
+#define SC_P_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY SC_P_SCU_PMIC_STANDBY 0
+#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 SC_P_SCU_BOOT_MODE0 0
+#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 SC_P_SCU_BOOT_MODE1 0
+#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 SC_P_SCU_BOOT_MODE2 0
+#define SC_P_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA SC_P_SCU_BOOT_MODE2 1
+#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 SC_P_SCU_BOOT_MODE3 0
+#define SC_P_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL SC_P_SCU_BOOT_MODE3 1
+#define SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K SC_P_SCU_BOOT_MODE3 3
+#define SC_P_CSI_D00_CI_PI_D02 SC_P_CSI_D00 0
+#define SC_P_CSI_D00_ADMA_SAI0_RXC SC_P_CSI_D00 2
+#define SC_P_CSI_D01_CI_PI_D03 SC_P_CSI_D01 0
+#define SC_P_CSI_D01_ADMA_SAI0_RXD SC_P_CSI_D01 2
+#define SC_P_CSI_D02_CI_PI_D04 SC_P_CSI_D02 0
+#define SC_P_CSI_D02_ADMA_SAI0_RXFS SC_P_CSI_D02 2
+#define SC_P_CSI_D03_CI_PI_D05 SC_P_CSI_D03 0
+#define SC_P_CSI_D03_ADMA_SAI2_RXC SC_P_CSI_D03 2
+#define SC_P_CSI_D04_CI_PI_D06 SC_P_CSI_D04 0
+#define SC_P_CSI_D04_ADMA_SAI2_RXD SC_P_CSI_D04 2
+#define SC_P_CSI_D05_CI_PI_D07 SC_P_CSI_D05 0
+#define SC_P_CSI_D05_ADMA_SAI2_RXFS SC_P_CSI_D05 2
+#define SC_P_CSI_D06_CI_PI_D08 SC_P_CSI_D06 0
+#define SC_P_CSI_D06_ADMA_SAI3_RXC SC_P_CSI_D06 2
+#define SC_P_CSI_D07_CI_PI_D09 SC_P_CSI_D07 0
+#define SC_P_CSI_D07_ADMA_SAI3_RXD SC_P_CSI_D07 2
+#define SC_P_CSI_HSYNC_CI_PI_HSYNC SC_P_CSI_HSYNC 0
+#define SC_P_CSI_HSYNC_CI_PI_D00 SC_P_CSI_HSYNC 1
+#define SC_P_CSI_HSYNC_ADMA_SAI3_RXFS SC_P_CSI_HSYNC 2
+#define SC_P_CSI_VSYNC_CI_PI_VSYNC SC_P_CSI_VSYNC 0
+#define SC_P_CSI_VSYNC_CI_PI_D01 SC_P_CSI_VSYNC 1
+#define SC_P_CSI_PCLK_CI_PI_PCLK SC_P_CSI_PCLK 0
+#define SC_P_CSI_PCLK_MIPI_CSI0_I2C0_SCL SC_P_CSI_PCLK 1
+#define SC_P_CSI_PCLK_ADMA_SPI1_SCK SC_P_CSI_PCLK 3
+#define SC_P_CSI_PCLK_LSIO_GPIO3_IO00 SC_P_CSI_PCLK 4
+#define SC_P_CSI_MCLK_CI_PI_MCLK SC_P_CSI_MCLK 0
+#define SC_P_CSI_MCLK_MIPI_CSI0_I2C0_SDA SC_P_CSI_MCLK 1
+#define SC_P_CSI_MCLK_ADMA_SPI1_SDO SC_P_CSI_MCLK 3
+#define SC_P_CSI_MCLK_LSIO_GPIO3_IO01 SC_P_CSI_MCLK 4
+#define SC_P_CSI_EN_CI_PI_EN SC_P_CSI_EN 0
+#define SC_P_CSI_EN_CI_PI_I2C_SCL SC_P_CSI_EN 1
+#define SC_P_CSI_EN_ADMA_I2C3_SCL SC_P_CSI_EN 2
+#define SC_P_CSI_EN_ADMA_SPI1_SDI SC_P_CSI_EN 3
+#define SC_P_CSI_EN_LSIO_GPIO3_IO02 SC_P_CSI_EN 4
+#define SC_P_CSI_RESET_CI_PI_RESET SC_P_CSI_RESET 0
+#define SC_P_CSI_RESET_CI_PI_I2C_SDA SC_P_CSI_RESET 1
+#define SC_P_CSI_RESET_ADMA_I2C3_SDA SC_P_CSI_RESET 2
+#define SC_P_CSI_RESET_ADMA_SPI1_CS0 SC_P_CSI_RESET 3
+#define SC_P_CSI_RESET_LSIO_GPIO3_IO03 SC_P_CSI_RESET 4
+#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT SC_P_MIPI_CSI0_MCLK_OUT 0
+#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 SC_P_MIPI_CSI0_MCLK_OUT 4
+#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL SC_P_MIPI_CSI0_I2C0_SCL 0
+#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02 SC_P_MIPI_CSI0_I2C0_SCL 1
+#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 SC_P_MIPI_CSI0_I2C0_SCL 4
+#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA SC_P_MIPI_CSI0_I2C0_SDA 0
+#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03 SC_P_MIPI_CSI0_I2C0_SDA 1
+#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 SC_P_MIPI_CSI0_I2C0_SDA 4
+#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 SC_P_MIPI_CSI0_GPIO0_01 0
+#define SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 1
+#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 SC_P_MIPI_CSI0_GPIO0_01 4
+#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 SC_P_MIPI_CSI0_GPIO0_00 0
+#define SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 1
+#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 SC_P_MIPI_CSI0_GPIO0_00 4
+#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 SC_P_QSPI0A_DATA0 0
+#define SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 SC_P_QSPI0A_DATA0 4
+#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 SC_P_QSPI0A_DATA1 0
+#define SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 SC_P_QSPI0A_DATA1 4
+#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 SC_P_QSPI0A_DATA2 0
+#define SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 SC_P_QSPI0A_DATA2 4
+#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 SC_P_QSPI0A_DATA3 0
+#define SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 SC_P_QSPI0A_DATA3 4
+#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS SC_P_QSPI0A_DQS 0
+#define SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 SC_P_QSPI0A_DQS 4
+#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B SC_P_QSPI0A_SS0_B 0
+#define SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 SC_P_QSPI0A_SS0_B 4
+#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B SC_P_QSPI0A_SS1_B 0
+#define SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 SC_P_QSPI0A_SS1_B 4
+#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK SC_P_QSPI0A_SCLK 0
+#define SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 SC_P_QSPI0A_SCLK 4
+#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK SC_P_QSPI0B_SCLK 0
+#define SC_P_QSPI0B_SCLK_LSIO_QSPI1A_SCLK SC_P_QSPI0B_SCLK 1
+#define SC_P_QSPI0B_SCLK_LSIO_KPP0_COL0 SC_P_QSPI0B_SCLK 2
+#define SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 SC_P_QSPI0B_SCLK 4
+#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 SC_P_QSPI0B_DATA0 0
+#define SC_P_QSPI0B_DATA0_LSIO_QSPI1A_DATA0 SC_P_QSPI0B_DATA0 1
+#define SC_P_QSPI0B_DATA0_LSIO_KPP0_COL1 SC_P_QSPI0B_DATA0 2
+#define SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 SC_P_QSPI0B_DATA0 4
+#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 SC_P_QSPI0B_DATA1 0
+#define SC_P_QSPI0B_DATA1_LSIO_QSPI1A_DATA1 SC_P_QSPI0B_DATA1 1
+#define SC_P_QSPI0B_DATA1_LSIO_KPP0_COL2 SC_P_QSPI0B_DATA1 2
+#define SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 SC_P_QSPI0B_DATA1 4
+#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 SC_P_QSPI0B_DATA2 0
+#define SC_P_QSPI0B_DATA2_LSIO_QSPI1A_DATA2 SC_P_QSPI0B_DATA2 1
+#define SC_P_QSPI0B_DATA2_LSIO_KPP0_COL3 SC_P_QSPI0B_DATA2 2
+#define SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 SC_P_QSPI0B_DATA2 4
+#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 SC_P_QSPI0B_DATA3 0
+#define SC_P_QSPI0B_DATA3_LSIO_QSPI1A_DATA3 SC_P_QSPI0B_DATA3 1
+#define SC_P_QSPI0B_DATA3_LSIO_KPP0_ROW0 SC_P_QSPI0B_DATA3 2
+#define SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 SC_P_QSPI0B_DATA3 4
+#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS SC_P_QSPI0B_DQS 0
+#define SC_P_QSPI0B_DQS_LSIO_QSPI1A_DQS SC_P_QSPI0B_DQS 1
+#define SC_P_QSPI0B_DQS_LSIO_KPP0_ROW1 SC_P_QSPI0B_DQS 2
+#define SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 SC_P_QSPI0B_DQS 4
+#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B SC_P_QSPI0B_SS0_B 0
+#define SC_P_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B SC_P_QSPI0B_SS0_B 1
+#define SC_P_QSPI0B_SS0_B_LSIO_KPP0_ROW2 SC_P_QSPI0B_SS0_B 2
+#define SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 SC_P_QSPI0B_SS0_B 4
+#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B SC_P_QSPI0B_SS1_B 0
+#define SC_P_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B SC_P_QSPI0B_SS1_B 1
+#define SC_P_QSPI0B_SS1_B_LSIO_KPP0_ROW3 SC_P_QSPI0B_SS1_B 2
+#define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 SC_P_QSPI0B_SS1_B 4
+
+#endif /* _SC_PADS_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 5/6] dt-bindings: pinctrl: add imx8qxp pinctrl binding doc
@ 2018-04-27 19:01 ` Dong Aisheng
0 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2018-04-27 19:01 UTC (permalink / raw)
To: linux-arm-kernel
Add imx8qxp pinctrl binding doc.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree at vger.kernel.org
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
Note: there's a checkpatch error as follows:
ERROR: Macros with complex values should be enclosed in parentheses
+#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0
However, this is the intended format. Seems checkpatch did not recognize
it well. Not sure if we could accept it.
---
.../bindings/pinctrl/fsl,imx8qxp-pinctrl.txt | 39 ++
include/dt-bindings/pinctrl/pads-imx8qxp.h | 751 +++++++++++++++++++++
2 files changed, 790 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt
create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt
new file mode 100644
index 0000000..62c0f55
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt
@@ -0,0 +1,39 @@
+* NXP i.MX8QXP IOMUX Controller
+
+MX8QXP contains a system controller that is responsible for controlling
+the pad setting of the IPs that are present. Communication between the
+host processor running an OS and the system controller happens through
+a SCU protocol.
+
+Please also refer to fsl,imx-pinctrl.txt in this directory for i.MX common
+pinctrl binding.
+
+=== Pin Controller Node ===
+
+Required properties:
+- compatible: "fsl,imx8qxp-iomuxc"
+
+=== Pin Configuration Node ===
+- fsl,pins: Each entry consists of 3 integers which represents the mux and
+ config setting for one pin. The first 2 integers <pin_id mux_mode>
+ are specified using a PIN_FUNC_ID macro, which can be found
+ in <dt-bindings/pinctrl/pads-imx8qxp.h>. The last integer CONFIG
+ is the pad setting value like pull-up on this pin.
+ Please refer to i.MX8QXP Reference Manual for detailed
+ CONFIG settings.
+
+Examples:
+#include <dt-bindings/pinctrl/pads-imx8qxp.h>
+
+/* Pin Controller Node */
+iomuxc: iomuxc {
+ compatible = "fsl,imx8qxp-iomuxc";
+
+ /* Pin Configuration Node */
+ pinctrl_lpuart0: lpuart0grp {
+ fsl,pins = <
+ SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
+ SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
+ >;
+ };
+};
diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h
new file mode 100644
index 0000000..8f477c3
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h
@@ -0,0 +1,751 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ */
+
+#ifndef _SC_PADS_H
+#define _SC_PADS_H
+
+/* pin id */
+#define SC_P_PCIE_CTRL0_PERST_B 0
+#define SC_P_PCIE_CTRL0_CLKREQ_B 1
+#define SC_P_PCIE_CTRL0_WAKE_B 2
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3
+#define SC_P_USB_SS3_TC0 4
+#define SC_P_USB_SS3_TC1 5
+#define SC_P_USB_SS3_TC2 6
+#define SC_P_USB_SS3_TC3 7
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8
+#define SC_P_EMMC0_CLK 9
+#define SC_P_EMMC0_CMD 10
+#define SC_P_EMMC0_DATA0 11
+#define SC_P_EMMC0_DATA1 12
+#define SC_P_EMMC0_DATA2 13
+#define SC_P_EMMC0_DATA3 14
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15
+#define SC_P_EMMC0_DATA4 16
+#define SC_P_EMMC0_DATA5 17
+#define SC_P_EMMC0_DATA6 18
+#define SC_P_EMMC0_DATA7 19
+#define SC_P_EMMC0_STROBE 20
+#define SC_P_EMMC0_RESET_B 21
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22
+#define SC_P_USDHC1_RESET_B 23
+#define SC_P_USDHC1_VSELECT 24
+#define SC_P_CTL_NAND_RE_P_N 25
+#define SC_P_USDHC1_WP 26
+#define SC_P_USDHC1_CD_B 27
+#define SC_P_CTL_NAND_DQS_P_N 28
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29
+#define SC_P_USDHC1_CLK 30
+#define SC_P_USDHC1_CMD 31
+#define SC_P_USDHC1_DATA0 32
+#define SC_P_USDHC1_DATA1 33
+#define SC_P_USDHC1_DATA2 34
+#define SC_P_USDHC1_DATA3 35
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36
+#define SC_P_ENET0_RGMII_TXC 37
+#define SC_P_ENET0_RGMII_TX_CTL 38
+#define SC_P_ENET0_RGMII_TXD0 39
+#define SC_P_ENET0_RGMII_TXD1 40
+#define SC_P_ENET0_RGMII_TXD2 41
+#define SC_P_ENET0_RGMII_TXD3 42
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43
+#define SC_P_ENET0_RGMII_RXC 44
+#define SC_P_ENET0_RGMII_RX_CTL 45
+#define SC_P_ENET0_RGMII_RXD0 46
+#define SC_P_ENET0_RGMII_RXD1 47
+#define SC_P_ENET0_RGMII_RXD2 48
+#define SC_P_ENET0_RGMII_RXD3 49
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50
+#define SC_P_ENET0_REFCLK_125M_25M 51
+#define SC_P_ENET0_MDIO 52
+#define SC_P_ENET0_MDC 53
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54
+#define SC_P_ESAI0_FSR 55
+#define SC_P_ESAI0_FST 56
+#define SC_P_ESAI0_SCKR 57
+#define SC_P_ESAI0_SCKT 58
+#define SC_P_ESAI0_TX0 59
+#define SC_P_ESAI0_TX1 60
+#define SC_P_ESAI0_TX2_RX3 61
+#define SC_P_ESAI0_TX3_RX2 62
+#define SC_P_ESAI0_TX4_RX1 63
+#define SC_P_ESAI0_TX5_RX0 64
+#define SC_P_SPDIF0_RX 65
+#define SC_P_SPDIF0_TX 66
+#define SC_P_SPDIF0_EXT_CLK 67
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68
+#define SC_P_SPI3_SCK 69
+#define SC_P_SPI3_SDO 70
+#define SC_P_SPI3_SDI 71
+#define SC_P_SPI3_CS0 72
+#define SC_P_SPI3_CS1 73
+#define SC_P_MCLK_IN1 74
+#define SC_P_MCLK_IN0 75
+#define SC_P_MCLK_OUT0 76
+#define SC_P_UART1_TX 77
+#define SC_P_UART1_RX 78
+#define SC_P_UART1_RTS_B 79
+#define SC_P_UART1_CTS_B 80
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81
+#define SC_P_SAI0_TXD 82
+#define SC_P_SAI0_TXC 83
+#define SC_P_SAI0_RXD 84
+#define SC_P_SAI0_TXFS 85
+#define SC_P_SAI1_RXD 86
+#define SC_P_SAI1_RXC 87
+#define SC_P_SAI1_RXFS 88
+#define SC_P_SPI2_CS0 89
+#define SC_P_SPI2_SDO 90
+#define SC_P_SPI2_SDI 91
+#define SC_P_SPI2_SCK 92
+#define SC_P_SPI0_SCK 93
+#define SC_P_SPI0_SDI 94
+#define SC_P_SPI0_SDO 95
+#define SC_P_SPI0_CS1 96
+#define SC_P_SPI0_CS0 97
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98
+#define SC_P_ADC_IN1 99
+#define SC_P_ADC_IN0 100
+#define SC_P_ADC_IN3 101
+#define SC_P_ADC_IN2 102
+#define SC_P_ADC_IN5 103
+#define SC_P_ADC_IN4 104
+#define SC_P_FLEXCAN0_RX 105
+#define SC_P_FLEXCAN0_TX 106
+#define SC_P_FLEXCAN1_RX 107
+#define SC_P_FLEXCAN1_TX 108
+#define SC_P_FLEXCAN2_RX 109
+#define SC_P_FLEXCAN2_TX 110
+#define SC_P_UART0_RX 111
+#define SC_P_UART0_TX 112
+#define SC_P_UART2_TX 113
+#define SC_P_UART2_RX 114
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115
+#define SC_P_MIPI_DSI0_I2C0_SCL 116
+#define SC_P_MIPI_DSI0_I2C0_SDA 117
+#define SC_P_MIPI_DSI0_GPIO0_00 118
+#define SC_P_MIPI_DSI0_GPIO0_01 119
+#define SC_P_MIPI_DSI1_I2C0_SCL 120
+#define SC_P_MIPI_DSI1_I2C0_SDA 121
+#define SC_P_MIPI_DSI1_GPIO0_00 122
+#define SC_P_MIPI_DSI1_GPIO0_01 123
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124
+#define SC_P_JTAG_TRST_B 125
+#define SC_P_PMIC_I2C_SCL 126
+#define SC_P_PMIC_I2C_SDA 127
+#define SC_P_PMIC_INT_B 128
+#define SC_P_SCU_GPIO0_00 129
+#define SC_P_SCU_GPIO0_01 130
+#define SC_P_SCU_PMIC_STANDBY 131
+#define SC_P_SCU_BOOT_MODE0 132
+#define SC_P_SCU_BOOT_MODE1 133
+#define SC_P_SCU_BOOT_MODE2 134
+#define SC_P_SCU_BOOT_MODE3 135
+#define SC_P_CSI_D00 136
+#define SC_P_CSI_D01 137
+#define SC_P_CSI_D02 138
+#define SC_P_CSI_D03 139
+#define SC_P_CSI_D04 140
+#define SC_P_CSI_D05 141
+#define SC_P_CSI_D06 142
+#define SC_P_CSI_D07 143
+#define SC_P_CSI_HSYNC 144
+#define SC_P_CSI_VSYNC 145
+#define SC_P_CSI_PCLK 146
+#define SC_P_CSI_MCLK 147
+#define SC_P_CSI_EN 148
+#define SC_P_CSI_RESET 149
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150
+#define SC_P_MIPI_CSI0_MCLK_OUT 151
+#define SC_P_MIPI_CSI0_I2C0_SCL 152
+#define SC_P_MIPI_CSI0_I2C0_SDA 153
+#define SC_P_MIPI_CSI0_GPIO0_01 154
+#define SC_P_MIPI_CSI0_GPIO0_00 155
+#define SC_P_QSPI0A_DATA0 156
+#define SC_P_QSPI0A_DATA1 157
+#define SC_P_QSPI0A_DATA2 158
+#define SC_P_QSPI0A_DATA3 159
+#define SC_P_QSPI0A_DQS 160
+#define SC_P_QSPI0A_SS0_B 161
+#define SC_P_QSPI0A_SS1_B 162
+#define SC_P_QSPI0A_SCLK 163
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164
+#define SC_P_QSPI0B_SCLK 165
+#define SC_P_QSPI0B_DATA0 166
+#define SC_P_QSPI0B_DATA1 167
+#define SC_P_QSPI0B_DATA2 168
+#define SC_P_QSPI0B_DATA3 169
+#define SC_P_QSPI0B_DQS 170
+#define SC_P_QSPI0B_SS0_B 171
+#define SC_P_QSPI0B_SS1_B 172
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173
+
+/*
+ * format: <pin_id mux_mode>
+ */
+#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0
+#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 SC_P_PCIE_CTRL0_PERST_B 4
+#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B SC_P_PCIE_CTRL0_CLKREQ_B 0
+#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 SC_P_PCIE_CTRL0_CLKREQ_B 4
+#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B SC_P_PCIE_CTRL0_WAKE_B 0
+#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 SC_P_PCIE_CTRL0_WAKE_B 4
+#define SC_P_USB_SS3_TC0_ADMA_I2C1_SCL SC_P_USB_SS3_TC0 0
+#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR SC_P_USB_SS3_TC0 1
+#define SC_P_USB_SS3_TC0_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC0 2
+#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 SC_P_USB_SS3_TC0 4
+#define SC_P_USB_SS3_TC1_ADMA_I2C1_SCL SC_P_USB_SS3_TC1 0
+#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC1 1
+#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 SC_P_USB_SS3_TC1 4
+#define SC_P_USB_SS3_TC2_ADMA_I2C1_SDA SC_P_USB_SS3_TC2 0
+#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC SC_P_USB_SS3_TC2 1
+#define SC_P_USB_SS3_TC2_CONN_USB_OTG2_OC SC_P_USB_SS3_TC2 2
+#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 SC_P_USB_SS3_TC2 4
+#define SC_P_USB_SS3_TC3_ADMA_I2C1_SDA SC_P_USB_SS3_TC3 0
+#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC SC_P_USB_SS3_TC3 1
+#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 SC_P_USB_SS3_TC3 4
+#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK SC_P_EMMC0_CLK 0
+#define SC_P_EMMC0_CLK_CONN_NAND_READY_B SC_P_EMMC0_CLK 1
+#define SC_P_EMMC0_CLK_LSIO_GPIO4_IO07 SC_P_EMMC0_CLK 4
+#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD SC_P_EMMC0_CMD 0
+#define SC_P_EMMC0_CMD_CONN_NAND_DQS SC_P_EMMC0_CMD 1
+#define SC_P_EMMC0_CMD_LSIO_GPIO4_IO08 SC_P_EMMC0_CMD 4
+#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 SC_P_EMMC0_DATA0 0
+#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 SC_P_EMMC0_DATA0 1
+#define SC_P_EMMC0_DATA0_LSIO_GPIO4_IO09 SC_P_EMMC0_DATA0 4
+#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 SC_P_EMMC0_DATA1 0
+#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 SC_P_EMMC0_DATA1 1
+#define SC_P_EMMC0_DATA1_LSIO_GPIO4_IO10 SC_P_EMMC0_DATA1 4
+#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 SC_P_EMMC0_DATA2 0
+#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 SC_P_EMMC0_DATA2 1
+#define SC_P_EMMC0_DATA2_LSIO_GPIO4_IO11 SC_P_EMMC0_DATA2 4
+#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 SC_P_EMMC0_DATA3 0
+#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 SC_P_EMMC0_DATA3 1
+#define SC_P_EMMC0_DATA3_LSIO_GPIO4_IO12 SC_P_EMMC0_DATA3 4
+#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 SC_P_EMMC0_DATA4 0
+#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 SC_P_EMMC0_DATA4 1
+#define SC_P_EMMC0_DATA4_CONN_EMMC0_WP SC_P_EMMC0_DATA4 3
+#define SC_P_EMMC0_DATA4_LSIO_GPIO4_IO13 SC_P_EMMC0_DATA4 4
+#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 SC_P_EMMC0_DATA5 0
+#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 SC_P_EMMC0_DATA5 1
+#define SC_P_EMMC0_DATA5_CONN_EMMC0_VSELECT SC_P_EMMC0_DATA5 3
+#define SC_P_EMMC0_DATA5_LSIO_GPIO4_IO14 SC_P_EMMC0_DATA5 4
+#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 SC_P_EMMC0_DATA6 0
+#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 SC_P_EMMC0_DATA6 1
+#define SC_P_EMMC0_DATA6_CONN_MLB_CLK SC_P_EMMC0_DATA6 3
+#define SC_P_EMMC0_DATA6_LSIO_GPIO4_IO15 SC_P_EMMC0_DATA6 4
+#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 SC_P_EMMC0_DATA7 0
+#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 SC_P_EMMC0_DATA7 1
+#define SC_P_EMMC0_DATA7_CONN_MLB_SIG SC_P_EMMC0_DATA7 3
+#define SC_P_EMMC0_DATA7_LSIO_GPIO4_IO16 SC_P_EMMC0_DATA7 4
+#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE SC_P_EMMC0_STROBE 0
+#define SC_P_EMMC0_STROBE_CONN_NAND_CLE SC_P_EMMC0_STROBE 1
+#define SC_P_EMMC0_STROBE_CONN_MLB_DATA SC_P_EMMC0_STROBE 3
+#define SC_P_EMMC0_STROBE_LSIO_GPIO4_IO17 SC_P_EMMC0_STROBE 4
+#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B SC_P_EMMC0_RESET_B 0
+#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B SC_P_EMMC0_RESET_B 1
+#define SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18 SC_P_EMMC0_RESET_B 4
+#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B SC_P_USDHC1_RESET_B 0
+#define SC_P_USDHC1_RESET_B_CONN_NAND_RE_N SC_P_USDHC1_RESET_B 1
+#define SC_P_USDHC1_RESET_B_ADMA_SPI2_SCK SC_P_USDHC1_RESET_B 2
+#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 SC_P_USDHC1_RESET_B 4
+#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT SC_P_USDHC1_VSELECT 0
+#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_P SC_P_USDHC1_VSELECT 1
+#define SC_P_USDHC1_VSELECT_ADMA_SPI2_SDO SC_P_USDHC1_VSELECT 2
+#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_B SC_P_USDHC1_VSELECT 3
+#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO20 SC_P_USDHC1_VSELECT 4
+#define SC_P_USDHC1_WP_CONN_USDHC1_WP SC_P_USDHC1_WP 0
+#define SC_P_USDHC1_WP_CONN_NAND_DQS_N SC_P_USDHC1_WP 1
+#define SC_P_USDHC1_WP_ADMA_SPI2_SDI SC_P_USDHC1_WP 2
+#define SC_P_USDHC1_WP_LSIO_GPIO4_IO21 SC_P_USDHC1_WP 4
+#define SC_P_USDHC1_CD_B_CONN_USDHC1_CD_B SC_P_USDHC1_CD_B 0
+#define SC_P_USDHC1_CD_B_CONN_NAND_DQS_P SC_P_USDHC1_CD_B 1
+#define SC_P_USDHC1_CD_B_ADMA_SPI2_CS0 SC_P_USDHC1_CD_B 2
+#define SC_P_USDHC1_CD_B_CONN_NAND_DQS SC_P_USDHC1_CD_B 3
+#define SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 SC_P_USDHC1_CD_B 4
+#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK SC_P_USDHC1_CLK 0
+#define SC_P_USDHC1_CLK_ADMA_UART3_RX SC_P_USDHC1_CLK 2
+#define SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 SC_P_USDHC1_CLK 4
+#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD SC_P_USDHC1_CMD 0
+#define SC_P_USDHC1_CMD_CONN_NAND_CE0_B SC_P_USDHC1_CMD 1
+#define SC_P_USDHC1_CMD_ADMA_MQS_R SC_P_USDHC1_CMD 2
+#define SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 SC_P_USDHC1_CMD 4
+#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 SC_P_USDHC1_DATA0 0
+#define SC_P_USDHC1_DATA0_CONN_NAND_CE1_B SC_P_USDHC1_DATA0 1
+#define SC_P_USDHC1_DATA0_ADMA_MQS_L SC_P_USDHC1_DATA0 2
+#define SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 SC_P_USDHC1_DATA0 4
+#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 SC_P_USDHC1_DATA1 0
+#define SC_P_USDHC1_DATA1_CONN_NAND_RE_B SC_P_USDHC1_DATA1 1
+#define SC_P_USDHC1_DATA1_ADMA_UART3_TX SC_P_USDHC1_DATA1 2
+#define SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 SC_P_USDHC1_DATA1 4
+#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 SC_P_USDHC1_DATA2 0
+#define SC_P_USDHC1_DATA2_CONN_NAND_WE_B SC_P_USDHC1_DATA2 1
+#define SC_P_USDHC1_DATA2_ADMA_UART3_CTS_B SC_P_USDHC1_DATA2 2
+#define SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 SC_P_USDHC1_DATA2 4
+#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 SC_P_USDHC1_DATA3 0
+#define SC_P_USDHC1_DATA3_CONN_NAND_ALE SC_P_USDHC1_DATA3 1
+#define SC_P_USDHC1_DATA3_ADMA_UART3_RTS_B SC_P_USDHC1_DATA3 2
+#define SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 SC_P_USDHC1_DATA3 4
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC SC_P_ENET0_RGMII_TXC 0
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT SC_P_ENET0_RGMII_TXC 1
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN SC_P_ENET0_RGMII_TXC 2
+#define SC_P_ENET0_RGMII_TXC_CONN_NAND_CE1_B SC_P_ENET0_RGMII_TXC 3
+#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 SC_P_ENET0_RGMII_TXC 4
+#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL SC_P_ENET0_RGMII_TX_CTL 0
+#define SC_P_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B SC_P_ENET0_RGMII_TX_CTL 3
+#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 SC_P_ENET0_RGMII_TX_CTL 4
+#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 SC_P_ENET0_RGMII_TXD0 0
+#define SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT SC_P_ENET0_RGMII_TXD0 3
+#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 SC_P_ENET0_RGMII_TXD0 4
+#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 SC_P_ENET0_RGMII_TXD1 0
+#define SC_P_ENET0_RGMII_TXD1_CONN_USDHC1_WP SC_P_ENET0_RGMII_TXD1 3
+#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 SC_P_ENET0_RGMII_TXD1 4
+#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 SC_P_ENET0_RGMII_TXD2 0
+#define SC_P_ENET0_RGMII_TXD2_CONN_MLB_CLK SC_P_ENET0_RGMII_TXD2 1
+#define SC_P_ENET0_RGMII_TXD2_CONN_NAND_CE0_B SC_P_ENET0_RGMII_TXD2 2
+#define SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B SC_P_ENET0_RGMII_TXD2 3
+#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 SC_P_ENET0_RGMII_TXD2 4
+#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 SC_P_ENET0_RGMII_TXD3 0
+#define SC_P_ENET0_RGMII_TXD3_CONN_MLB_SIG SC_P_ENET0_RGMII_TXD3 1
+#define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B SC_P_ENET0_RGMII_TXD3 2
+#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 SC_P_ENET0_RGMII_TXD3 4
+#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0
+#define SC_P_ENET0_RGMII_RXC_CONN_MLB_DATA SC_P_ENET0_RGMII_RXC 1
+#define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B SC_P_ENET0_RGMII_RXC 2
+#define SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK SC_P_ENET0_RGMII_RXC 3
+#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 SC_P_ENET0_RGMII_RXC 4
+#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL SC_P_ENET0_RGMII_RX_CTL 0
+#define SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD SC_P_ENET0_RGMII_RX_CTL 3
+#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 SC_P_ENET0_RGMII_RX_CTL 4
+#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 SC_P_ENET0_RGMII_RXD0 0
+#define SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 SC_P_ENET0_RGMII_RXD0 3
+#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 SC_P_ENET0_RGMII_RXD0 4
+#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 SC_P_ENET0_RGMII_RXD1 0
+#define SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 SC_P_ENET0_RGMII_RXD1 3
+#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 SC_P_ENET0_RGMII_RXD1 4
+#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 SC_P_ENET0_RGMII_RXD2 0
+#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER SC_P_ENET0_RGMII_RXD2 1
+#define SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 SC_P_ENET0_RGMII_RXD2 3
+#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 SC_P_ENET0_RGMII_RXD2 4
+#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 SC_P_ENET0_RGMII_RXD3 0
+#define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE SC_P_ENET0_RGMII_RXD3 2
+#define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 SC_P_ENET0_RGMII_RXD3 3
+#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 SC_P_ENET0_RGMII_RXD3 4
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET0_REFCLK_125M_25M 2
+#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 SC_P_ENET0_REFCLK_125M_25M 4
+#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO SC_P_ENET0_MDIO 0
+#define SC_P_ENET0_MDIO_ADMA_I2C3_SDA SC_P_ENET0_MDIO 1
+#define SC_P_ENET0_MDIO_CONN_ENET1_MDIO SC_P_ENET0_MDIO 2
+#define SC_P_ENET0_MDIO_LSIO_GPIO5_IO10 SC_P_ENET0_MDIO 4
+#define SC_P_ENET0_MDC_CONN_ENET0_MDC SC_P_ENET0_MDC 0
+#define SC_P_ENET0_MDC_ADMA_I2C3_SCL SC_P_ENET0_MDC 1
+#define SC_P_ENET0_MDC_CONN_ENET1_MDC SC_P_ENET0_MDC 2
+#define SC_P_ENET0_MDC_LSIO_GPIO5_IO11 SC_P_ENET0_MDC 4
+#define SC_P_ESAI0_FSR_ADMA_ESAI0_FSR SC_P_ESAI0_FSR 0
+#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT SC_P_ESAI0_FSR 1
+#define SC_P_ESAI0_FSR_ADMA_LCDIF_D00 SC_P_ESAI0_FSR 2
+#define SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC SC_P_ESAI0_FSR 3
+#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN SC_P_ESAI0_FSR 4
+#define SC_P_ESAI0_FST_ADMA_ESAI0_FST SC_P_ESAI0_FST 0
+#define SC_P_ESAI0_FST_CONN_MLB_CLK SC_P_ESAI0_FST 1
+#define SC_P_ESAI0_FST_ADMA_LCDIF_D01 SC_P_ESAI0_FST 2
+#define SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 SC_P_ESAI0_FST 3
+#define SC_P_ESAI0_FST_LSIO_GPIO0_IO01 SC_P_ESAI0_FST 4
+#define SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR SC_P_ESAI0_SCKR 0
+#define SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 SC_P_ESAI0_SCKR 2
+#define SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL SC_P_ESAI0_SCKR 3
+#define SC_P_ESAI0_SCKR_LSIO_GPIO0_IO02 SC_P_ESAI0_SCKR 4
+#define SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT SC_P_ESAI0_SCKT 0
+#define SC_P_ESAI0_SCKT_CONN_MLB_SIG SC_P_ESAI0_SCKT 1
+#define SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 SC_P_ESAI0_SCKT 2
+#define SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 SC_P_ESAI0_SCKT 3
+#define SC_P_ESAI0_SCKT_LSIO_GPIO0_IO03 SC_P_ESAI0_SCKT 4
+#define SC_P_ESAI0_TX0_ADMA_ESAI0_TX0 SC_P_ESAI0_TX0 0
+#define SC_P_ESAI0_TX0_CONN_MLB_DATA SC_P_ESAI0_TX0 1
+#define SC_P_ESAI0_TX0_ADMA_LCDIF_D04 SC_P_ESAI0_TX0 2
+#define SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC SC_P_ESAI0_TX0 3
+#define SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 SC_P_ESAI0_TX0 4
+#define SC_P_ESAI0_TX1_ADMA_ESAI0_TX1 SC_P_ESAI0_TX1 0
+#define SC_P_ESAI0_TX1_ADMA_LCDIF_D05 SC_P_ESAI0_TX1 2
+#define SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 SC_P_ESAI0_TX1 3
+#define SC_P_ESAI0_TX1_LSIO_GPIO0_IO05 SC_P_ESAI0_TX1 4
+#define SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 SC_P_ESAI0_TX2_RX3 0
+#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER SC_P_ESAI0_TX2_RX3 1
+#define SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 SC_P_ESAI0_TX2_RX3 2
+#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 SC_P_ESAI0_TX2_RX3 3
+#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 SC_P_ESAI0_TX2_RX3 4
+#define SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 SC_P_ESAI0_TX3_RX2 0
+#define SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 SC_P_ESAI0_TX3_RX2 2
+#define SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 SC_P_ESAI0_TX3_RX2 3
+#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 SC_P_ESAI0_TX3_RX2 4
+#define SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 SC_P_ESAI0_TX4_RX1 0
+#define SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 SC_P_ESAI0_TX4_RX1 2
+#define SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 SC_P_ESAI0_TX4_RX1 3
+#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO0_IO08 SC_P_ESAI0_TX4_RX1 4
+#define SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 SC_P_ESAI0_TX5_RX0 0
+#define SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 SC_P_ESAI0_TX5_RX0 2
+#define SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 SC_P_ESAI0_TX5_RX0 3
+#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO0_IO09 SC_P_ESAI0_TX5_RX0 4
+#define SC_P_SPDIF0_RX_ADMA_SPDIF0_RX SC_P_SPDIF0_RX 0
+#define SC_P_SPDIF0_RX_ADMA_MQS_R SC_P_SPDIF0_RX 1
+#define SC_P_SPDIF0_RX_ADMA_LCDIF_D10 SC_P_SPDIF0_RX 2
+#define SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 SC_P_SPDIF0_RX 3
+#define SC_P_SPDIF0_RX_LSIO_GPIO0_IO10 SC_P_SPDIF0_RX 4
+#define SC_P_SPDIF0_TX_ADMA_SPDIF0_TX SC_P_SPDIF0_TX 0
+#define SC_P_SPDIF0_TX_ADMA_MQS_L SC_P_SPDIF0_TX 1
+#define SC_P_SPDIF0_TX_ADMA_LCDIF_D11 SC_P_SPDIF0_TX 2
+#define SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL SC_P_SPDIF0_TX 3
+#define SC_P_SPDIF0_TX_LSIO_GPIO0_IO11 SC_P_SPDIF0_TX 4
+#define SC_P_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK SC_P_SPDIF0_EXT_CLK 0
+#define SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 SC_P_SPDIF0_EXT_CLK 2
+#define SC_P_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M SC_P_SPDIF0_EXT_CLK 3
+#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 SC_P_SPDIF0_EXT_CLK 4
+#define SC_P_SPI3_SCK_ADMA_SPI3_SCK SC_P_SPI3_SCK 0
+#define SC_P_SPI3_SCK_ADMA_LCDIF_D13 SC_P_SPI3_SCK 2
+#define SC_P_SPI3_SCK_LSIO_GPIO0_IO13 SC_P_SPI3_SCK 4
+#define SC_P_SPI3_SDO_ADMA_SPI3_SDO SC_P_SPI3_SDO 0
+#define SC_P_SPI3_SDO_ADMA_LCDIF_D14 SC_P_SPI3_SDO 2
+#define SC_P_SPI3_SDO_LSIO_GPIO0_IO14 SC_P_SPI3_SDO 4
+#define SC_P_SPI3_SDI_ADMA_SPI3_SDI SC_P_SPI3_SDI 0
+#define SC_P_SPI3_SDI_ADMA_LCDIF_D15 SC_P_SPI3_SDI 2
+#define SC_P_SPI3_SDI_LSIO_GPIO0_IO15 SC_P_SPI3_SDI 4
+#define SC_P_SPI3_CS0_ADMA_SPI3_CS0 SC_P_SPI3_CS0 0
+#define SC_P_SPI3_CS0_ADMA_ACM_MCLK_OUT1 SC_P_SPI3_CS0 1
+#define SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC SC_P_SPI3_CS0 2
+#define SC_P_SPI3_CS0_LSIO_GPIO0_IO16 SC_P_SPI3_CS0 4
+#define SC_P_SPI3_CS1_ADMA_SPI3_CS1 SC_P_SPI3_CS1 0
+#define SC_P_SPI3_CS1_ADMA_I2C3_SCL SC_P_SPI3_CS1 1
+#define SC_P_SPI3_CS1_ADMA_LCDIF_RESET SC_P_SPI3_CS1 2
+#define SC_P_SPI3_CS1_ADMA_SPI2_CS0 SC_P_SPI3_CS1 3
+#define SC_P_SPI3_CS1_ADMA_LCDIF_D16 SC_P_SPI3_CS1 4
+#define SC_P_MCLK_IN1_ADMA_ACM_MCLK_IN1 SC_P_MCLK_IN1 0
+#define SC_P_MCLK_IN1_ADMA_I2C3_SDA SC_P_MCLK_IN1 1
+#define SC_P_MCLK_IN1_ADMA_LCDIF_EN SC_P_MCLK_IN1 2
+#define SC_P_MCLK_IN1_ADMA_SPI2_SCK SC_P_MCLK_IN1 3
+#define SC_P_MCLK_IN1_ADMA_LCDIF_D17 SC_P_MCLK_IN1 4
+#define SC_P_MCLK_IN0_ADMA_ACM_MCLK_IN0 SC_P_MCLK_IN0 0
+#define SC_P_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK SC_P_MCLK_IN0 1
+#define SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC SC_P_MCLK_IN0 2
+#define SC_P_MCLK_IN0_ADMA_SPI2_SDI SC_P_MCLK_IN0 3
+#define SC_P_MCLK_IN0_LSIO_GPIO0_IO19 SC_P_MCLK_IN0 4
+#define SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 SC_P_MCLK_OUT0 0
+#define SC_P_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK SC_P_MCLK_OUT0 1
+#define SC_P_MCLK_OUT0_ADMA_LCDIF_CLK SC_P_MCLK_OUT0 2
+#define SC_P_MCLK_OUT0_ADMA_SPI2_SDO SC_P_MCLK_OUT0 3
+#define SC_P_MCLK_OUT0_LSIO_GPIO0_IO20 SC_P_MCLK_OUT0 4
+#define SC_P_UART1_TX_ADMA_UART1_TX SC_P_UART1_TX 0
+#define SC_P_UART1_TX_LSIO_PWM0_OUT SC_P_UART1_TX 1
+#define SC_P_UART1_TX_LSIO_GPT0_CAPTURE SC_P_UART1_TX 2
+#define SC_P_UART1_TX_LSIO_GPIO0_IO21 SC_P_UART1_TX 4
+#define SC_P_UART1_RX_ADMA_UART1_RX SC_P_UART1_RX 0
+#define SC_P_UART1_RX_LSIO_PWM1_OUT SC_P_UART1_RX 1
+#define SC_P_UART1_RX_LSIO_GPT0_COMPARE SC_P_UART1_RX 2
+#define SC_P_UART1_RX_LSIO_GPT1_CLK SC_P_UART1_RX 3
+#define SC_P_UART1_RX_LSIO_GPIO0_IO22 SC_P_UART1_RX 4
+#define SC_P_UART1_RTS_B_ADMA_UART1_RTS_B SC_P_UART1_RTS_B 0
+#define SC_P_UART1_RTS_B_LSIO_PWM2_OUT SC_P_UART1_RTS_B 1
+#define SC_P_UART1_RTS_B_ADMA_LCDIF_D16 SC_P_UART1_RTS_B 2
+#define SC_P_UART1_RTS_B_LSIO_GPT1_CAPTURE SC_P_UART1_RTS_B 3
+#define SC_P_UART1_RTS_B_LSIO_GPT0_CLK SC_P_UART1_RTS_B 4
+#define SC_P_UART1_CTS_B_ADMA_UART1_CTS_B SC_P_UART1_CTS_B 0
+#define SC_P_UART1_CTS_B_LSIO_PWM3_OUT SC_P_UART1_CTS_B 1
+#define SC_P_UART1_CTS_B_ADMA_LCDIF_D17 SC_P_UART1_CTS_B 2
+#define SC_P_UART1_CTS_B_LSIO_GPT1_COMPARE SC_P_UART1_CTS_B 3
+#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO24 SC_P_UART1_CTS_B 4
+#define SC_P_SAI0_TXD_ADMA_SAI0_TXD SC_P_SAI0_TXD 0
+#define SC_P_SAI0_TXD_ADMA_SAI1_RXC SC_P_SAI0_TXD 1
+#define SC_P_SAI0_TXD_ADMA_SPI1_SDO SC_P_SAI0_TXD 2
+#define SC_P_SAI0_TXD_ADMA_LCDIF_D18 SC_P_SAI0_TXD 3
+#define SC_P_SAI0_TXD_LSIO_GPIO0_IO25 SC_P_SAI0_TXD 4
+#define SC_P_SAI0_TXC_ADMA_SAI0_TXC SC_P_SAI0_TXC 0
+#define SC_P_SAI0_TXC_ADMA_SAI1_TXD SC_P_SAI0_TXC 1
+#define SC_P_SAI0_TXC_ADMA_SPI1_SDI SC_P_SAI0_TXC 2
+#define SC_P_SAI0_TXC_ADMA_LCDIF_D19 SC_P_SAI0_TXC 3
+#define SC_P_SAI0_TXC_LSIO_GPIO0_IO26 SC_P_SAI0_TXC 4
+#define SC_P_SAI0_RXD_ADMA_SAI0_RXD SC_P_SAI0_RXD 0
+#define SC_P_SAI0_RXD_ADMA_SAI1_RXFS SC_P_SAI0_RXD 1
+#define SC_P_SAI0_RXD_ADMA_SPI1_CS0 SC_P_SAI0_RXD 2
+#define SC_P_SAI0_RXD_ADMA_LCDIF_D20 SC_P_SAI0_RXD 3
+#define SC_P_SAI0_RXD_LSIO_GPIO0_IO27 SC_P_SAI0_RXD 4
+#define SC_P_SAI0_TXFS_ADMA_SAI0_TXFS SC_P_SAI0_TXFS 0
+#define SC_P_SAI0_TXFS_ADMA_SPI2_CS1 SC_P_SAI0_TXFS 1
+#define SC_P_SAI0_TXFS_ADMA_SPI1_SCK SC_P_SAI0_TXFS 2
+#define SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 SC_P_SAI0_TXFS 4
+#define SC_P_SAI1_RXD_ADMA_SAI1_RXD SC_P_SAI1_RXD 0
+#define SC_P_SAI1_RXD_ADMA_SAI0_RXFS SC_P_SAI1_RXD 1
+#define SC_P_SAI1_RXD_ADMA_SPI1_CS1 SC_P_SAI1_RXD 2
+#define SC_P_SAI1_RXD_ADMA_LCDIF_D21 SC_P_SAI1_RXD 3
+#define SC_P_SAI1_RXD_LSIO_GPIO0_IO29 SC_P_SAI1_RXD 4
+#define SC_P_SAI1_RXC_ADMA_SAI1_RXC SC_P_SAI1_RXC 0
+#define SC_P_SAI1_RXC_ADMA_SAI1_TXC SC_P_SAI1_RXC 1
+#define SC_P_SAI1_RXC_ADMA_LCDIF_D22 SC_P_SAI1_RXC 3
+#define SC_P_SAI1_RXC_LSIO_GPIO0_IO30 SC_P_SAI1_RXC 4
+#define SC_P_SAI1_RXFS_ADMA_SAI1_RXFS SC_P_SAI1_RXFS 0
+#define SC_P_SAI1_RXFS_ADMA_SAI1_TXFS SC_P_SAI1_RXFS 1
+#define SC_P_SAI1_RXFS_ADMA_LCDIF_D23 SC_P_SAI1_RXFS 3
+#define SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 SC_P_SAI1_RXFS 4
+#define SC_P_SPI2_CS0_ADMA_SPI2_CS0 SC_P_SPI2_CS0 0
+#define SC_P_SPI2_CS0_LSIO_GPIO1_IO00 SC_P_SPI2_CS0 4
+#define SC_P_SPI2_SDO_ADMA_SPI2_SDO SC_P_SPI2_SDO 0
+#define SC_P_SPI2_SDO_LSIO_GPIO1_IO01 SC_P_SPI2_SDO 4
+#define SC_P_SPI2_SDI_ADMA_SPI2_SDI SC_P_SPI2_SDI 0
+#define SC_P_SPI2_SDI_LSIO_GPIO1_IO02 SC_P_SPI2_SDI 4
+#define SC_P_SPI2_SCK_ADMA_SPI2_SCK SC_P_SPI2_SCK 0
+#define SC_P_SPI2_SCK_LSIO_GPIO1_IO03 SC_P_SPI2_SCK 4
+#define SC_P_SPI0_SCK_ADMA_SPI0_SCK SC_P_SPI0_SCK 0
+#define SC_P_SPI0_SCK_ADMA_SAI0_TXC SC_P_SPI0_SCK 1
+#define SC_P_SPI0_SCK_M40_I2C0_SCL SC_P_SPI0_SCK 2
+#define SC_P_SPI0_SCK_M40_GPIO0_IO00 SC_P_SPI0_SCK 3
+#define SC_P_SPI0_SCK_LSIO_GPIO1_IO04 SC_P_SPI0_SCK 4
+#define SC_P_SPI0_SDI_ADMA_SPI0_SDI SC_P_SPI0_SDI 0
+#define SC_P_SPI0_SDI_ADMA_SAI0_TXD SC_P_SPI0_SDI 1
+#define SC_P_SPI0_SDI_M40_TPM0_CH0 SC_P_SPI0_SDI 2
+#define SC_P_SPI0_SDI_M40_GPIO0_IO02 SC_P_SPI0_SDI 3
+#define SC_P_SPI0_SDI_LSIO_GPIO1_IO05 SC_P_SPI0_SDI 4
+#define SC_P_SPI0_SDO_ADMA_SPI0_SDO SC_P_SPI0_SDO 0
+#define SC_P_SPI0_SDO_ADMA_SAI0_TXFS SC_P_SPI0_SDO 1
+#define SC_P_SPI0_SDO_M40_I2C0_SDA SC_P_SPI0_SDO 2
+#define SC_P_SPI0_SDO_M40_GPIO0_IO01 SC_P_SPI0_SDO 3
+#define SC_P_SPI0_SDO_LSIO_GPIO1_IO06 SC_P_SPI0_SDO 4
+#define SC_P_SPI0_CS1_ADMA_SPI0_CS1 SC_P_SPI0_CS1 0
+#define SC_P_SPI0_CS1_ADMA_SAI0_RXC SC_P_SPI0_CS1 1
+#define SC_P_SPI0_CS1_ADMA_SAI1_TXD SC_P_SPI0_CS1 2
+#define SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT SC_P_SPI0_CS1 3
+#define SC_P_SPI0_CS1_LSIO_GPIO1_IO07 SC_P_SPI0_CS1 4
+#define SC_P_SPI0_CS0_ADMA_SPI0_CS0 SC_P_SPI0_CS0 0
+#define SC_P_SPI0_CS0_ADMA_SAI0_RXD SC_P_SPI0_CS0 1
+#define SC_P_SPI0_CS0_M40_TPM0_CH1 SC_P_SPI0_CS0 2
+#define SC_P_SPI0_CS0_M40_GPIO0_IO03 SC_P_SPI0_CS0 3
+#define SC_P_SPI0_CS0_LSIO_GPIO1_IO08 SC_P_SPI0_CS0 4
+#define SC_P_ADC_IN1_ADMA_ADC_IN1 SC_P_ADC_IN1 0
+#define SC_P_ADC_IN1_M40_I2C0_SDA SC_P_ADC_IN1 1
+#define SC_P_ADC_IN1_M40_GPIO0_IO01 SC_P_ADC_IN1 2
+#define SC_P_ADC_IN1_LSIO_GPIO1_IO09 SC_P_ADC_IN1 4
+#define SC_P_ADC_IN0_ADMA_ADC_IN0 SC_P_ADC_IN0 0
+#define SC_P_ADC_IN0_M40_I2C0_SCL SC_P_ADC_IN0 1
+#define SC_P_ADC_IN0_M40_GPIO0_IO00 SC_P_ADC_IN0 2
+#define SC_P_ADC_IN0_LSIO_GPIO1_IO10 SC_P_ADC_IN0 4
+#define SC_P_ADC_IN3_ADMA_ADC_IN3 SC_P_ADC_IN3 0
+#define SC_P_ADC_IN3_M40_UART0_TX SC_P_ADC_IN3 1
+#define SC_P_ADC_IN3_M40_GPIO0_IO03 SC_P_ADC_IN3 2
+#define SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0 SC_P_ADC_IN3 3
+#define SC_P_ADC_IN3_LSIO_GPIO1_IO11 SC_P_ADC_IN3 4
+#define SC_P_ADC_IN2_ADMA_ADC_IN2 SC_P_ADC_IN2 0
+#define SC_P_ADC_IN2_M40_UART0_RX SC_P_ADC_IN2 1
+#define SC_P_ADC_IN2_M40_GPIO0_IO02 SC_P_ADC_IN2 2
+#define SC_P_ADC_IN2_ADMA_ACM_MCLK_IN0 SC_P_ADC_IN2 3
+#define SC_P_ADC_IN2_LSIO_GPIO1_IO12 SC_P_ADC_IN2 4
+#define SC_P_ADC_IN5_ADMA_ADC_IN5 SC_P_ADC_IN5 0
+#define SC_P_ADC_IN5_M40_TPM0_CH1 SC_P_ADC_IN5 1
+#define SC_P_ADC_IN5_M40_GPIO0_IO05 SC_P_ADC_IN5 2
+#define SC_P_ADC_IN5_LSIO_GPIO1_IO13 SC_P_ADC_IN5 4
+#define SC_P_ADC_IN4_ADMA_ADC_IN4 SC_P_ADC_IN4 0
+#define SC_P_ADC_IN4_M40_TPM0_CH0 SC_P_ADC_IN4 1
+#define SC_P_ADC_IN4_M40_GPIO0_IO04 SC_P_ADC_IN4 2
+#define SC_P_ADC_IN4_LSIO_GPIO1_IO14 SC_P_ADC_IN4 4
+#define SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX SC_P_FLEXCAN0_RX 0
+#define SC_P_FLEXCAN0_RX_ADMA_SAI2_RXC SC_P_FLEXCAN0_RX 1
+#define SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B SC_P_FLEXCAN0_RX 2
+#define SC_P_FLEXCAN0_RX_ADMA_SAI1_TXC SC_P_FLEXCAN0_RX 3
+#define SC_P_FLEXCAN0_RX_LSIO_GPIO1_IO15 SC_P_FLEXCAN0_RX 4
+#define SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX SC_P_FLEXCAN0_TX 0
+#define SC_P_FLEXCAN0_TX_ADMA_SAI2_RXD SC_P_FLEXCAN0_TX 1
+#define SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B SC_P_FLEXCAN0_TX 2
+#define SC_P_FLEXCAN0_TX_ADMA_SAI1_TXFS SC_P_FLEXCAN0_TX 3
+#define SC_P_FLEXCAN0_TX_LSIO_GPIO1_IO16 SC_P_FLEXCAN0_TX 4
+#define SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX SC_P_FLEXCAN1_RX 0
+#define SC_P_FLEXCAN1_RX_ADMA_SAI2_RXFS SC_P_FLEXCAN1_RX 1
+#define SC_P_FLEXCAN1_RX_ADMA_FTM_CH2 SC_P_FLEXCAN1_RX 2
+#define SC_P_FLEXCAN1_RX_ADMA_SAI1_TXD SC_P_FLEXCAN1_RX 3
+#define SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 SC_P_FLEXCAN1_RX 4
+#define SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX SC_P_FLEXCAN1_TX 0
+#define SC_P_FLEXCAN1_TX_ADMA_SAI3_RXC SC_P_FLEXCAN1_TX 1
+#define SC_P_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 SC_P_FLEXCAN1_TX 2
+#define SC_P_FLEXCAN1_TX_ADMA_SAI1_RXD SC_P_FLEXCAN1_TX 3
+#define SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 SC_P_FLEXCAN1_TX 4
+#define SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX SC_P_FLEXCAN2_RX 0
+#define SC_P_FLEXCAN2_RX_ADMA_SAI3_RXD SC_P_FLEXCAN2_RX 1
+#define SC_P_FLEXCAN2_RX_ADMA_UART3_RX SC_P_FLEXCAN2_RX 2
+#define SC_P_FLEXCAN2_RX_ADMA_SAI1_RXFS SC_P_FLEXCAN2_RX 3
+#define SC_P_FLEXCAN2_RX_LSIO_GPIO1_IO19 SC_P_FLEXCAN2_RX 4
+#define SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX SC_P_FLEXCAN2_TX 0
+#define SC_P_FLEXCAN2_TX_ADMA_SAI3_RXFS SC_P_FLEXCAN2_TX 1
+#define SC_P_FLEXCAN2_TX_ADMA_UART3_TX SC_P_FLEXCAN2_TX 2
+#define SC_P_FLEXCAN2_TX_ADMA_SAI1_RXC SC_P_FLEXCAN2_TX 3
+#define SC_P_FLEXCAN2_TX_LSIO_GPIO1_IO20 SC_P_FLEXCAN2_TX 4
+#define SC_P_UART0_RX_ADMA_UART0_RX SC_P_UART0_RX 0
+#define SC_P_UART0_RX_ADMA_MQS_R SC_P_UART0_RX 1
+#define SC_P_UART0_RX_ADMA_FLEXCAN0_RX SC_P_UART0_RX 2
+#define SC_P_UART0_RX_LSIO_GPIO1_IO21 SC_P_UART0_RX 4
+#define SC_P_UART0_TX_ADMA_UART0_TX SC_P_UART0_TX 0
+#define SC_P_UART0_TX_ADMA_MQS_L SC_P_UART0_TX 1
+#define SC_P_UART0_TX_ADMA_FLEXCAN0_TX SC_P_UART0_TX 2
+#define SC_P_UART0_TX_LSIO_GPIO1_IO22 SC_P_UART0_TX 4
+#define SC_P_UART2_TX_ADMA_UART2_TX SC_P_UART2_TX 0
+#define SC_P_UART2_TX_ADMA_FTM_CH1 SC_P_UART2_TX 1
+#define SC_P_UART2_TX_ADMA_FLEXCAN1_TX SC_P_UART2_TX 2
+#define SC_P_UART2_TX_LSIO_GPIO1_IO23 SC_P_UART2_TX 4
+#define SC_P_UART2_RX_ADMA_UART2_RX SC_P_UART2_RX 0
+#define SC_P_UART2_RX_ADMA_FTM_CH0 SC_P_UART2_RX 1
+#define SC_P_UART2_RX_ADMA_FLEXCAN1_RX SC_P_UART2_RX 2
+#define SC_P_UART2_RX_LSIO_GPIO1_IO24 SC_P_UART2_RX 4
+#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL SC_P_MIPI_DSI0_I2C0_SCL 0
+#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02 SC_P_MIPI_DSI0_I2C0_SCL 1
+#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 SC_P_MIPI_DSI0_I2C0_SCL 4
+#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA SC_P_MIPI_DSI0_I2C0_SDA 0
+#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03 SC_P_MIPI_DSI0_I2C0_SDA 1
+#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 SC_P_MIPI_DSI0_I2C0_SDA 4
+#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 SC_P_MIPI_DSI0_GPIO0_00 0
+#define SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL SC_P_MIPI_DSI0_GPIO0_00 1
+#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT SC_P_MIPI_DSI0_GPIO0_00 2
+#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 SC_P_MIPI_DSI0_GPIO0_00 4
+#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 SC_P_MIPI_DSI0_GPIO0_01 0
+#define SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA SC_P_MIPI_DSI0_GPIO0_01 1
+#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 SC_P_MIPI_DSI0_GPIO0_01 4
+#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL SC_P_MIPI_DSI1_I2C0_SCL 0
+#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02 SC_P_MIPI_DSI1_I2C0_SCL 1
+#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29 SC_P_MIPI_DSI1_I2C0_SCL 4
+#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA SC_P_MIPI_DSI1_I2C0_SDA 0
+#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03 SC_P_MIPI_DSI1_I2C0_SDA 1
+#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 SC_P_MIPI_DSI1_I2C0_SDA 4
+#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 SC_P_MIPI_DSI1_GPIO0_00 0
+#define SC_P_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL SC_P_MIPI_DSI1_GPIO0_00 1
+#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT SC_P_MIPI_DSI1_GPIO0_00 2
+#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 SC_P_MIPI_DSI1_GPIO0_00 4
+#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 SC_P_MIPI_DSI1_GPIO0_01 0
+#define SC_P_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA SC_P_MIPI_DSI1_GPIO0_01 1
+#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 SC_P_MIPI_DSI1_GPIO0_01 4
+#define SC_P_JTAG_TRST_B_SCU_JTAG_TRST_B SC_P_JTAG_TRST_B 0
+#define SC_P_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT SC_P_JTAG_TRST_B 1
+#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL SC_P_PMIC_I2C_SCL 0
+#define SC_P_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON SC_P_PMIC_I2C_SCL 1
+#define SC_P_PMIC_I2C_SCL_LSIO_GPIO2_IO01 SC_P_PMIC_I2C_SCL 4
+#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA SC_P_PMIC_I2C_SDA 0
+#define SC_P_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON SC_P_PMIC_I2C_SDA 1
+#define SC_P_PMIC_I2C_SDA_LSIO_GPIO2_IO02 SC_P_PMIC_I2C_SDA 4
+#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B SC_P_PMIC_INT_B 0
+#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 SC_P_SCU_GPIO0_00 0
+#define SC_P_SCU_GPIO0_00_SCU_UART0_RX SC_P_SCU_GPIO0_00 1
+#define SC_P_SCU_GPIO0_00_M40_UART0_RX SC_P_SCU_GPIO0_00 2
+#define SC_P_SCU_GPIO0_00_ADMA_UART3_RX SC_P_SCU_GPIO0_00 3
+#define SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03 SC_P_SCU_GPIO0_00 4
+#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 SC_P_SCU_GPIO0_01 0
+#define SC_P_SCU_GPIO0_01_SCU_UART0_TX SC_P_SCU_GPIO0_01 1
+#define SC_P_SCU_GPIO0_01_M40_UART0_TX SC_P_SCU_GPIO0_01 2
+#define SC_P_SCU_GPIO0_01_ADMA_UART3_TX SC_P_SCU_GPIO0_01 3
+#define SC_P_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT SC_P_SCU_GPIO0_01 4
+#define SC_P_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY SC_P_SCU_PMIC_STANDBY 0
+#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 SC_P_SCU_BOOT_MODE0 0
+#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 SC_P_SCU_BOOT_MODE1 0
+#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 SC_P_SCU_BOOT_MODE2 0
+#define SC_P_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA SC_P_SCU_BOOT_MODE2 1
+#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 SC_P_SCU_BOOT_MODE3 0
+#define SC_P_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL SC_P_SCU_BOOT_MODE3 1
+#define SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K SC_P_SCU_BOOT_MODE3 3
+#define SC_P_CSI_D00_CI_PI_D02 SC_P_CSI_D00 0
+#define SC_P_CSI_D00_ADMA_SAI0_RXC SC_P_CSI_D00 2
+#define SC_P_CSI_D01_CI_PI_D03 SC_P_CSI_D01 0
+#define SC_P_CSI_D01_ADMA_SAI0_RXD SC_P_CSI_D01 2
+#define SC_P_CSI_D02_CI_PI_D04 SC_P_CSI_D02 0
+#define SC_P_CSI_D02_ADMA_SAI0_RXFS SC_P_CSI_D02 2
+#define SC_P_CSI_D03_CI_PI_D05 SC_P_CSI_D03 0
+#define SC_P_CSI_D03_ADMA_SAI2_RXC SC_P_CSI_D03 2
+#define SC_P_CSI_D04_CI_PI_D06 SC_P_CSI_D04 0
+#define SC_P_CSI_D04_ADMA_SAI2_RXD SC_P_CSI_D04 2
+#define SC_P_CSI_D05_CI_PI_D07 SC_P_CSI_D05 0
+#define SC_P_CSI_D05_ADMA_SAI2_RXFS SC_P_CSI_D05 2
+#define SC_P_CSI_D06_CI_PI_D08 SC_P_CSI_D06 0
+#define SC_P_CSI_D06_ADMA_SAI3_RXC SC_P_CSI_D06 2
+#define SC_P_CSI_D07_CI_PI_D09 SC_P_CSI_D07 0
+#define SC_P_CSI_D07_ADMA_SAI3_RXD SC_P_CSI_D07 2
+#define SC_P_CSI_HSYNC_CI_PI_HSYNC SC_P_CSI_HSYNC 0
+#define SC_P_CSI_HSYNC_CI_PI_D00 SC_P_CSI_HSYNC 1
+#define SC_P_CSI_HSYNC_ADMA_SAI3_RXFS SC_P_CSI_HSYNC 2
+#define SC_P_CSI_VSYNC_CI_PI_VSYNC SC_P_CSI_VSYNC 0
+#define SC_P_CSI_VSYNC_CI_PI_D01 SC_P_CSI_VSYNC 1
+#define SC_P_CSI_PCLK_CI_PI_PCLK SC_P_CSI_PCLK 0
+#define SC_P_CSI_PCLK_MIPI_CSI0_I2C0_SCL SC_P_CSI_PCLK 1
+#define SC_P_CSI_PCLK_ADMA_SPI1_SCK SC_P_CSI_PCLK 3
+#define SC_P_CSI_PCLK_LSIO_GPIO3_IO00 SC_P_CSI_PCLK 4
+#define SC_P_CSI_MCLK_CI_PI_MCLK SC_P_CSI_MCLK 0
+#define SC_P_CSI_MCLK_MIPI_CSI0_I2C0_SDA SC_P_CSI_MCLK 1
+#define SC_P_CSI_MCLK_ADMA_SPI1_SDO SC_P_CSI_MCLK 3
+#define SC_P_CSI_MCLK_LSIO_GPIO3_IO01 SC_P_CSI_MCLK 4
+#define SC_P_CSI_EN_CI_PI_EN SC_P_CSI_EN 0
+#define SC_P_CSI_EN_CI_PI_I2C_SCL SC_P_CSI_EN 1
+#define SC_P_CSI_EN_ADMA_I2C3_SCL SC_P_CSI_EN 2
+#define SC_P_CSI_EN_ADMA_SPI1_SDI SC_P_CSI_EN 3
+#define SC_P_CSI_EN_LSIO_GPIO3_IO02 SC_P_CSI_EN 4
+#define SC_P_CSI_RESET_CI_PI_RESET SC_P_CSI_RESET 0
+#define SC_P_CSI_RESET_CI_PI_I2C_SDA SC_P_CSI_RESET 1
+#define SC_P_CSI_RESET_ADMA_I2C3_SDA SC_P_CSI_RESET 2
+#define SC_P_CSI_RESET_ADMA_SPI1_CS0 SC_P_CSI_RESET 3
+#define SC_P_CSI_RESET_LSIO_GPIO3_IO03 SC_P_CSI_RESET 4
+#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT SC_P_MIPI_CSI0_MCLK_OUT 0
+#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 SC_P_MIPI_CSI0_MCLK_OUT 4
+#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL SC_P_MIPI_CSI0_I2C0_SCL 0
+#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02 SC_P_MIPI_CSI0_I2C0_SCL 1
+#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 SC_P_MIPI_CSI0_I2C0_SCL 4
+#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA SC_P_MIPI_CSI0_I2C0_SDA 0
+#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03 SC_P_MIPI_CSI0_I2C0_SDA 1
+#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 SC_P_MIPI_CSI0_I2C0_SDA 4
+#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 SC_P_MIPI_CSI0_GPIO0_01 0
+#define SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 1
+#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 SC_P_MIPI_CSI0_GPIO0_01 4
+#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 SC_P_MIPI_CSI0_GPIO0_00 0
+#define SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 1
+#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 SC_P_MIPI_CSI0_GPIO0_00 4
+#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 SC_P_QSPI0A_DATA0 0
+#define SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 SC_P_QSPI0A_DATA0 4
+#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 SC_P_QSPI0A_DATA1 0
+#define SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 SC_P_QSPI0A_DATA1 4
+#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 SC_P_QSPI0A_DATA2 0
+#define SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 SC_P_QSPI0A_DATA2 4
+#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 SC_P_QSPI0A_DATA3 0
+#define SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 SC_P_QSPI0A_DATA3 4
+#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS SC_P_QSPI0A_DQS 0
+#define SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 SC_P_QSPI0A_DQS 4
+#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B SC_P_QSPI0A_SS0_B 0
+#define SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 SC_P_QSPI0A_SS0_B 4
+#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B SC_P_QSPI0A_SS1_B 0
+#define SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 SC_P_QSPI0A_SS1_B 4
+#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK SC_P_QSPI0A_SCLK 0
+#define SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 SC_P_QSPI0A_SCLK 4
+#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK SC_P_QSPI0B_SCLK 0
+#define SC_P_QSPI0B_SCLK_LSIO_QSPI1A_SCLK SC_P_QSPI0B_SCLK 1
+#define SC_P_QSPI0B_SCLK_LSIO_KPP0_COL0 SC_P_QSPI0B_SCLK 2
+#define SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 SC_P_QSPI0B_SCLK 4
+#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 SC_P_QSPI0B_DATA0 0
+#define SC_P_QSPI0B_DATA0_LSIO_QSPI1A_DATA0 SC_P_QSPI0B_DATA0 1
+#define SC_P_QSPI0B_DATA0_LSIO_KPP0_COL1 SC_P_QSPI0B_DATA0 2
+#define SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 SC_P_QSPI0B_DATA0 4
+#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 SC_P_QSPI0B_DATA1 0
+#define SC_P_QSPI0B_DATA1_LSIO_QSPI1A_DATA1 SC_P_QSPI0B_DATA1 1
+#define SC_P_QSPI0B_DATA1_LSIO_KPP0_COL2 SC_P_QSPI0B_DATA1 2
+#define SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 SC_P_QSPI0B_DATA1 4
+#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 SC_P_QSPI0B_DATA2 0
+#define SC_P_QSPI0B_DATA2_LSIO_QSPI1A_DATA2 SC_P_QSPI0B_DATA2 1
+#define SC_P_QSPI0B_DATA2_LSIO_KPP0_COL3 SC_P_QSPI0B_DATA2 2
+#define SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 SC_P_QSPI0B_DATA2 4
+#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 SC_P_QSPI0B_DATA3 0
+#define SC_P_QSPI0B_DATA3_LSIO_QSPI1A_DATA3 SC_P_QSPI0B_DATA3 1
+#define SC_P_QSPI0B_DATA3_LSIO_KPP0_ROW0 SC_P_QSPI0B_DATA3 2
+#define SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 SC_P_QSPI0B_DATA3 4
+#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS SC_P_QSPI0B_DQS 0
+#define SC_P_QSPI0B_DQS_LSIO_QSPI1A_DQS SC_P_QSPI0B_DQS 1
+#define SC_P_QSPI0B_DQS_LSIO_KPP0_ROW1 SC_P_QSPI0B_DQS 2
+#define SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 SC_P_QSPI0B_DQS 4
+#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B SC_P_QSPI0B_SS0_B 0
+#define SC_P_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B SC_P_QSPI0B_SS0_B 1
+#define SC_P_QSPI0B_SS0_B_LSIO_KPP0_ROW2 SC_P_QSPI0B_SS0_B 2
+#define SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 SC_P_QSPI0B_SS0_B 4
+#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B SC_P_QSPI0B_SS1_B 0
+#define SC_P_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B SC_P_QSPI0B_SS1_B 1
+#define SC_P_QSPI0B_SS1_B_LSIO_KPP0_ROW3 SC_P_QSPI0B_SS1_B 2
+#define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 SC_P_QSPI0B_SS1_B 4
+
+#endif /* _SC_PADS_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 6/6] pinctrl: imx: add imx8qxp driver
2018-04-27 19:01 ` Dong Aisheng
@ 2018-04-27 19:01 ` Dong Aisheng
-1 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2018-04-27 19:01 UTC (permalink / raw)
To: linux-gpio
Cc: aisheng.dong, dongas86, Fabio Estevam, linus.walleij, stefan,
linux-imx, kernel, fabio.estevam, shawnguo, linux-arm-kernel
MX8QXP contains a system controller that is responsible for controlling
the pad setting of the IPs that are present. Communication between the
host processor running an OS and the system controller happens through
a SCU protocol. This patch adds the SCU based MX8QXP pinctrl driver.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
drivers/pinctrl/freescale/Kconfig | 7 +
drivers/pinctrl/freescale/Makefile | 1 +
drivers/pinctrl/freescale/pinctrl-imx8qxp.c | 232 ++++++++++++++++++++++++++++
3 files changed, 240 insertions(+)
create mode 100644 drivers/pinctrl/freescale/pinctrl-imx8qxp.c
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index 329e1a4..bffb5b9 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -121,6 +121,13 @@ config PINCTRL_IMX7ULP
help
Say Y here to enable the imx7ulp pinctrl driver
+config PINCTRL_IMX8QXP
+ bool "IMX8QXP pinctrl driver"
+ depends on SOC_IMX8QXP
+ select PINCTRL_IMX_SCU
+ help
+ Say Y here to enable the imx8qxp pinctrl driver
+
config PINCTRL_VF610
bool "Freescale Vybrid VF610 pinctrl driver"
depends on SOC_VF610
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index 1acd569..c55a744 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
+obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imx8qxp.c b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c
new file mode 100644
index 0000000..165f32c
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/pinctrl/pads-imx8qxp.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <soc/imx/sc/sci.h>
+
+#include "pinctrl-imx.h"
+
+static struct pinctrl_pin_desc imx8qxp_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(SC_P_PCIE_CTRL0_PERST_B),
+ IMX_PINCTRL_PIN(SC_P_PCIE_CTRL0_CLKREQ_B),
+ IMX_PINCTRL_PIN(SC_P_PCIE_CTRL0_WAKE_B),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP),
+ IMX_PINCTRL_PIN(SC_P_USB_SS3_TC0),
+ IMX_PINCTRL_PIN(SC_P_USB_SS3_TC1),
+ IMX_PINCTRL_PIN(SC_P_USB_SS3_TC2),
+ IMX_PINCTRL_PIN(SC_P_USB_SS3_TC3),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_3V3_USB3IO),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_CLK),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_CMD),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_DATA0),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_DATA1),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_DATA2),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_DATA3),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_DATA4),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_DATA5),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_DATA6),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_DATA7),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_STROBE),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_RESET_B),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1),
+ IMX_PINCTRL_PIN(SC_P_USDHC1_RESET_B),
+ IMX_PINCTRL_PIN(SC_P_USDHC1_VSELECT),
+ IMX_PINCTRL_PIN(SC_P_CTL_NAND_RE_P_N),
+ IMX_PINCTRL_PIN(SC_P_USDHC1_WP),
+ IMX_PINCTRL_PIN(SC_P_USDHC1_CD_B),
+ IMX_PINCTRL_PIN(SC_P_CTL_NAND_DQS_P_N),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP),
+ IMX_PINCTRL_PIN(SC_P_USDHC1_CLK),
+ IMX_PINCTRL_PIN(SC_P_USDHC1_CMD),
+ IMX_PINCTRL_PIN(SC_P_USDHC1_DATA0),
+ IMX_PINCTRL_PIN(SC_P_USDHC1_DATA1),
+ IMX_PINCTRL_PIN(SC_P_USDHC1_DATA2),
+ IMX_PINCTRL_PIN(SC_P_USDHC1_DATA3),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_TXC),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_TX_CTL),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_TXD0),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_TXD1),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_TXD2),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_TXD3),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_RXC),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_RX_CTL),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_RXD0),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_RXD1),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_RXD2),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_RXD3),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1),
+ IMX_PINCTRL_PIN(SC_P_ENET0_REFCLK_125M_25M),
+ IMX_PINCTRL_PIN(SC_P_ENET0_MDIO),
+ IMX_PINCTRL_PIN(SC_P_ENET0_MDC),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT),
+ IMX_PINCTRL_PIN(SC_P_ESAI0_FSR),
+ IMX_PINCTRL_PIN(SC_P_ESAI0_FST),
+ IMX_PINCTRL_PIN(SC_P_ESAI0_SCKR),
+ IMX_PINCTRL_PIN(SC_P_ESAI0_SCKT),
+ IMX_PINCTRL_PIN(SC_P_ESAI0_TX0),
+ IMX_PINCTRL_PIN(SC_P_ESAI0_TX1),
+ IMX_PINCTRL_PIN(SC_P_ESAI0_TX2_RX3),
+ IMX_PINCTRL_PIN(SC_P_ESAI0_TX3_RX2),
+ IMX_PINCTRL_PIN(SC_P_ESAI0_TX4_RX1),
+ IMX_PINCTRL_PIN(SC_P_ESAI0_TX5_RX0),
+ IMX_PINCTRL_PIN(SC_P_SPDIF0_RX),
+ IMX_PINCTRL_PIN(SC_P_SPDIF0_TX),
+ IMX_PINCTRL_PIN(SC_P_SPDIF0_EXT_CLK),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB),
+ IMX_PINCTRL_PIN(SC_P_SPI3_SCK),
+ IMX_PINCTRL_PIN(SC_P_SPI3_SDO),
+ IMX_PINCTRL_PIN(SC_P_SPI3_SDI),
+ IMX_PINCTRL_PIN(SC_P_SPI3_CS0),
+ IMX_PINCTRL_PIN(SC_P_SPI3_CS1),
+ IMX_PINCTRL_PIN(SC_P_MCLK_IN1),
+ IMX_PINCTRL_PIN(SC_P_MCLK_IN0),
+ IMX_PINCTRL_PIN(SC_P_MCLK_OUT0),
+ IMX_PINCTRL_PIN(SC_P_UART1_TX),
+ IMX_PINCTRL_PIN(SC_P_UART1_RX),
+ IMX_PINCTRL_PIN(SC_P_UART1_RTS_B),
+ IMX_PINCTRL_PIN(SC_P_UART1_CTS_B),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK),
+ IMX_PINCTRL_PIN(SC_P_SAI0_TXD),
+ IMX_PINCTRL_PIN(SC_P_SAI0_TXC),
+ IMX_PINCTRL_PIN(SC_P_SAI0_RXD),
+ IMX_PINCTRL_PIN(SC_P_SAI0_TXFS),
+ IMX_PINCTRL_PIN(SC_P_SAI1_RXD),
+ IMX_PINCTRL_PIN(SC_P_SAI1_RXC),
+ IMX_PINCTRL_PIN(SC_P_SAI1_RXFS),
+ IMX_PINCTRL_PIN(SC_P_SPI2_CS0),
+ IMX_PINCTRL_PIN(SC_P_SPI2_SDO),
+ IMX_PINCTRL_PIN(SC_P_SPI2_SDI),
+ IMX_PINCTRL_PIN(SC_P_SPI2_SCK),
+ IMX_PINCTRL_PIN(SC_P_SPI0_SCK),
+ IMX_PINCTRL_PIN(SC_P_SPI0_SDI),
+ IMX_PINCTRL_PIN(SC_P_SPI0_SDO),
+ IMX_PINCTRL_PIN(SC_P_SPI0_CS1),
+ IMX_PINCTRL_PIN(SC_P_SPI0_CS0),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT),
+ IMX_PINCTRL_PIN(SC_P_ADC_IN1),
+ IMX_PINCTRL_PIN(SC_P_ADC_IN0),
+ IMX_PINCTRL_PIN(SC_P_ADC_IN3),
+ IMX_PINCTRL_PIN(SC_P_ADC_IN2),
+ IMX_PINCTRL_PIN(SC_P_ADC_IN5),
+ IMX_PINCTRL_PIN(SC_P_ADC_IN4),
+ IMX_PINCTRL_PIN(SC_P_FLEXCAN0_RX),
+ IMX_PINCTRL_PIN(SC_P_FLEXCAN0_TX),
+ IMX_PINCTRL_PIN(SC_P_FLEXCAN1_RX),
+ IMX_PINCTRL_PIN(SC_P_FLEXCAN1_TX),
+ IMX_PINCTRL_PIN(SC_P_FLEXCAN2_RX),
+ IMX_PINCTRL_PIN(SC_P_FLEXCAN2_TX),
+ IMX_PINCTRL_PIN(SC_P_UART0_RX),
+ IMX_PINCTRL_PIN(SC_P_UART0_TX),
+ IMX_PINCTRL_PIN(SC_P_UART2_TX),
+ IMX_PINCTRL_PIN(SC_P_UART2_RX),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH),
+ IMX_PINCTRL_PIN(SC_P_MIPI_DSI0_I2C0_SCL),
+ IMX_PINCTRL_PIN(SC_P_MIPI_DSI0_I2C0_SDA),
+ IMX_PINCTRL_PIN(SC_P_MIPI_DSI0_GPIO0_00),
+ IMX_PINCTRL_PIN(SC_P_MIPI_DSI0_GPIO0_01),
+ IMX_PINCTRL_PIN(SC_P_MIPI_DSI1_I2C0_SCL),
+ IMX_PINCTRL_PIN(SC_P_MIPI_DSI1_I2C0_SDA),
+ IMX_PINCTRL_PIN(SC_P_MIPI_DSI1_GPIO0_00),
+ IMX_PINCTRL_PIN(SC_P_MIPI_DSI1_GPIO0_01),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO),
+ IMX_PINCTRL_PIN(SC_P_JTAG_TRST_B),
+ IMX_PINCTRL_PIN(SC_P_PMIC_I2C_SCL),
+ IMX_PINCTRL_PIN(SC_P_PMIC_I2C_SDA),
+ IMX_PINCTRL_PIN(SC_P_PMIC_INT_B),
+ IMX_PINCTRL_PIN(SC_P_SCU_GPIO0_00),
+ IMX_PINCTRL_PIN(SC_P_SCU_GPIO0_01),
+ IMX_PINCTRL_PIN(SC_P_SCU_PMIC_STANDBY),
+ IMX_PINCTRL_PIN(SC_P_SCU_BOOT_MODE0),
+ IMX_PINCTRL_PIN(SC_P_SCU_BOOT_MODE1),
+ IMX_PINCTRL_PIN(SC_P_SCU_BOOT_MODE2),
+ IMX_PINCTRL_PIN(SC_P_SCU_BOOT_MODE3),
+ IMX_PINCTRL_PIN(SC_P_CSI_D00),
+ IMX_PINCTRL_PIN(SC_P_CSI_D01),
+ IMX_PINCTRL_PIN(SC_P_CSI_D02),
+ IMX_PINCTRL_PIN(SC_P_CSI_D03),
+ IMX_PINCTRL_PIN(SC_P_CSI_D04),
+ IMX_PINCTRL_PIN(SC_P_CSI_D05),
+ IMX_PINCTRL_PIN(SC_P_CSI_D06),
+ IMX_PINCTRL_PIN(SC_P_CSI_D07),
+ IMX_PINCTRL_PIN(SC_P_CSI_HSYNC),
+ IMX_PINCTRL_PIN(SC_P_CSI_VSYNC),
+ IMX_PINCTRL_PIN(SC_P_CSI_PCLK),
+ IMX_PINCTRL_PIN(SC_P_CSI_MCLK),
+ IMX_PINCTRL_PIN(SC_P_CSI_EN),
+ IMX_PINCTRL_PIN(SC_P_CSI_RESET),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD),
+ IMX_PINCTRL_PIN(SC_P_MIPI_CSI0_MCLK_OUT),
+ IMX_PINCTRL_PIN(SC_P_MIPI_CSI0_I2C0_SCL),
+ IMX_PINCTRL_PIN(SC_P_MIPI_CSI0_I2C0_SDA),
+ IMX_PINCTRL_PIN(SC_P_MIPI_CSI0_GPIO0_01),
+ IMX_PINCTRL_PIN(SC_P_MIPI_CSI0_GPIO0_00),
+ IMX_PINCTRL_PIN(SC_P_QSPI0A_DATA0),
+ IMX_PINCTRL_PIN(SC_P_QSPI0A_DATA1),
+ IMX_PINCTRL_PIN(SC_P_QSPI0A_DATA2),
+ IMX_PINCTRL_PIN(SC_P_QSPI0A_DATA3),
+ IMX_PINCTRL_PIN(SC_P_QSPI0A_DQS),
+ IMX_PINCTRL_PIN(SC_P_QSPI0A_SS0_B),
+ IMX_PINCTRL_PIN(SC_P_QSPI0A_SS1_B),
+ IMX_PINCTRL_PIN(SC_P_QSPI0A_SCLK),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A),
+ IMX_PINCTRL_PIN(SC_P_QSPI0B_SCLK),
+ IMX_PINCTRL_PIN(SC_P_QSPI0B_DATA0),
+ IMX_PINCTRL_PIN(SC_P_QSPI0B_DATA1),
+ IMX_PINCTRL_PIN(SC_P_QSPI0B_DATA2),
+ IMX_PINCTRL_PIN(SC_P_QSPI0B_DATA3),
+ IMX_PINCTRL_PIN(SC_P_QSPI0B_DQS),
+ IMX_PINCTRL_PIN(SC_P_QSPI0B_SS0_B),
+ IMX_PINCTRL_PIN(SC_P_QSPI0B_SS1_B),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B),
+};
+
+static struct imx_pinctrl_soc_info imx8qxp_pinctrl_info = {
+ .pins = imx8qxp_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx8qxp_pinctrl_pads),
+ .flags = IMX_USE_SCU,
+};
+
+static const struct of_device_id imx8qxp_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx8qxp-iomuxc", },
+ { /* sentinel */ }
+};
+
+static int imx8qxp_pinctrl_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = imx_pinctrl_sc_ipc_init(pdev);
+ if (ret)
+ return ret;
+
+ return imx_pinctrl_probe(pdev, &imx8qxp_pinctrl_info);
+}
+
+static struct platform_driver imx8qxp_pinctrl_driver = {
+ .driver = {
+ .name = "imx8qxp-pinctrl",
+ .of_match_table = of_match_ptr(imx8qxp_pinctrl_of_match),
+ .suppress_bind_attrs = true,
+ },
+ .probe = imx8qxp_pinctrl_probe,
+};
+
+static int __init imx8qxp_pinctrl_init(void)
+{
+ return platform_driver_register(&imx8qxp_pinctrl_driver);
+}
+arch_initcall(imx8qxp_pinctrl_init);
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH 6/6] pinctrl: imx: add imx8qxp driver
@ 2018-04-27 19:01 ` Dong Aisheng
0 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2018-04-27 19:01 UTC (permalink / raw)
To: linux-arm-kernel
MX8QXP contains a system controller that is responsible for controlling
the pad setting of the IPs that are present. Communication between the
host processor running an OS and the system controller happens through
a SCU protocol. This patch adds the SCU based MX8QXP pinctrl driver.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
drivers/pinctrl/freescale/Kconfig | 7 +
drivers/pinctrl/freescale/Makefile | 1 +
drivers/pinctrl/freescale/pinctrl-imx8qxp.c | 232 ++++++++++++++++++++++++++++
3 files changed, 240 insertions(+)
create mode 100644 drivers/pinctrl/freescale/pinctrl-imx8qxp.c
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index 329e1a4..bffb5b9 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -121,6 +121,13 @@ config PINCTRL_IMX7ULP
help
Say Y here to enable the imx7ulp pinctrl driver
+config PINCTRL_IMX8QXP
+ bool "IMX8QXP pinctrl driver"
+ depends on SOC_IMX8QXP
+ select PINCTRL_IMX_SCU
+ help
+ Say Y here to enable the imx8qxp pinctrl driver
+
config PINCTRL_VF610
bool "Freescale Vybrid VF610 pinctrl driver"
depends on SOC_VF610
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index 1acd569..c55a744 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
+obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imx8qxp.c b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c
new file mode 100644
index 0000000..165f32c
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/pinctrl/pads-imx8qxp.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <soc/imx/sc/sci.h>
+
+#include "pinctrl-imx.h"
+
+static struct pinctrl_pin_desc imx8qxp_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(SC_P_PCIE_CTRL0_PERST_B),
+ IMX_PINCTRL_PIN(SC_P_PCIE_CTRL0_CLKREQ_B),
+ IMX_PINCTRL_PIN(SC_P_PCIE_CTRL0_WAKE_B),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP),
+ IMX_PINCTRL_PIN(SC_P_USB_SS3_TC0),
+ IMX_PINCTRL_PIN(SC_P_USB_SS3_TC1),
+ IMX_PINCTRL_PIN(SC_P_USB_SS3_TC2),
+ IMX_PINCTRL_PIN(SC_P_USB_SS3_TC3),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_3V3_USB3IO),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_CLK),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_CMD),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_DATA0),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_DATA1),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_DATA2),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_DATA3),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_DATA4),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_DATA5),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_DATA6),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_DATA7),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_STROBE),
+ IMX_PINCTRL_PIN(SC_P_EMMC0_RESET_B),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1),
+ IMX_PINCTRL_PIN(SC_P_USDHC1_RESET_B),
+ IMX_PINCTRL_PIN(SC_P_USDHC1_VSELECT),
+ IMX_PINCTRL_PIN(SC_P_CTL_NAND_RE_P_N),
+ IMX_PINCTRL_PIN(SC_P_USDHC1_WP),
+ IMX_PINCTRL_PIN(SC_P_USDHC1_CD_B),
+ IMX_PINCTRL_PIN(SC_P_CTL_NAND_DQS_P_N),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP),
+ IMX_PINCTRL_PIN(SC_P_USDHC1_CLK),
+ IMX_PINCTRL_PIN(SC_P_USDHC1_CMD),
+ IMX_PINCTRL_PIN(SC_P_USDHC1_DATA0),
+ IMX_PINCTRL_PIN(SC_P_USDHC1_DATA1),
+ IMX_PINCTRL_PIN(SC_P_USDHC1_DATA2),
+ IMX_PINCTRL_PIN(SC_P_USDHC1_DATA3),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_TXC),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_TX_CTL),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_TXD0),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_TXD1),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_TXD2),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_TXD3),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_RXC),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_RX_CTL),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_RXD0),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_RXD1),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_RXD2),
+ IMX_PINCTRL_PIN(SC_P_ENET0_RGMII_RXD3),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1),
+ IMX_PINCTRL_PIN(SC_P_ENET0_REFCLK_125M_25M),
+ IMX_PINCTRL_PIN(SC_P_ENET0_MDIO),
+ IMX_PINCTRL_PIN(SC_P_ENET0_MDC),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT),
+ IMX_PINCTRL_PIN(SC_P_ESAI0_FSR),
+ IMX_PINCTRL_PIN(SC_P_ESAI0_FST),
+ IMX_PINCTRL_PIN(SC_P_ESAI0_SCKR),
+ IMX_PINCTRL_PIN(SC_P_ESAI0_SCKT),
+ IMX_PINCTRL_PIN(SC_P_ESAI0_TX0),
+ IMX_PINCTRL_PIN(SC_P_ESAI0_TX1),
+ IMX_PINCTRL_PIN(SC_P_ESAI0_TX2_RX3),
+ IMX_PINCTRL_PIN(SC_P_ESAI0_TX3_RX2),
+ IMX_PINCTRL_PIN(SC_P_ESAI0_TX4_RX1),
+ IMX_PINCTRL_PIN(SC_P_ESAI0_TX5_RX0),
+ IMX_PINCTRL_PIN(SC_P_SPDIF0_RX),
+ IMX_PINCTRL_PIN(SC_P_SPDIF0_TX),
+ IMX_PINCTRL_PIN(SC_P_SPDIF0_EXT_CLK),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB),
+ IMX_PINCTRL_PIN(SC_P_SPI3_SCK),
+ IMX_PINCTRL_PIN(SC_P_SPI3_SDO),
+ IMX_PINCTRL_PIN(SC_P_SPI3_SDI),
+ IMX_PINCTRL_PIN(SC_P_SPI3_CS0),
+ IMX_PINCTRL_PIN(SC_P_SPI3_CS1),
+ IMX_PINCTRL_PIN(SC_P_MCLK_IN1),
+ IMX_PINCTRL_PIN(SC_P_MCLK_IN0),
+ IMX_PINCTRL_PIN(SC_P_MCLK_OUT0),
+ IMX_PINCTRL_PIN(SC_P_UART1_TX),
+ IMX_PINCTRL_PIN(SC_P_UART1_RX),
+ IMX_PINCTRL_PIN(SC_P_UART1_RTS_B),
+ IMX_PINCTRL_PIN(SC_P_UART1_CTS_B),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK),
+ IMX_PINCTRL_PIN(SC_P_SAI0_TXD),
+ IMX_PINCTRL_PIN(SC_P_SAI0_TXC),
+ IMX_PINCTRL_PIN(SC_P_SAI0_RXD),
+ IMX_PINCTRL_PIN(SC_P_SAI0_TXFS),
+ IMX_PINCTRL_PIN(SC_P_SAI1_RXD),
+ IMX_PINCTRL_PIN(SC_P_SAI1_RXC),
+ IMX_PINCTRL_PIN(SC_P_SAI1_RXFS),
+ IMX_PINCTRL_PIN(SC_P_SPI2_CS0),
+ IMX_PINCTRL_PIN(SC_P_SPI2_SDO),
+ IMX_PINCTRL_PIN(SC_P_SPI2_SDI),
+ IMX_PINCTRL_PIN(SC_P_SPI2_SCK),
+ IMX_PINCTRL_PIN(SC_P_SPI0_SCK),
+ IMX_PINCTRL_PIN(SC_P_SPI0_SDI),
+ IMX_PINCTRL_PIN(SC_P_SPI0_SDO),
+ IMX_PINCTRL_PIN(SC_P_SPI0_CS1),
+ IMX_PINCTRL_PIN(SC_P_SPI0_CS0),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT),
+ IMX_PINCTRL_PIN(SC_P_ADC_IN1),
+ IMX_PINCTRL_PIN(SC_P_ADC_IN0),
+ IMX_PINCTRL_PIN(SC_P_ADC_IN3),
+ IMX_PINCTRL_PIN(SC_P_ADC_IN2),
+ IMX_PINCTRL_PIN(SC_P_ADC_IN5),
+ IMX_PINCTRL_PIN(SC_P_ADC_IN4),
+ IMX_PINCTRL_PIN(SC_P_FLEXCAN0_RX),
+ IMX_PINCTRL_PIN(SC_P_FLEXCAN0_TX),
+ IMX_PINCTRL_PIN(SC_P_FLEXCAN1_RX),
+ IMX_PINCTRL_PIN(SC_P_FLEXCAN1_TX),
+ IMX_PINCTRL_PIN(SC_P_FLEXCAN2_RX),
+ IMX_PINCTRL_PIN(SC_P_FLEXCAN2_TX),
+ IMX_PINCTRL_PIN(SC_P_UART0_RX),
+ IMX_PINCTRL_PIN(SC_P_UART0_TX),
+ IMX_PINCTRL_PIN(SC_P_UART2_TX),
+ IMX_PINCTRL_PIN(SC_P_UART2_RX),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH),
+ IMX_PINCTRL_PIN(SC_P_MIPI_DSI0_I2C0_SCL),
+ IMX_PINCTRL_PIN(SC_P_MIPI_DSI0_I2C0_SDA),
+ IMX_PINCTRL_PIN(SC_P_MIPI_DSI0_GPIO0_00),
+ IMX_PINCTRL_PIN(SC_P_MIPI_DSI0_GPIO0_01),
+ IMX_PINCTRL_PIN(SC_P_MIPI_DSI1_I2C0_SCL),
+ IMX_PINCTRL_PIN(SC_P_MIPI_DSI1_I2C0_SDA),
+ IMX_PINCTRL_PIN(SC_P_MIPI_DSI1_GPIO0_00),
+ IMX_PINCTRL_PIN(SC_P_MIPI_DSI1_GPIO0_01),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO),
+ IMX_PINCTRL_PIN(SC_P_JTAG_TRST_B),
+ IMX_PINCTRL_PIN(SC_P_PMIC_I2C_SCL),
+ IMX_PINCTRL_PIN(SC_P_PMIC_I2C_SDA),
+ IMX_PINCTRL_PIN(SC_P_PMIC_INT_B),
+ IMX_PINCTRL_PIN(SC_P_SCU_GPIO0_00),
+ IMX_PINCTRL_PIN(SC_P_SCU_GPIO0_01),
+ IMX_PINCTRL_PIN(SC_P_SCU_PMIC_STANDBY),
+ IMX_PINCTRL_PIN(SC_P_SCU_BOOT_MODE0),
+ IMX_PINCTRL_PIN(SC_P_SCU_BOOT_MODE1),
+ IMX_PINCTRL_PIN(SC_P_SCU_BOOT_MODE2),
+ IMX_PINCTRL_PIN(SC_P_SCU_BOOT_MODE3),
+ IMX_PINCTRL_PIN(SC_P_CSI_D00),
+ IMX_PINCTRL_PIN(SC_P_CSI_D01),
+ IMX_PINCTRL_PIN(SC_P_CSI_D02),
+ IMX_PINCTRL_PIN(SC_P_CSI_D03),
+ IMX_PINCTRL_PIN(SC_P_CSI_D04),
+ IMX_PINCTRL_PIN(SC_P_CSI_D05),
+ IMX_PINCTRL_PIN(SC_P_CSI_D06),
+ IMX_PINCTRL_PIN(SC_P_CSI_D07),
+ IMX_PINCTRL_PIN(SC_P_CSI_HSYNC),
+ IMX_PINCTRL_PIN(SC_P_CSI_VSYNC),
+ IMX_PINCTRL_PIN(SC_P_CSI_PCLK),
+ IMX_PINCTRL_PIN(SC_P_CSI_MCLK),
+ IMX_PINCTRL_PIN(SC_P_CSI_EN),
+ IMX_PINCTRL_PIN(SC_P_CSI_RESET),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD),
+ IMX_PINCTRL_PIN(SC_P_MIPI_CSI0_MCLK_OUT),
+ IMX_PINCTRL_PIN(SC_P_MIPI_CSI0_I2C0_SCL),
+ IMX_PINCTRL_PIN(SC_P_MIPI_CSI0_I2C0_SDA),
+ IMX_PINCTRL_PIN(SC_P_MIPI_CSI0_GPIO0_01),
+ IMX_PINCTRL_PIN(SC_P_MIPI_CSI0_GPIO0_00),
+ IMX_PINCTRL_PIN(SC_P_QSPI0A_DATA0),
+ IMX_PINCTRL_PIN(SC_P_QSPI0A_DATA1),
+ IMX_PINCTRL_PIN(SC_P_QSPI0A_DATA2),
+ IMX_PINCTRL_PIN(SC_P_QSPI0A_DATA3),
+ IMX_PINCTRL_PIN(SC_P_QSPI0A_DQS),
+ IMX_PINCTRL_PIN(SC_P_QSPI0A_SS0_B),
+ IMX_PINCTRL_PIN(SC_P_QSPI0A_SS1_B),
+ IMX_PINCTRL_PIN(SC_P_QSPI0A_SCLK),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A),
+ IMX_PINCTRL_PIN(SC_P_QSPI0B_SCLK),
+ IMX_PINCTRL_PIN(SC_P_QSPI0B_DATA0),
+ IMX_PINCTRL_PIN(SC_P_QSPI0B_DATA1),
+ IMX_PINCTRL_PIN(SC_P_QSPI0B_DATA2),
+ IMX_PINCTRL_PIN(SC_P_QSPI0B_DATA3),
+ IMX_PINCTRL_PIN(SC_P_QSPI0B_DQS),
+ IMX_PINCTRL_PIN(SC_P_QSPI0B_SS0_B),
+ IMX_PINCTRL_PIN(SC_P_QSPI0B_SS1_B),
+ IMX_PINCTRL_PIN(SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B),
+};
+
+static struct imx_pinctrl_soc_info imx8qxp_pinctrl_info = {
+ .pins = imx8qxp_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx8qxp_pinctrl_pads),
+ .flags = IMX_USE_SCU,
+};
+
+static const struct of_device_id imx8qxp_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx8qxp-iomuxc", },
+ { /* sentinel */ }
+};
+
+static int imx8qxp_pinctrl_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = imx_pinctrl_sc_ipc_init(pdev);
+ if (ret)
+ return ret;
+
+ return imx_pinctrl_probe(pdev, &imx8qxp_pinctrl_info);
+}
+
+static struct platform_driver imx8qxp_pinctrl_driver = {
+ .driver = {
+ .name = "imx8qxp-pinctrl",
+ .of_match_table = of_match_ptr(imx8qxp_pinctrl_of_match),
+ .suppress_bind_attrs = true,
+ },
+ .probe = imx8qxp_pinctrl_probe,
+};
+
+static int __init imx8qxp_pinctrl_init(void)
+{
+ return platform_driver_register(&imx8qxp_pinctrl_driver);
+}
+arch_initcall(imx8qxp_pinctrl_init);
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [PATCH 5/6] dt-bindings: pinctrl: add imx8qxp pinctrl binding doc
2018-04-27 19:01 ` Dong Aisheng
@ 2018-05-01 15:58 ` Rob Herring
-1 siblings, 0 replies; 36+ messages in thread
From: Rob Herring @ 2018-05-01 15:58 UTC (permalink / raw)
To: Dong Aisheng
Cc: Mark Rutland, devicetree, dongas86, Fabio Estevam, linus.walleij,
stefan, linux-gpio, linux-imx, kernel, fabio.estevam, shawnguo,
linux-arm-kernel
On Sat, Apr 28, 2018 at 03:01:52AM +0800, Dong Aisheng wrote:
> Add imx8qxp pinctrl binding doc.
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: devicetree@vger.kernel.org
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> Note: there's a checkpatch error as follows:
> ERROR: Macros with complex values should be enclosed in parentheses
> +#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0
>
> However, this is the intended format. Seems checkpatch did not recognize
> it well. Not sure if we could accept it.
> ---
> .../bindings/pinctrl/fsl,imx8qxp-pinctrl.txt | 39 ++
> include/dt-bindings/pinctrl/pads-imx8qxp.h | 751 +++++++++++++++++++++
> 2 files changed, 790 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt
> create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt
> new file mode 100644
> index 0000000..62c0f55
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt
> @@ -0,0 +1,39 @@
> +* NXP i.MX8QXP IOMUX Controller
> +
> +MX8QXP contains a system controller that is responsible for controlling
> +the pad setting of the IPs that are present. Communication between the
> +host processor running an OS and the system controller happens through
> +a SCU protocol.
> +
> +Please also refer to fsl,imx-pinctrl.txt in this directory for i.MX common
> +pinctrl binding.
> +
> +=== Pin Controller Node ===
> +
> +Required properties:
> +- compatible: "fsl,imx8qxp-iomuxc"
How is this block accessed?
I see the answer in the dts is the SCU. Is this really a IOMUXC as
defined by prior i.MX chips if it is hidden behind firmware?
> +
> +=== Pin Configuration Node ===
> +- fsl,pins: Each entry consists of 3 integers which represents the mux and
> + config setting for one pin. The first 2 integers <pin_id mux_mode>
> + are specified using a PIN_FUNC_ID macro, which can be found
> + in <dt-bindings/pinctrl/pads-imx8qxp.h>. The last integer CONFIG
> + is the pad setting value like pull-up on this pin.
> + Please refer to i.MX8QXP Reference Manual for detailed
> + CONFIG settings.
> +
> +Examples:
> +#include <dt-bindings/pinctrl/pads-imx8qxp.h>
> +
> +/* Pin Controller Node */
> +iomuxc: iomuxc {
pinctrl {
> + compatible = "fsl,imx8qxp-iomuxc";
> +
> + /* Pin Configuration Node */
> + pinctrl_lpuart0: lpuart0grp {
> + fsl,pins = <
> + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
> + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
> + >;
> + };
> +};
> diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h
> new file mode 100644
> index 0000000..8f477c3
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h
> @@ -0,0 +1,751 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + * Copyright 2017~2018 NXP
> + */
> +
> +#ifndef _SC_PADS_H
> +#define _SC_PADS_H
> +
> +/* pin id */
> +#define SC_P_PCIE_CTRL0_PERST_B 0
> +#define SC_P_PCIE_CTRL0_CLKREQ_B 1
> +#define SC_P_PCIE_CTRL0_WAKE_B 2
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3
> +#define SC_P_USB_SS3_TC0 4
> +#define SC_P_USB_SS3_TC1 5
> +#define SC_P_USB_SS3_TC2 6
> +#define SC_P_USB_SS3_TC3 7
> +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8
> +#define SC_P_EMMC0_CLK 9
> +#define SC_P_EMMC0_CMD 10
> +#define SC_P_EMMC0_DATA0 11
> +#define SC_P_EMMC0_DATA1 12
> +#define SC_P_EMMC0_DATA2 13
> +#define SC_P_EMMC0_DATA3 14
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15
> +#define SC_P_EMMC0_DATA4 16
> +#define SC_P_EMMC0_DATA5 17
> +#define SC_P_EMMC0_DATA6 18
> +#define SC_P_EMMC0_DATA7 19
> +#define SC_P_EMMC0_STROBE 20
> +#define SC_P_EMMC0_RESET_B 21
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22
> +#define SC_P_USDHC1_RESET_B 23
> +#define SC_P_USDHC1_VSELECT 24
> +#define SC_P_CTL_NAND_RE_P_N 25
> +#define SC_P_USDHC1_WP 26
> +#define SC_P_USDHC1_CD_B 27
> +#define SC_P_CTL_NAND_DQS_P_N 28
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29
> +#define SC_P_USDHC1_CLK 30
> +#define SC_P_USDHC1_CMD 31
> +#define SC_P_USDHC1_DATA0 32
> +#define SC_P_USDHC1_DATA1 33
> +#define SC_P_USDHC1_DATA2 34
> +#define SC_P_USDHC1_DATA3 35
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36
> +#define SC_P_ENET0_RGMII_TXC 37
> +#define SC_P_ENET0_RGMII_TX_CTL 38
> +#define SC_P_ENET0_RGMII_TXD0 39
> +#define SC_P_ENET0_RGMII_TXD1 40
> +#define SC_P_ENET0_RGMII_TXD2 41
> +#define SC_P_ENET0_RGMII_TXD3 42
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43
> +#define SC_P_ENET0_RGMII_RXC 44
> +#define SC_P_ENET0_RGMII_RX_CTL 45
> +#define SC_P_ENET0_RGMII_RXD0 46
> +#define SC_P_ENET0_RGMII_RXD1 47
> +#define SC_P_ENET0_RGMII_RXD2 48
> +#define SC_P_ENET0_RGMII_RXD3 49
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50
> +#define SC_P_ENET0_REFCLK_125M_25M 51
> +#define SC_P_ENET0_MDIO 52
> +#define SC_P_ENET0_MDC 53
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54
> +#define SC_P_ESAI0_FSR 55
> +#define SC_P_ESAI0_FST 56
> +#define SC_P_ESAI0_SCKR 57
> +#define SC_P_ESAI0_SCKT 58
> +#define SC_P_ESAI0_TX0 59
> +#define SC_P_ESAI0_TX1 60
> +#define SC_P_ESAI0_TX2_RX3 61
> +#define SC_P_ESAI0_TX3_RX2 62
> +#define SC_P_ESAI0_TX4_RX1 63
> +#define SC_P_ESAI0_TX5_RX0 64
> +#define SC_P_SPDIF0_RX 65
> +#define SC_P_SPDIF0_TX 66
> +#define SC_P_SPDIF0_EXT_CLK 67
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68
> +#define SC_P_SPI3_SCK 69
> +#define SC_P_SPI3_SDO 70
> +#define SC_P_SPI3_SDI 71
> +#define SC_P_SPI3_CS0 72
> +#define SC_P_SPI3_CS1 73
> +#define SC_P_MCLK_IN1 74
> +#define SC_P_MCLK_IN0 75
> +#define SC_P_MCLK_OUT0 76
> +#define SC_P_UART1_TX 77
> +#define SC_P_UART1_RX 78
> +#define SC_P_UART1_RTS_B 79
> +#define SC_P_UART1_CTS_B 80
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81
> +#define SC_P_SAI0_TXD 82
> +#define SC_P_SAI0_TXC 83
> +#define SC_P_SAI0_RXD 84
> +#define SC_P_SAI0_TXFS 85
> +#define SC_P_SAI1_RXD 86
> +#define SC_P_SAI1_RXC 87
> +#define SC_P_SAI1_RXFS 88
> +#define SC_P_SPI2_CS0 89
> +#define SC_P_SPI2_SDO 90
> +#define SC_P_SPI2_SDI 91
> +#define SC_P_SPI2_SCK 92
> +#define SC_P_SPI0_SCK 93
> +#define SC_P_SPI0_SDI 94
> +#define SC_P_SPI0_SDO 95
> +#define SC_P_SPI0_CS1 96
> +#define SC_P_SPI0_CS0 97
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98
> +#define SC_P_ADC_IN1 99
> +#define SC_P_ADC_IN0 100
> +#define SC_P_ADC_IN3 101
> +#define SC_P_ADC_IN2 102
> +#define SC_P_ADC_IN5 103
> +#define SC_P_ADC_IN4 104
> +#define SC_P_FLEXCAN0_RX 105
> +#define SC_P_FLEXCAN0_TX 106
> +#define SC_P_FLEXCAN1_RX 107
> +#define SC_P_FLEXCAN1_TX 108
> +#define SC_P_FLEXCAN2_RX 109
> +#define SC_P_FLEXCAN2_TX 110
> +#define SC_P_UART0_RX 111
> +#define SC_P_UART0_TX 112
> +#define SC_P_UART2_TX 113
> +#define SC_P_UART2_RX 114
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115
> +#define SC_P_MIPI_DSI0_I2C0_SCL 116
> +#define SC_P_MIPI_DSI0_I2C0_SDA 117
> +#define SC_P_MIPI_DSI0_GPIO0_00 118
> +#define SC_P_MIPI_DSI0_GPIO0_01 119
> +#define SC_P_MIPI_DSI1_I2C0_SCL 120
> +#define SC_P_MIPI_DSI1_I2C0_SDA 121
> +#define SC_P_MIPI_DSI1_GPIO0_00 122
> +#define SC_P_MIPI_DSI1_GPIO0_01 123
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124
> +#define SC_P_JTAG_TRST_B 125
> +#define SC_P_PMIC_I2C_SCL 126
> +#define SC_P_PMIC_I2C_SDA 127
> +#define SC_P_PMIC_INT_B 128
> +#define SC_P_SCU_GPIO0_00 129
> +#define SC_P_SCU_GPIO0_01 130
> +#define SC_P_SCU_PMIC_STANDBY 131
> +#define SC_P_SCU_BOOT_MODE0 132
> +#define SC_P_SCU_BOOT_MODE1 133
> +#define SC_P_SCU_BOOT_MODE2 134
> +#define SC_P_SCU_BOOT_MODE3 135
> +#define SC_P_CSI_D00 136
> +#define SC_P_CSI_D01 137
> +#define SC_P_CSI_D02 138
> +#define SC_P_CSI_D03 139
> +#define SC_P_CSI_D04 140
> +#define SC_P_CSI_D05 141
> +#define SC_P_CSI_D06 142
> +#define SC_P_CSI_D07 143
> +#define SC_P_CSI_HSYNC 144
> +#define SC_P_CSI_VSYNC 145
> +#define SC_P_CSI_PCLK 146
> +#define SC_P_CSI_MCLK 147
> +#define SC_P_CSI_EN 148
> +#define SC_P_CSI_RESET 149
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150
> +#define SC_P_MIPI_CSI0_MCLK_OUT 151
> +#define SC_P_MIPI_CSI0_I2C0_SCL 152
> +#define SC_P_MIPI_CSI0_I2C0_SDA 153
> +#define SC_P_MIPI_CSI0_GPIO0_01 154
> +#define SC_P_MIPI_CSI0_GPIO0_00 155
> +#define SC_P_QSPI0A_DATA0 156
> +#define SC_P_QSPI0A_DATA1 157
> +#define SC_P_QSPI0A_DATA2 158
> +#define SC_P_QSPI0A_DATA3 159
> +#define SC_P_QSPI0A_DQS 160
> +#define SC_P_QSPI0A_SS0_B 161
> +#define SC_P_QSPI0A_SS1_B 162
> +#define SC_P_QSPI0A_SCLK 163
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164
> +#define SC_P_QSPI0B_SCLK 165
> +#define SC_P_QSPI0B_DATA0 166
> +#define SC_P_QSPI0B_DATA1 167
> +#define SC_P_QSPI0B_DATA2 168
> +#define SC_P_QSPI0B_DATA3 169
> +#define SC_P_QSPI0B_DQS 170
> +#define SC_P_QSPI0B_SS0_B 171
> +#define SC_P_QSPI0B_SS1_B 172
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173
> +
> +/*
> + * format: <pin_id mux_mode>
> + */
> +#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0
> +#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 SC_P_PCIE_CTRL0_PERST_B 4
> +#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B SC_P_PCIE_CTRL0_CLKREQ_B 0
> +#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 SC_P_PCIE_CTRL0_CLKREQ_B 4
> +#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B SC_P_PCIE_CTRL0_WAKE_B 0
> +#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 SC_P_PCIE_CTRL0_WAKE_B 4
> +#define SC_P_USB_SS3_TC0_ADMA_I2C1_SCL SC_P_USB_SS3_TC0 0
> +#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR SC_P_USB_SS3_TC0 1
> +#define SC_P_USB_SS3_TC0_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC0 2
> +#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 SC_P_USB_SS3_TC0 4
> +#define SC_P_USB_SS3_TC1_ADMA_I2C1_SCL SC_P_USB_SS3_TC1 0
> +#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC1 1
> +#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 SC_P_USB_SS3_TC1 4
> +#define SC_P_USB_SS3_TC2_ADMA_I2C1_SDA SC_P_USB_SS3_TC2 0
> +#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC SC_P_USB_SS3_TC2 1
> +#define SC_P_USB_SS3_TC2_CONN_USB_OTG2_OC SC_P_USB_SS3_TC2 2
> +#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 SC_P_USB_SS3_TC2 4
> +#define SC_P_USB_SS3_TC3_ADMA_I2C1_SDA SC_P_USB_SS3_TC3 0
> +#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC SC_P_USB_SS3_TC3 1
> +#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 SC_P_USB_SS3_TC3 4
> +#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK SC_P_EMMC0_CLK 0
> +#define SC_P_EMMC0_CLK_CONN_NAND_READY_B SC_P_EMMC0_CLK 1
> +#define SC_P_EMMC0_CLK_LSIO_GPIO4_IO07 SC_P_EMMC0_CLK 4
> +#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD SC_P_EMMC0_CMD 0
> +#define SC_P_EMMC0_CMD_CONN_NAND_DQS SC_P_EMMC0_CMD 1
> +#define SC_P_EMMC0_CMD_LSIO_GPIO4_IO08 SC_P_EMMC0_CMD 4
> +#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 SC_P_EMMC0_DATA0 0
> +#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 SC_P_EMMC0_DATA0 1
> +#define SC_P_EMMC0_DATA0_LSIO_GPIO4_IO09 SC_P_EMMC0_DATA0 4
> +#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 SC_P_EMMC0_DATA1 0
> +#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 SC_P_EMMC0_DATA1 1
> +#define SC_P_EMMC0_DATA1_LSIO_GPIO4_IO10 SC_P_EMMC0_DATA1 4
> +#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 SC_P_EMMC0_DATA2 0
> +#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 SC_P_EMMC0_DATA2 1
> +#define SC_P_EMMC0_DATA2_LSIO_GPIO4_IO11 SC_P_EMMC0_DATA2 4
> +#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 SC_P_EMMC0_DATA3 0
> +#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 SC_P_EMMC0_DATA3 1
> +#define SC_P_EMMC0_DATA3_LSIO_GPIO4_IO12 SC_P_EMMC0_DATA3 4
> +#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 SC_P_EMMC0_DATA4 0
> +#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 SC_P_EMMC0_DATA4 1
> +#define SC_P_EMMC0_DATA4_CONN_EMMC0_WP SC_P_EMMC0_DATA4 3
> +#define SC_P_EMMC0_DATA4_LSIO_GPIO4_IO13 SC_P_EMMC0_DATA4 4
> +#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 SC_P_EMMC0_DATA5 0
> +#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 SC_P_EMMC0_DATA5 1
> +#define SC_P_EMMC0_DATA5_CONN_EMMC0_VSELECT SC_P_EMMC0_DATA5 3
> +#define SC_P_EMMC0_DATA5_LSIO_GPIO4_IO14 SC_P_EMMC0_DATA5 4
> +#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 SC_P_EMMC0_DATA6 0
> +#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 SC_P_EMMC0_DATA6 1
> +#define SC_P_EMMC0_DATA6_CONN_MLB_CLK SC_P_EMMC0_DATA6 3
> +#define SC_P_EMMC0_DATA6_LSIO_GPIO4_IO15 SC_P_EMMC0_DATA6 4
> +#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 SC_P_EMMC0_DATA7 0
> +#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 SC_P_EMMC0_DATA7 1
> +#define SC_P_EMMC0_DATA7_CONN_MLB_SIG SC_P_EMMC0_DATA7 3
> +#define SC_P_EMMC0_DATA7_LSIO_GPIO4_IO16 SC_P_EMMC0_DATA7 4
> +#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE SC_P_EMMC0_STROBE 0
> +#define SC_P_EMMC0_STROBE_CONN_NAND_CLE SC_P_EMMC0_STROBE 1
> +#define SC_P_EMMC0_STROBE_CONN_MLB_DATA SC_P_EMMC0_STROBE 3
> +#define SC_P_EMMC0_STROBE_LSIO_GPIO4_IO17 SC_P_EMMC0_STROBE 4
> +#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B SC_P_EMMC0_RESET_B 0
> +#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B SC_P_EMMC0_RESET_B 1
> +#define SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18 SC_P_EMMC0_RESET_B 4
> +#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B SC_P_USDHC1_RESET_B 0
> +#define SC_P_USDHC1_RESET_B_CONN_NAND_RE_N SC_P_USDHC1_RESET_B 1
> +#define SC_P_USDHC1_RESET_B_ADMA_SPI2_SCK SC_P_USDHC1_RESET_B 2
> +#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 SC_P_USDHC1_RESET_B 4
> +#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT SC_P_USDHC1_VSELECT 0
> +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_P SC_P_USDHC1_VSELECT 1
> +#define SC_P_USDHC1_VSELECT_ADMA_SPI2_SDO SC_P_USDHC1_VSELECT 2
> +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_B SC_P_USDHC1_VSELECT 3
> +#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO20 SC_P_USDHC1_VSELECT 4
> +#define SC_P_USDHC1_WP_CONN_USDHC1_WP SC_P_USDHC1_WP 0
> +#define SC_P_USDHC1_WP_CONN_NAND_DQS_N SC_P_USDHC1_WP 1
> +#define SC_P_USDHC1_WP_ADMA_SPI2_SDI SC_P_USDHC1_WP 2
> +#define SC_P_USDHC1_WP_LSIO_GPIO4_IO21 SC_P_USDHC1_WP 4
> +#define SC_P_USDHC1_CD_B_CONN_USDHC1_CD_B SC_P_USDHC1_CD_B 0
> +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS_P SC_P_USDHC1_CD_B 1
> +#define SC_P_USDHC1_CD_B_ADMA_SPI2_CS0 SC_P_USDHC1_CD_B 2
> +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS SC_P_USDHC1_CD_B 3
> +#define SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 SC_P_USDHC1_CD_B 4
> +#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK SC_P_USDHC1_CLK 0
> +#define SC_P_USDHC1_CLK_ADMA_UART3_RX SC_P_USDHC1_CLK 2
> +#define SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 SC_P_USDHC1_CLK 4
> +#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD SC_P_USDHC1_CMD 0
> +#define SC_P_USDHC1_CMD_CONN_NAND_CE0_B SC_P_USDHC1_CMD 1
> +#define SC_P_USDHC1_CMD_ADMA_MQS_R SC_P_USDHC1_CMD 2
> +#define SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 SC_P_USDHC1_CMD 4
> +#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 SC_P_USDHC1_DATA0 0
> +#define SC_P_USDHC1_DATA0_CONN_NAND_CE1_B SC_P_USDHC1_DATA0 1
> +#define SC_P_USDHC1_DATA0_ADMA_MQS_L SC_P_USDHC1_DATA0 2
> +#define SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 SC_P_USDHC1_DATA0 4
> +#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 SC_P_USDHC1_DATA1 0
> +#define SC_P_USDHC1_DATA1_CONN_NAND_RE_B SC_P_USDHC1_DATA1 1
> +#define SC_P_USDHC1_DATA1_ADMA_UART3_TX SC_P_USDHC1_DATA1 2
> +#define SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 SC_P_USDHC1_DATA1 4
> +#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 SC_P_USDHC1_DATA2 0
> +#define SC_P_USDHC1_DATA2_CONN_NAND_WE_B SC_P_USDHC1_DATA2 1
> +#define SC_P_USDHC1_DATA2_ADMA_UART3_CTS_B SC_P_USDHC1_DATA2 2
> +#define SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 SC_P_USDHC1_DATA2 4
> +#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 SC_P_USDHC1_DATA3 0
> +#define SC_P_USDHC1_DATA3_CONN_NAND_ALE SC_P_USDHC1_DATA3 1
> +#define SC_P_USDHC1_DATA3_ADMA_UART3_RTS_B SC_P_USDHC1_DATA3 2
> +#define SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 SC_P_USDHC1_DATA3 4
> +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC SC_P_ENET0_RGMII_TXC 0
> +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT SC_P_ENET0_RGMII_TXC 1
> +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN SC_P_ENET0_RGMII_TXC 2
> +#define SC_P_ENET0_RGMII_TXC_CONN_NAND_CE1_B SC_P_ENET0_RGMII_TXC 3
> +#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 SC_P_ENET0_RGMII_TXC 4
> +#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL SC_P_ENET0_RGMII_TX_CTL 0
> +#define SC_P_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B SC_P_ENET0_RGMII_TX_CTL 3
> +#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 SC_P_ENET0_RGMII_TX_CTL 4
> +#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 SC_P_ENET0_RGMII_TXD0 0
> +#define SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT SC_P_ENET0_RGMII_TXD0 3
> +#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 SC_P_ENET0_RGMII_TXD0 4
> +#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 SC_P_ENET0_RGMII_TXD1 0
> +#define SC_P_ENET0_RGMII_TXD1_CONN_USDHC1_WP SC_P_ENET0_RGMII_TXD1 3
> +#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 SC_P_ENET0_RGMII_TXD1 4
> +#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 SC_P_ENET0_RGMII_TXD2 0
> +#define SC_P_ENET0_RGMII_TXD2_CONN_MLB_CLK SC_P_ENET0_RGMII_TXD2 1
> +#define SC_P_ENET0_RGMII_TXD2_CONN_NAND_CE0_B SC_P_ENET0_RGMII_TXD2 2
> +#define SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B SC_P_ENET0_RGMII_TXD2 3
> +#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 SC_P_ENET0_RGMII_TXD2 4
> +#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 SC_P_ENET0_RGMII_TXD3 0
> +#define SC_P_ENET0_RGMII_TXD3_CONN_MLB_SIG SC_P_ENET0_RGMII_TXD3 1
> +#define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B SC_P_ENET0_RGMII_TXD3 2
> +#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 SC_P_ENET0_RGMII_TXD3 4
> +#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0
> +#define SC_P_ENET0_RGMII_RXC_CONN_MLB_DATA SC_P_ENET0_RGMII_RXC 1
> +#define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B SC_P_ENET0_RGMII_RXC 2
> +#define SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK SC_P_ENET0_RGMII_RXC 3
> +#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 SC_P_ENET0_RGMII_RXC 4
> +#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL SC_P_ENET0_RGMII_RX_CTL 0
> +#define SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD SC_P_ENET0_RGMII_RX_CTL 3
> +#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 SC_P_ENET0_RGMII_RX_CTL 4
> +#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 SC_P_ENET0_RGMII_RXD0 0
> +#define SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 SC_P_ENET0_RGMII_RXD0 3
> +#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 SC_P_ENET0_RGMII_RXD0 4
> +#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 SC_P_ENET0_RGMII_RXD1 0
> +#define SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 SC_P_ENET0_RGMII_RXD1 3
> +#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 SC_P_ENET0_RGMII_RXD1 4
> +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 SC_P_ENET0_RGMII_RXD2 0
> +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER SC_P_ENET0_RGMII_RXD2 1
> +#define SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 SC_P_ENET0_RGMII_RXD2 3
> +#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 SC_P_ENET0_RGMII_RXD2 4
> +#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 SC_P_ENET0_RGMII_RXD3 0
> +#define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE SC_P_ENET0_RGMII_RXD3 2
> +#define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 SC_P_ENET0_RGMII_RXD3 3
> +#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 SC_P_ENET0_RGMII_RXD3 4
> +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0
> +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1
> +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET0_REFCLK_125M_25M 2
> +#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 SC_P_ENET0_REFCLK_125M_25M 4
> +#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO SC_P_ENET0_MDIO 0
> +#define SC_P_ENET0_MDIO_ADMA_I2C3_SDA SC_P_ENET0_MDIO 1
> +#define SC_P_ENET0_MDIO_CONN_ENET1_MDIO SC_P_ENET0_MDIO 2
> +#define SC_P_ENET0_MDIO_LSIO_GPIO5_IO10 SC_P_ENET0_MDIO 4
> +#define SC_P_ENET0_MDC_CONN_ENET0_MDC SC_P_ENET0_MDC 0
> +#define SC_P_ENET0_MDC_ADMA_I2C3_SCL SC_P_ENET0_MDC 1
> +#define SC_P_ENET0_MDC_CONN_ENET1_MDC SC_P_ENET0_MDC 2
> +#define SC_P_ENET0_MDC_LSIO_GPIO5_IO11 SC_P_ENET0_MDC 4
> +#define SC_P_ESAI0_FSR_ADMA_ESAI0_FSR SC_P_ESAI0_FSR 0
> +#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT SC_P_ESAI0_FSR 1
> +#define SC_P_ESAI0_FSR_ADMA_LCDIF_D00 SC_P_ESAI0_FSR 2
> +#define SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC SC_P_ESAI0_FSR 3
> +#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN SC_P_ESAI0_FSR 4
> +#define SC_P_ESAI0_FST_ADMA_ESAI0_FST SC_P_ESAI0_FST 0
> +#define SC_P_ESAI0_FST_CONN_MLB_CLK SC_P_ESAI0_FST 1
> +#define SC_P_ESAI0_FST_ADMA_LCDIF_D01 SC_P_ESAI0_FST 2
> +#define SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 SC_P_ESAI0_FST 3
> +#define SC_P_ESAI0_FST_LSIO_GPIO0_IO01 SC_P_ESAI0_FST 4
> +#define SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR SC_P_ESAI0_SCKR 0
> +#define SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 SC_P_ESAI0_SCKR 2
> +#define SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL SC_P_ESAI0_SCKR 3
> +#define SC_P_ESAI0_SCKR_LSIO_GPIO0_IO02 SC_P_ESAI0_SCKR 4
> +#define SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT SC_P_ESAI0_SCKT 0
> +#define SC_P_ESAI0_SCKT_CONN_MLB_SIG SC_P_ESAI0_SCKT 1
> +#define SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 SC_P_ESAI0_SCKT 2
> +#define SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 SC_P_ESAI0_SCKT 3
> +#define SC_P_ESAI0_SCKT_LSIO_GPIO0_IO03 SC_P_ESAI0_SCKT 4
> +#define SC_P_ESAI0_TX0_ADMA_ESAI0_TX0 SC_P_ESAI0_TX0 0
> +#define SC_P_ESAI0_TX0_CONN_MLB_DATA SC_P_ESAI0_TX0 1
> +#define SC_P_ESAI0_TX0_ADMA_LCDIF_D04 SC_P_ESAI0_TX0 2
> +#define SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC SC_P_ESAI0_TX0 3
> +#define SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 SC_P_ESAI0_TX0 4
> +#define SC_P_ESAI0_TX1_ADMA_ESAI0_TX1 SC_P_ESAI0_TX1 0
> +#define SC_P_ESAI0_TX1_ADMA_LCDIF_D05 SC_P_ESAI0_TX1 2
> +#define SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 SC_P_ESAI0_TX1 3
> +#define SC_P_ESAI0_TX1_LSIO_GPIO0_IO05 SC_P_ESAI0_TX1 4
> +#define SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 SC_P_ESAI0_TX2_RX3 0
> +#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER SC_P_ESAI0_TX2_RX3 1
> +#define SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 SC_P_ESAI0_TX2_RX3 2
> +#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 SC_P_ESAI0_TX2_RX3 3
> +#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 SC_P_ESAI0_TX2_RX3 4
> +#define SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 SC_P_ESAI0_TX3_RX2 0
> +#define SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 SC_P_ESAI0_TX3_RX2 2
> +#define SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 SC_P_ESAI0_TX3_RX2 3
> +#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 SC_P_ESAI0_TX3_RX2 4
> +#define SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 SC_P_ESAI0_TX4_RX1 0
> +#define SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 SC_P_ESAI0_TX4_RX1 2
> +#define SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 SC_P_ESAI0_TX4_RX1 3
> +#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO0_IO08 SC_P_ESAI0_TX4_RX1 4
> +#define SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 SC_P_ESAI0_TX5_RX0 0
> +#define SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 SC_P_ESAI0_TX5_RX0 2
> +#define SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 SC_P_ESAI0_TX5_RX0 3
> +#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO0_IO09 SC_P_ESAI0_TX5_RX0 4
> +#define SC_P_SPDIF0_RX_ADMA_SPDIF0_RX SC_P_SPDIF0_RX 0
> +#define SC_P_SPDIF0_RX_ADMA_MQS_R SC_P_SPDIF0_RX 1
> +#define SC_P_SPDIF0_RX_ADMA_LCDIF_D10 SC_P_SPDIF0_RX 2
> +#define SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 SC_P_SPDIF0_RX 3
> +#define SC_P_SPDIF0_RX_LSIO_GPIO0_IO10 SC_P_SPDIF0_RX 4
> +#define SC_P_SPDIF0_TX_ADMA_SPDIF0_TX SC_P_SPDIF0_TX 0
> +#define SC_P_SPDIF0_TX_ADMA_MQS_L SC_P_SPDIF0_TX 1
> +#define SC_P_SPDIF0_TX_ADMA_LCDIF_D11 SC_P_SPDIF0_TX 2
> +#define SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL SC_P_SPDIF0_TX 3
> +#define SC_P_SPDIF0_TX_LSIO_GPIO0_IO11 SC_P_SPDIF0_TX 4
> +#define SC_P_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK SC_P_SPDIF0_EXT_CLK 0
> +#define SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 SC_P_SPDIF0_EXT_CLK 2
> +#define SC_P_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M SC_P_SPDIF0_EXT_CLK 3
> +#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 SC_P_SPDIF0_EXT_CLK 4
> +#define SC_P_SPI3_SCK_ADMA_SPI3_SCK SC_P_SPI3_SCK 0
> +#define SC_P_SPI3_SCK_ADMA_LCDIF_D13 SC_P_SPI3_SCK 2
> +#define SC_P_SPI3_SCK_LSIO_GPIO0_IO13 SC_P_SPI3_SCK 4
> +#define SC_P_SPI3_SDO_ADMA_SPI3_SDO SC_P_SPI3_SDO 0
> +#define SC_P_SPI3_SDO_ADMA_LCDIF_D14 SC_P_SPI3_SDO 2
> +#define SC_P_SPI3_SDO_LSIO_GPIO0_IO14 SC_P_SPI3_SDO 4
> +#define SC_P_SPI3_SDI_ADMA_SPI3_SDI SC_P_SPI3_SDI 0
> +#define SC_P_SPI3_SDI_ADMA_LCDIF_D15 SC_P_SPI3_SDI 2
> +#define SC_P_SPI3_SDI_LSIO_GPIO0_IO15 SC_P_SPI3_SDI 4
> +#define SC_P_SPI3_CS0_ADMA_SPI3_CS0 SC_P_SPI3_CS0 0
> +#define SC_P_SPI3_CS0_ADMA_ACM_MCLK_OUT1 SC_P_SPI3_CS0 1
> +#define SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC SC_P_SPI3_CS0 2
> +#define SC_P_SPI3_CS0_LSIO_GPIO0_IO16 SC_P_SPI3_CS0 4
> +#define SC_P_SPI3_CS1_ADMA_SPI3_CS1 SC_P_SPI3_CS1 0
> +#define SC_P_SPI3_CS1_ADMA_I2C3_SCL SC_P_SPI3_CS1 1
> +#define SC_P_SPI3_CS1_ADMA_LCDIF_RESET SC_P_SPI3_CS1 2
> +#define SC_P_SPI3_CS1_ADMA_SPI2_CS0 SC_P_SPI3_CS1 3
> +#define SC_P_SPI3_CS1_ADMA_LCDIF_D16 SC_P_SPI3_CS1 4
> +#define SC_P_MCLK_IN1_ADMA_ACM_MCLK_IN1 SC_P_MCLK_IN1 0
> +#define SC_P_MCLK_IN1_ADMA_I2C3_SDA SC_P_MCLK_IN1 1
> +#define SC_P_MCLK_IN1_ADMA_LCDIF_EN SC_P_MCLK_IN1 2
> +#define SC_P_MCLK_IN1_ADMA_SPI2_SCK SC_P_MCLK_IN1 3
> +#define SC_P_MCLK_IN1_ADMA_LCDIF_D17 SC_P_MCLK_IN1 4
> +#define SC_P_MCLK_IN0_ADMA_ACM_MCLK_IN0 SC_P_MCLK_IN0 0
> +#define SC_P_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK SC_P_MCLK_IN0 1
> +#define SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC SC_P_MCLK_IN0 2
> +#define SC_P_MCLK_IN0_ADMA_SPI2_SDI SC_P_MCLK_IN0 3
> +#define SC_P_MCLK_IN0_LSIO_GPIO0_IO19 SC_P_MCLK_IN0 4
> +#define SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 SC_P_MCLK_OUT0 0
> +#define SC_P_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK SC_P_MCLK_OUT0 1
> +#define SC_P_MCLK_OUT0_ADMA_LCDIF_CLK SC_P_MCLK_OUT0 2
> +#define SC_P_MCLK_OUT0_ADMA_SPI2_SDO SC_P_MCLK_OUT0 3
> +#define SC_P_MCLK_OUT0_LSIO_GPIO0_IO20 SC_P_MCLK_OUT0 4
> +#define SC_P_UART1_TX_ADMA_UART1_TX SC_P_UART1_TX 0
> +#define SC_P_UART1_TX_LSIO_PWM0_OUT SC_P_UART1_TX 1
> +#define SC_P_UART1_TX_LSIO_GPT0_CAPTURE SC_P_UART1_TX 2
> +#define SC_P_UART1_TX_LSIO_GPIO0_IO21 SC_P_UART1_TX 4
> +#define SC_P_UART1_RX_ADMA_UART1_RX SC_P_UART1_RX 0
> +#define SC_P_UART1_RX_LSIO_PWM1_OUT SC_P_UART1_RX 1
> +#define SC_P_UART1_RX_LSIO_GPT0_COMPARE SC_P_UART1_RX 2
> +#define SC_P_UART1_RX_LSIO_GPT1_CLK SC_P_UART1_RX 3
> +#define SC_P_UART1_RX_LSIO_GPIO0_IO22 SC_P_UART1_RX 4
> +#define SC_P_UART1_RTS_B_ADMA_UART1_RTS_B SC_P_UART1_RTS_B 0
> +#define SC_P_UART1_RTS_B_LSIO_PWM2_OUT SC_P_UART1_RTS_B 1
> +#define SC_P_UART1_RTS_B_ADMA_LCDIF_D16 SC_P_UART1_RTS_B 2
> +#define SC_P_UART1_RTS_B_LSIO_GPT1_CAPTURE SC_P_UART1_RTS_B 3
> +#define SC_P_UART1_RTS_B_LSIO_GPT0_CLK SC_P_UART1_RTS_B 4
> +#define SC_P_UART1_CTS_B_ADMA_UART1_CTS_B SC_P_UART1_CTS_B 0
> +#define SC_P_UART1_CTS_B_LSIO_PWM3_OUT SC_P_UART1_CTS_B 1
> +#define SC_P_UART1_CTS_B_ADMA_LCDIF_D17 SC_P_UART1_CTS_B 2
> +#define SC_P_UART1_CTS_B_LSIO_GPT1_COMPARE SC_P_UART1_CTS_B 3
> +#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO24 SC_P_UART1_CTS_B 4
> +#define SC_P_SAI0_TXD_ADMA_SAI0_TXD SC_P_SAI0_TXD 0
> +#define SC_P_SAI0_TXD_ADMA_SAI1_RXC SC_P_SAI0_TXD 1
> +#define SC_P_SAI0_TXD_ADMA_SPI1_SDO SC_P_SAI0_TXD 2
> +#define SC_P_SAI0_TXD_ADMA_LCDIF_D18 SC_P_SAI0_TXD 3
> +#define SC_P_SAI0_TXD_LSIO_GPIO0_IO25 SC_P_SAI0_TXD 4
> +#define SC_P_SAI0_TXC_ADMA_SAI0_TXC SC_P_SAI0_TXC 0
> +#define SC_P_SAI0_TXC_ADMA_SAI1_TXD SC_P_SAI0_TXC 1
> +#define SC_P_SAI0_TXC_ADMA_SPI1_SDI SC_P_SAI0_TXC 2
> +#define SC_P_SAI0_TXC_ADMA_LCDIF_D19 SC_P_SAI0_TXC 3
> +#define SC_P_SAI0_TXC_LSIO_GPIO0_IO26 SC_P_SAI0_TXC 4
> +#define SC_P_SAI0_RXD_ADMA_SAI0_RXD SC_P_SAI0_RXD 0
> +#define SC_P_SAI0_RXD_ADMA_SAI1_RXFS SC_P_SAI0_RXD 1
> +#define SC_P_SAI0_RXD_ADMA_SPI1_CS0 SC_P_SAI0_RXD 2
> +#define SC_P_SAI0_RXD_ADMA_LCDIF_D20 SC_P_SAI0_RXD 3
> +#define SC_P_SAI0_RXD_LSIO_GPIO0_IO27 SC_P_SAI0_RXD 4
> +#define SC_P_SAI0_TXFS_ADMA_SAI0_TXFS SC_P_SAI0_TXFS 0
> +#define SC_P_SAI0_TXFS_ADMA_SPI2_CS1 SC_P_SAI0_TXFS 1
> +#define SC_P_SAI0_TXFS_ADMA_SPI1_SCK SC_P_SAI0_TXFS 2
> +#define SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 SC_P_SAI0_TXFS 4
> +#define SC_P_SAI1_RXD_ADMA_SAI1_RXD SC_P_SAI1_RXD 0
> +#define SC_P_SAI1_RXD_ADMA_SAI0_RXFS SC_P_SAI1_RXD 1
> +#define SC_P_SAI1_RXD_ADMA_SPI1_CS1 SC_P_SAI1_RXD 2
> +#define SC_P_SAI1_RXD_ADMA_LCDIF_D21 SC_P_SAI1_RXD 3
> +#define SC_P_SAI1_RXD_LSIO_GPIO0_IO29 SC_P_SAI1_RXD 4
> +#define SC_P_SAI1_RXC_ADMA_SAI1_RXC SC_P_SAI1_RXC 0
> +#define SC_P_SAI1_RXC_ADMA_SAI1_TXC SC_P_SAI1_RXC 1
> +#define SC_P_SAI1_RXC_ADMA_LCDIF_D22 SC_P_SAI1_RXC 3
> +#define SC_P_SAI1_RXC_LSIO_GPIO0_IO30 SC_P_SAI1_RXC 4
> +#define SC_P_SAI1_RXFS_ADMA_SAI1_RXFS SC_P_SAI1_RXFS 0
> +#define SC_P_SAI1_RXFS_ADMA_SAI1_TXFS SC_P_SAI1_RXFS 1
> +#define SC_P_SAI1_RXFS_ADMA_LCDIF_D23 SC_P_SAI1_RXFS 3
> +#define SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 SC_P_SAI1_RXFS 4
> +#define SC_P_SPI2_CS0_ADMA_SPI2_CS0 SC_P_SPI2_CS0 0
> +#define SC_P_SPI2_CS0_LSIO_GPIO1_IO00 SC_P_SPI2_CS0 4
> +#define SC_P_SPI2_SDO_ADMA_SPI2_SDO SC_P_SPI2_SDO 0
> +#define SC_P_SPI2_SDO_LSIO_GPIO1_IO01 SC_P_SPI2_SDO 4
> +#define SC_P_SPI2_SDI_ADMA_SPI2_SDI SC_P_SPI2_SDI 0
> +#define SC_P_SPI2_SDI_LSIO_GPIO1_IO02 SC_P_SPI2_SDI 4
> +#define SC_P_SPI2_SCK_ADMA_SPI2_SCK SC_P_SPI2_SCK 0
> +#define SC_P_SPI2_SCK_LSIO_GPIO1_IO03 SC_P_SPI2_SCK 4
> +#define SC_P_SPI0_SCK_ADMA_SPI0_SCK SC_P_SPI0_SCK 0
> +#define SC_P_SPI0_SCK_ADMA_SAI0_TXC SC_P_SPI0_SCK 1
> +#define SC_P_SPI0_SCK_M40_I2C0_SCL SC_P_SPI0_SCK 2
> +#define SC_P_SPI0_SCK_M40_GPIO0_IO00 SC_P_SPI0_SCK 3
> +#define SC_P_SPI0_SCK_LSIO_GPIO1_IO04 SC_P_SPI0_SCK 4
> +#define SC_P_SPI0_SDI_ADMA_SPI0_SDI SC_P_SPI0_SDI 0
> +#define SC_P_SPI0_SDI_ADMA_SAI0_TXD SC_P_SPI0_SDI 1
> +#define SC_P_SPI0_SDI_M40_TPM0_CH0 SC_P_SPI0_SDI 2
> +#define SC_P_SPI0_SDI_M40_GPIO0_IO02 SC_P_SPI0_SDI 3
> +#define SC_P_SPI0_SDI_LSIO_GPIO1_IO05 SC_P_SPI0_SDI 4
> +#define SC_P_SPI0_SDO_ADMA_SPI0_SDO SC_P_SPI0_SDO 0
> +#define SC_P_SPI0_SDO_ADMA_SAI0_TXFS SC_P_SPI0_SDO 1
> +#define SC_P_SPI0_SDO_M40_I2C0_SDA SC_P_SPI0_SDO 2
> +#define SC_P_SPI0_SDO_M40_GPIO0_IO01 SC_P_SPI0_SDO 3
> +#define SC_P_SPI0_SDO_LSIO_GPIO1_IO06 SC_P_SPI0_SDO 4
> +#define SC_P_SPI0_CS1_ADMA_SPI0_CS1 SC_P_SPI0_CS1 0
> +#define SC_P_SPI0_CS1_ADMA_SAI0_RXC SC_P_SPI0_CS1 1
> +#define SC_P_SPI0_CS1_ADMA_SAI1_TXD SC_P_SPI0_CS1 2
> +#define SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT SC_P_SPI0_CS1 3
> +#define SC_P_SPI0_CS1_LSIO_GPIO1_IO07 SC_P_SPI0_CS1 4
> +#define SC_P_SPI0_CS0_ADMA_SPI0_CS0 SC_P_SPI0_CS0 0
> +#define SC_P_SPI0_CS0_ADMA_SAI0_RXD SC_P_SPI0_CS0 1
> +#define SC_P_SPI0_CS0_M40_TPM0_CH1 SC_P_SPI0_CS0 2
> +#define SC_P_SPI0_CS0_M40_GPIO0_IO03 SC_P_SPI0_CS0 3
> +#define SC_P_SPI0_CS0_LSIO_GPIO1_IO08 SC_P_SPI0_CS0 4
> +#define SC_P_ADC_IN1_ADMA_ADC_IN1 SC_P_ADC_IN1 0
> +#define SC_P_ADC_IN1_M40_I2C0_SDA SC_P_ADC_IN1 1
> +#define SC_P_ADC_IN1_M40_GPIO0_IO01 SC_P_ADC_IN1 2
> +#define SC_P_ADC_IN1_LSIO_GPIO1_IO09 SC_P_ADC_IN1 4
> +#define SC_P_ADC_IN0_ADMA_ADC_IN0 SC_P_ADC_IN0 0
> +#define SC_P_ADC_IN0_M40_I2C0_SCL SC_P_ADC_IN0 1
> +#define SC_P_ADC_IN0_M40_GPIO0_IO00 SC_P_ADC_IN0 2
> +#define SC_P_ADC_IN0_LSIO_GPIO1_IO10 SC_P_ADC_IN0 4
> +#define SC_P_ADC_IN3_ADMA_ADC_IN3 SC_P_ADC_IN3 0
> +#define SC_P_ADC_IN3_M40_UART0_TX SC_P_ADC_IN3 1
> +#define SC_P_ADC_IN3_M40_GPIO0_IO03 SC_P_ADC_IN3 2
> +#define SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0 SC_P_ADC_IN3 3
> +#define SC_P_ADC_IN3_LSIO_GPIO1_IO11 SC_P_ADC_IN3 4
> +#define SC_P_ADC_IN2_ADMA_ADC_IN2 SC_P_ADC_IN2 0
> +#define SC_P_ADC_IN2_M40_UART0_RX SC_P_ADC_IN2 1
> +#define SC_P_ADC_IN2_M40_GPIO0_IO02 SC_P_ADC_IN2 2
> +#define SC_P_ADC_IN2_ADMA_ACM_MCLK_IN0 SC_P_ADC_IN2 3
> +#define SC_P_ADC_IN2_LSIO_GPIO1_IO12 SC_P_ADC_IN2 4
> +#define SC_P_ADC_IN5_ADMA_ADC_IN5 SC_P_ADC_IN5 0
> +#define SC_P_ADC_IN5_M40_TPM0_CH1 SC_P_ADC_IN5 1
> +#define SC_P_ADC_IN5_M40_GPIO0_IO05 SC_P_ADC_IN5 2
> +#define SC_P_ADC_IN5_LSIO_GPIO1_IO13 SC_P_ADC_IN5 4
> +#define SC_P_ADC_IN4_ADMA_ADC_IN4 SC_P_ADC_IN4 0
> +#define SC_P_ADC_IN4_M40_TPM0_CH0 SC_P_ADC_IN4 1
> +#define SC_P_ADC_IN4_M40_GPIO0_IO04 SC_P_ADC_IN4 2
> +#define SC_P_ADC_IN4_LSIO_GPIO1_IO14 SC_P_ADC_IN4 4
> +#define SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX SC_P_FLEXCAN0_RX 0
> +#define SC_P_FLEXCAN0_RX_ADMA_SAI2_RXC SC_P_FLEXCAN0_RX 1
> +#define SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B SC_P_FLEXCAN0_RX 2
> +#define SC_P_FLEXCAN0_RX_ADMA_SAI1_TXC SC_P_FLEXCAN0_RX 3
> +#define SC_P_FLEXCAN0_RX_LSIO_GPIO1_IO15 SC_P_FLEXCAN0_RX 4
> +#define SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX SC_P_FLEXCAN0_TX 0
> +#define SC_P_FLEXCAN0_TX_ADMA_SAI2_RXD SC_P_FLEXCAN0_TX 1
> +#define SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B SC_P_FLEXCAN0_TX 2
> +#define SC_P_FLEXCAN0_TX_ADMA_SAI1_TXFS SC_P_FLEXCAN0_TX 3
> +#define SC_P_FLEXCAN0_TX_LSIO_GPIO1_IO16 SC_P_FLEXCAN0_TX 4
> +#define SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX SC_P_FLEXCAN1_RX 0
> +#define SC_P_FLEXCAN1_RX_ADMA_SAI2_RXFS SC_P_FLEXCAN1_RX 1
> +#define SC_P_FLEXCAN1_RX_ADMA_FTM_CH2 SC_P_FLEXCAN1_RX 2
> +#define SC_P_FLEXCAN1_RX_ADMA_SAI1_TXD SC_P_FLEXCAN1_RX 3
> +#define SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 SC_P_FLEXCAN1_RX 4
> +#define SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX SC_P_FLEXCAN1_TX 0
> +#define SC_P_FLEXCAN1_TX_ADMA_SAI3_RXC SC_P_FLEXCAN1_TX 1
> +#define SC_P_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 SC_P_FLEXCAN1_TX 2
> +#define SC_P_FLEXCAN1_TX_ADMA_SAI1_RXD SC_P_FLEXCAN1_TX 3
> +#define SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 SC_P_FLEXCAN1_TX 4
> +#define SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX SC_P_FLEXCAN2_RX 0
> +#define SC_P_FLEXCAN2_RX_ADMA_SAI3_RXD SC_P_FLEXCAN2_RX 1
> +#define SC_P_FLEXCAN2_RX_ADMA_UART3_RX SC_P_FLEXCAN2_RX 2
> +#define SC_P_FLEXCAN2_RX_ADMA_SAI1_RXFS SC_P_FLEXCAN2_RX 3
> +#define SC_P_FLEXCAN2_RX_LSIO_GPIO1_IO19 SC_P_FLEXCAN2_RX 4
> +#define SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX SC_P_FLEXCAN2_TX 0
> +#define SC_P_FLEXCAN2_TX_ADMA_SAI3_RXFS SC_P_FLEXCAN2_TX 1
> +#define SC_P_FLEXCAN2_TX_ADMA_UART3_TX SC_P_FLEXCAN2_TX 2
> +#define SC_P_FLEXCAN2_TX_ADMA_SAI1_RXC SC_P_FLEXCAN2_TX 3
> +#define SC_P_FLEXCAN2_TX_LSIO_GPIO1_IO20 SC_P_FLEXCAN2_TX 4
> +#define SC_P_UART0_RX_ADMA_UART0_RX SC_P_UART0_RX 0
> +#define SC_P_UART0_RX_ADMA_MQS_R SC_P_UART0_RX 1
> +#define SC_P_UART0_RX_ADMA_FLEXCAN0_RX SC_P_UART0_RX 2
> +#define SC_P_UART0_RX_LSIO_GPIO1_IO21 SC_P_UART0_RX 4
> +#define SC_P_UART0_TX_ADMA_UART0_TX SC_P_UART0_TX 0
> +#define SC_P_UART0_TX_ADMA_MQS_L SC_P_UART0_TX 1
> +#define SC_P_UART0_TX_ADMA_FLEXCAN0_TX SC_P_UART0_TX 2
> +#define SC_P_UART0_TX_LSIO_GPIO1_IO22 SC_P_UART0_TX 4
> +#define SC_P_UART2_TX_ADMA_UART2_TX SC_P_UART2_TX 0
> +#define SC_P_UART2_TX_ADMA_FTM_CH1 SC_P_UART2_TX 1
> +#define SC_P_UART2_TX_ADMA_FLEXCAN1_TX SC_P_UART2_TX 2
> +#define SC_P_UART2_TX_LSIO_GPIO1_IO23 SC_P_UART2_TX 4
> +#define SC_P_UART2_RX_ADMA_UART2_RX SC_P_UART2_RX 0
> +#define SC_P_UART2_RX_ADMA_FTM_CH0 SC_P_UART2_RX 1
> +#define SC_P_UART2_RX_ADMA_FLEXCAN1_RX SC_P_UART2_RX 2
> +#define SC_P_UART2_RX_LSIO_GPIO1_IO24 SC_P_UART2_RX 4
> +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL SC_P_MIPI_DSI0_I2C0_SCL 0
> +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02 SC_P_MIPI_DSI0_I2C0_SCL 1
> +#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 SC_P_MIPI_DSI0_I2C0_SCL 4
> +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA SC_P_MIPI_DSI0_I2C0_SDA 0
> +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03 SC_P_MIPI_DSI0_I2C0_SDA 1
> +#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 SC_P_MIPI_DSI0_I2C0_SDA 4
> +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 SC_P_MIPI_DSI0_GPIO0_00 0
> +#define SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL SC_P_MIPI_DSI0_GPIO0_00 1
> +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT SC_P_MIPI_DSI0_GPIO0_00 2
> +#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 SC_P_MIPI_DSI0_GPIO0_00 4
> +#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 SC_P_MIPI_DSI0_GPIO0_01 0
> +#define SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA SC_P_MIPI_DSI0_GPIO0_01 1
> +#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 SC_P_MIPI_DSI0_GPIO0_01 4
> +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL SC_P_MIPI_DSI1_I2C0_SCL 0
> +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02 SC_P_MIPI_DSI1_I2C0_SCL 1
> +#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29 SC_P_MIPI_DSI1_I2C0_SCL 4
> +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA SC_P_MIPI_DSI1_I2C0_SDA 0
> +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03 SC_P_MIPI_DSI1_I2C0_SDA 1
> +#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 SC_P_MIPI_DSI1_I2C0_SDA 4
> +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 SC_P_MIPI_DSI1_GPIO0_00 0
> +#define SC_P_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL SC_P_MIPI_DSI1_GPIO0_00 1
> +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT SC_P_MIPI_DSI1_GPIO0_00 2
> +#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 SC_P_MIPI_DSI1_GPIO0_00 4
> +#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 SC_P_MIPI_DSI1_GPIO0_01 0
> +#define SC_P_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA SC_P_MIPI_DSI1_GPIO0_01 1
> +#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 SC_P_MIPI_DSI1_GPIO0_01 4
> +#define SC_P_JTAG_TRST_B_SCU_JTAG_TRST_B SC_P_JTAG_TRST_B 0
> +#define SC_P_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT SC_P_JTAG_TRST_B 1
> +#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL SC_P_PMIC_I2C_SCL 0
> +#define SC_P_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON SC_P_PMIC_I2C_SCL 1
> +#define SC_P_PMIC_I2C_SCL_LSIO_GPIO2_IO01 SC_P_PMIC_I2C_SCL 4
> +#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA SC_P_PMIC_I2C_SDA 0
> +#define SC_P_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON SC_P_PMIC_I2C_SDA 1
> +#define SC_P_PMIC_I2C_SDA_LSIO_GPIO2_IO02 SC_P_PMIC_I2C_SDA 4
> +#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B SC_P_PMIC_INT_B 0
> +#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 SC_P_SCU_GPIO0_00 0
> +#define SC_P_SCU_GPIO0_00_SCU_UART0_RX SC_P_SCU_GPIO0_00 1
> +#define SC_P_SCU_GPIO0_00_M40_UART0_RX SC_P_SCU_GPIO0_00 2
> +#define SC_P_SCU_GPIO0_00_ADMA_UART3_RX SC_P_SCU_GPIO0_00 3
> +#define SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03 SC_P_SCU_GPIO0_00 4
> +#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 SC_P_SCU_GPIO0_01 0
> +#define SC_P_SCU_GPIO0_01_SCU_UART0_TX SC_P_SCU_GPIO0_01 1
> +#define SC_P_SCU_GPIO0_01_M40_UART0_TX SC_P_SCU_GPIO0_01 2
> +#define SC_P_SCU_GPIO0_01_ADMA_UART3_TX SC_P_SCU_GPIO0_01 3
> +#define SC_P_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT SC_P_SCU_GPIO0_01 4
> +#define SC_P_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY SC_P_SCU_PMIC_STANDBY 0
> +#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 SC_P_SCU_BOOT_MODE0 0
> +#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 SC_P_SCU_BOOT_MODE1 0
> +#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 SC_P_SCU_BOOT_MODE2 0
> +#define SC_P_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA SC_P_SCU_BOOT_MODE2 1
> +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 SC_P_SCU_BOOT_MODE3 0
> +#define SC_P_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL SC_P_SCU_BOOT_MODE3 1
> +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K SC_P_SCU_BOOT_MODE3 3
> +#define SC_P_CSI_D00_CI_PI_D02 SC_P_CSI_D00 0
> +#define SC_P_CSI_D00_ADMA_SAI0_RXC SC_P_CSI_D00 2
> +#define SC_P_CSI_D01_CI_PI_D03 SC_P_CSI_D01 0
> +#define SC_P_CSI_D01_ADMA_SAI0_RXD SC_P_CSI_D01 2
> +#define SC_P_CSI_D02_CI_PI_D04 SC_P_CSI_D02 0
> +#define SC_P_CSI_D02_ADMA_SAI0_RXFS SC_P_CSI_D02 2
> +#define SC_P_CSI_D03_CI_PI_D05 SC_P_CSI_D03 0
> +#define SC_P_CSI_D03_ADMA_SAI2_RXC SC_P_CSI_D03 2
> +#define SC_P_CSI_D04_CI_PI_D06 SC_P_CSI_D04 0
> +#define SC_P_CSI_D04_ADMA_SAI2_RXD SC_P_CSI_D04 2
> +#define SC_P_CSI_D05_CI_PI_D07 SC_P_CSI_D05 0
> +#define SC_P_CSI_D05_ADMA_SAI2_RXFS SC_P_CSI_D05 2
> +#define SC_P_CSI_D06_CI_PI_D08 SC_P_CSI_D06 0
> +#define SC_P_CSI_D06_ADMA_SAI3_RXC SC_P_CSI_D06 2
> +#define SC_P_CSI_D07_CI_PI_D09 SC_P_CSI_D07 0
> +#define SC_P_CSI_D07_ADMA_SAI3_RXD SC_P_CSI_D07 2
> +#define SC_P_CSI_HSYNC_CI_PI_HSYNC SC_P_CSI_HSYNC 0
> +#define SC_P_CSI_HSYNC_CI_PI_D00 SC_P_CSI_HSYNC 1
> +#define SC_P_CSI_HSYNC_ADMA_SAI3_RXFS SC_P_CSI_HSYNC 2
> +#define SC_P_CSI_VSYNC_CI_PI_VSYNC SC_P_CSI_VSYNC 0
> +#define SC_P_CSI_VSYNC_CI_PI_D01 SC_P_CSI_VSYNC 1
> +#define SC_P_CSI_PCLK_CI_PI_PCLK SC_P_CSI_PCLK 0
> +#define SC_P_CSI_PCLK_MIPI_CSI0_I2C0_SCL SC_P_CSI_PCLK 1
> +#define SC_P_CSI_PCLK_ADMA_SPI1_SCK SC_P_CSI_PCLK 3
> +#define SC_P_CSI_PCLK_LSIO_GPIO3_IO00 SC_P_CSI_PCLK 4
> +#define SC_P_CSI_MCLK_CI_PI_MCLK SC_P_CSI_MCLK 0
> +#define SC_P_CSI_MCLK_MIPI_CSI0_I2C0_SDA SC_P_CSI_MCLK 1
> +#define SC_P_CSI_MCLK_ADMA_SPI1_SDO SC_P_CSI_MCLK 3
> +#define SC_P_CSI_MCLK_LSIO_GPIO3_IO01 SC_P_CSI_MCLK 4
> +#define SC_P_CSI_EN_CI_PI_EN SC_P_CSI_EN 0
> +#define SC_P_CSI_EN_CI_PI_I2C_SCL SC_P_CSI_EN 1
> +#define SC_P_CSI_EN_ADMA_I2C3_SCL SC_P_CSI_EN 2
> +#define SC_P_CSI_EN_ADMA_SPI1_SDI SC_P_CSI_EN 3
> +#define SC_P_CSI_EN_LSIO_GPIO3_IO02 SC_P_CSI_EN 4
> +#define SC_P_CSI_RESET_CI_PI_RESET SC_P_CSI_RESET 0
> +#define SC_P_CSI_RESET_CI_PI_I2C_SDA SC_P_CSI_RESET 1
> +#define SC_P_CSI_RESET_ADMA_I2C3_SDA SC_P_CSI_RESET 2
> +#define SC_P_CSI_RESET_ADMA_SPI1_CS0 SC_P_CSI_RESET 3
> +#define SC_P_CSI_RESET_LSIO_GPIO3_IO03 SC_P_CSI_RESET 4
> +#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT SC_P_MIPI_CSI0_MCLK_OUT 0
> +#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 SC_P_MIPI_CSI0_MCLK_OUT 4
> +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL SC_P_MIPI_CSI0_I2C0_SCL 0
> +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02 SC_P_MIPI_CSI0_I2C0_SCL 1
> +#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 SC_P_MIPI_CSI0_I2C0_SCL 4
> +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA SC_P_MIPI_CSI0_I2C0_SDA 0
> +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03 SC_P_MIPI_CSI0_I2C0_SDA 1
> +#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 SC_P_MIPI_CSI0_I2C0_SDA 4
> +#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 SC_P_MIPI_CSI0_GPIO0_01 0
> +#define SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 1
> +#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 SC_P_MIPI_CSI0_GPIO0_01 4
> +#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 SC_P_MIPI_CSI0_GPIO0_00 0
> +#define SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 1
> +#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 SC_P_MIPI_CSI0_GPIO0_00 4
> +#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 SC_P_QSPI0A_DATA0 0
> +#define SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 SC_P_QSPI0A_DATA0 4
> +#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 SC_P_QSPI0A_DATA1 0
> +#define SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 SC_P_QSPI0A_DATA1 4
> +#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 SC_P_QSPI0A_DATA2 0
> +#define SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 SC_P_QSPI0A_DATA2 4
> +#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 SC_P_QSPI0A_DATA3 0
> +#define SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 SC_P_QSPI0A_DATA3 4
> +#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS SC_P_QSPI0A_DQS 0
> +#define SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 SC_P_QSPI0A_DQS 4
> +#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B SC_P_QSPI0A_SS0_B 0
> +#define SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 SC_P_QSPI0A_SS0_B 4
> +#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B SC_P_QSPI0A_SS1_B 0
> +#define SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 SC_P_QSPI0A_SS1_B 4
> +#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK SC_P_QSPI0A_SCLK 0
> +#define SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 SC_P_QSPI0A_SCLK 4
> +#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK SC_P_QSPI0B_SCLK 0
> +#define SC_P_QSPI0B_SCLK_LSIO_QSPI1A_SCLK SC_P_QSPI0B_SCLK 1
> +#define SC_P_QSPI0B_SCLK_LSIO_KPP0_COL0 SC_P_QSPI0B_SCLK 2
> +#define SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 SC_P_QSPI0B_SCLK 4
> +#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 SC_P_QSPI0B_DATA0 0
> +#define SC_P_QSPI0B_DATA0_LSIO_QSPI1A_DATA0 SC_P_QSPI0B_DATA0 1
> +#define SC_P_QSPI0B_DATA0_LSIO_KPP0_COL1 SC_P_QSPI0B_DATA0 2
> +#define SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 SC_P_QSPI0B_DATA0 4
> +#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 SC_P_QSPI0B_DATA1 0
> +#define SC_P_QSPI0B_DATA1_LSIO_QSPI1A_DATA1 SC_P_QSPI0B_DATA1 1
> +#define SC_P_QSPI0B_DATA1_LSIO_KPP0_COL2 SC_P_QSPI0B_DATA1 2
> +#define SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 SC_P_QSPI0B_DATA1 4
> +#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 SC_P_QSPI0B_DATA2 0
> +#define SC_P_QSPI0B_DATA2_LSIO_QSPI1A_DATA2 SC_P_QSPI0B_DATA2 1
> +#define SC_P_QSPI0B_DATA2_LSIO_KPP0_COL3 SC_P_QSPI0B_DATA2 2
> +#define SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 SC_P_QSPI0B_DATA2 4
> +#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 SC_P_QSPI0B_DATA3 0
> +#define SC_P_QSPI0B_DATA3_LSIO_QSPI1A_DATA3 SC_P_QSPI0B_DATA3 1
> +#define SC_P_QSPI0B_DATA3_LSIO_KPP0_ROW0 SC_P_QSPI0B_DATA3 2
> +#define SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 SC_P_QSPI0B_DATA3 4
> +#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS SC_P_QSPI0B_DQS 0
> +#define SC_P_QSPI0B_DQS_LSIO_QSPI1A_DQS SC_P_QSPI0B_DQS 1
> +#define SC_P_QSPI0B_DQS_LSIO_KPP0_ROW1 SC_P_QSPI0B_DQS 2
> +#define SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 SC_P_QSPI0B_DQS 4
> +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B SC_P_QSPI0B_SS0_B 0
> +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B SC_P_QSPI0B_SS0_B 1
> +#define SC_P_QSPI0B_SS0_B_LSIO_KPP0_ROW2 SC_P_QSPI0B_SS0_B 2
> +#define SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 SC_P_QSPI0B_SS0_B 4
> +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B SC_P_QSPI0B_SS1_B 0
> +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B SC_P_QSPI0B_SS1_B 1
> +#define SC_P_QSPI0B_SS1_B_LSIO_KPP0_ROW3 SC_P_QSPI0B_SS1_B 2
> +#define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 SC_P_QSPI0B_SS1_B 4
> +
> +#endif /* _SC_PADS_H */
> --
> 2.7.4
>
> --
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^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 5/6] dt-bindings: pinctrl: add imx8qxp pinctrl binding doc
@ 2018-05-01 15:58 ` Rob Herring
0 siblings, 0 replies; 36+ messages in thread
From: Rob Herring @ 2018-05-01 15:58 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Apr 28, 2018 at 03:01:52AM +0800, Dong Aisheng wrote:
> Add imx8qxp pinctrl binding doc.
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: devicetree at vger.kernel.org
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> Note: there's a checkpatch error as follows:
> ERROR: Macros with complex values should be enclosed in parentheses
> +#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0
>
> However, this is the intended format. Seems checkpatch did not recognize
> it well. Not sure if we could accept it.
> ---
> .../bindings/pinctrl/fsl,imx8qxp-pinctrl.txt | 39 ++
> include/dt-bindings/pinctrl/pads-imx8qxp.h | 751 +++++++++++++++++++++
> 2 files changed, 790 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt
> create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt
> new file mode 100644
> index 0000000..62c0f55
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt
> @@ -0,0 +1,39 @@
> +* NXP i.MX8QXP IOMUX Controller
> +
> +MX8QXP contains a system controller that is responsible for controlling
> +the pad setting of the IPs that are present. Communication between the
> +host processor running an OS and the system controller happens through
> +a SCU protocol.
> +
> +Please also refer to fsl,imx-pinctrl.txt in this directory for i.MX common
> +pinctrl binding.
> +
> +=== Pin Controller Node ===
> +
> +Required properties:
> +- compatible: "fsl,imx8qxp-iomuxc"
How is this block accessed?
I see the answer in the dts is the SCU. Is this really a IOMUXC as
defined by prior i.MX chips if it is hidden behind firmware?
> +
> +=== Pin Configuration Node ===
> +- fsl,pins: Each entry consists of 3 integers which represents the mux and
> + config setting for one pin. The first 2 integers <pin_id mux_mode>
> + are specified using a PIN_FUNC_ID macro, which can be found
> + in <dt-bindings/pinctrl/pads-imx8qxp.h>. The last integer CONFIG
> + is the pad setting value like pull-up on this pin.
> + Please refer to i.MX8QXP Reference Manual for detailed
> + CONFIG settings.
> +
> +Examples:
> +#include <dt-bindings/pinctrl/pads-imx8qxp.h>
> +
> +/* Pin Controller Node */
> +iomuxc: iomuxc {
pinctrl {
> + compatible = "fsl,imx8qxp-iomuxc";
> +
> + /* Pin Configuration Node */
> + pinctrl_lpuart0: lpuart0grp {
> + fsl,pins = <
> + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
> + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
> + >;
> + };
> +};
> diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h
> new file mode 100644
> index 0000000..8f477c3
> --- /dev/null
> +++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h
> @@ -0,0 +1,751 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + * Copyright 2017~2018 NXP
> + */
> +
> +#ifndef _SC_PADS_H
> +#define _SC_PADS_H
> +
> +/* pin id */
> +#define SC_P_PCIE_CTRL0_PERST_B 0
> +#define SC_P_PCIE_CTRL0_CLKREQ_B 1
> +#define SC_P_PCIE_CTRL0_WAKE_B 2
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3
> +#define SC_P_USB_SS3_TC0 4
> +#define SC_P_USB_SS3_TC1 5
> +#define SC_P_USB_SS3_TC2 6
> +#define SC_P_USB_SS3_TC3 7
> +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8
> +#define SC_P_EMMC0_CLK 9
> +#define SC_P_EMMC0_CMD 10
> +#define SC_P_EMMC0_DATA0 11
> +#define SC_P_EMMC0_DATA1 12
> +#define SC_P_EMMC0_DATA2 13
> +#define SC_P_EMMC0_DATA3 14
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15
> +#define SC_P_EMMC0_DATA4 16
> +#define SC_P_EMMC0_DATA5 17
> +#define SC_P_EMMC0_DATA6 18
> +#define SC_P_EMMC0_DATA7 19
> +#define SC_P_EMMC0_STROBE 20
> +#define SC_P_EMMC0_RESET_B 21
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22
> +#define SC_P_USDHC1_RESET_B 23
> +#define SC_P_USDHC1_VSELECT 24
> +#define SC_P_CTL_NAND_RE_P_N 25
> +#define SC_P_USDHC1_WP 26
> +#define SC_P_USDHC1_CD_B 27
> +#define SC_P_CTL_NAND_DQS_P_N 28
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29
> +#define SC_P_USDHC1_CLK 30
> +#define SC_P_USDHC1_CMD 31
> +#define SC_P_USDHC1_DATA0 32
> +#define SC_P_USDHC1_DATA1 33
> +#define SC_P_USDHC1_DATA2 34
> +#define SC_P_USDHC1_DATA3 35
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36
> +#define SC_P_ENET0_RGMII_TXC 37
> +#define SC_P_ENET0_RGMII_TX_CTL 38
> +#define SC_P_ENET0_RGMII_TXD0 39
> +#define SC_P_ENET0_RGMII_TXD1 40
> +#define SC_P_ENET0_RGMII_TXD2 41
> +#define SC_P_ENET0_RGMII_TXD3 42
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43
> +#define SC_P_ENET0_RGMII_RXC 44
> +#define SC_P_ENET0_RGMII_RX_CTL 45
> +#define SC_P_ENET0_RGMII_RXD0 46
> +#define SC_P_ENET0_RGMII_RXD1 47
> +#define SC_P_ENET0_RGMII_RXD2 48
> +#define SC_P_ENET0_RGMII_RXD3 49
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50
> +#define SC_P_ENET0_REFCLK_125M_25M 51
> +#define SC_P_ENET0_MDIO 52
> +#define SC_P_ENET0_MDC 53
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54
> +#define SC_P_ESAI0_FSR 55
> +#define SC_P_ESAI0_FST 56
> +#define SC_P_ESAI0_SCKR 57
> +#define SC_P_ESAI0_SCKT 58
> +#define SC_P_ESAI0_TX0 59
> +#define SC_P_ESAI0_TX1 60
> +#define SC_P_ESAI0_TX2_RX3 61
> +#define SC_P_ESAI0_TX3_RX2 62
> +#define SC_P_ESAI0_TX4_RX1 63
> +#define SC_P_ESAI0_TX5_RX0 64
> +#define SC_P_SPDIF0_RX 65
> +#define SC_P_SPDIF0_TX 66
> +#define SC_P_SPDIF0_EXT_CLK 67
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68
> +#define SC_P_SPI3_SCK 69
> +#define SC_P_SPI3_SDO 70
> +#define SC_P_SPI3_SDI 71
> +#define SC_P_SPI3_CS0 72
> +#define SC_P_SPI3_CS1 73
> +#define SC_P_MCLK_IN1 74
> +#define SC_P_MCLK_IN0 75
> +#define SC_P_MCLK_OUT0 76
> +#define SC_P_UART1_TX 77
> +#define SC_P_UART1_RX 78
> +#define SC_P_UART1_RTS_B 79
> +#define SC_P_UART1_CTS_B 80
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81
> +#define SC_P_SAI0_TXD 82
> +#define SC_P_SAI0_TXC 83
> +#define SC_P_SAI0_RXD 84
> +#define SC_P_SAI0_TXFS 85
> +#define SC_P_SAI1_RXD 86
> +#define SC_P_SAI1_RXC 87
> +#define SC_P_SAI1_RXFS 88
> +#define SC_P_SPI2_CS0 89
> +#define SC_P_SPI2_SDO 90
> +#define SC_P_SPI2_SDI 91
> +#define SC_P_SPI2_SCK 92
> +#define SC_P_SPI0_SCK 93
> +#define SC_P_SPI0_SDI 94
> +#define SC_P_SPI0_SDO 95
> +#define SC_P_SPI0_CS1 96
> +#define SC_P_SPI0_CS0 97
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98
> +#define SC_P_ADC_IN1 99
> +#define SC_P_ADC_IN0 100
> +#define SC_P_ADC_IN3 101
> +#define SC_P_ADC_IN2 102
> +#define SC_P_ADC_IN5 103
> +#define SC_P_ADC_IN4 104
> +#define SC_P_FLEXCAN0_RX 105
> +#define SC_P_FLEXCAN0_TX 106
> +#define SC_P_FLEXCAN1_RX 107
> +#define SC_P_FLEXCAN1_TX 108
> +#define SC_P_FLEXCAN2_RX 109
> +#define SC_P_FLEXCAN2_TX 110
> +#define SC_P_UART0_RX 111
> +#define SC_P_UART0_TX 112
> +#define SC_P_UART2_TX 113
> +#define SC_P_UART2_RX 114
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115
> +#define SC_P_MIPI_DSI0_I2C0_SCL 116
> +#define SC_P_MIPI_DSI0_I2C0_SDA 117
> +#define SC_P_MIPI_DSI0_GPIO0_00 118
> +#define SC_P_MIPI_DSI0_GPIO0_01 119
> +#define SC_P_MIPI_DSI1_I2C0_SCL 120
> +#define SC_P_MIPI_DSI1_I2C0_SDA 121
> +#define SC_P_MIPI_DSI1_GPIO0_00 122
> +#define SC_P_MIPI_DSI1_GPIO0_01 123
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124
> +#define SC_P_JTAG_TRST_B 125
> +#define SC_P_PMIC_I2C_SCL 126
> +#define SC_P_PMIC_I2C_SDA 127
> +#define SC_P_PMIC_INT_B 128
> +#define SC_P_SCU_GPIO0_00 129
> +#define SC_P_SCU_GPIO0_01 130
> +#define SC_P_SCU_PMIC_STANDBY 131
> +#define SC_P_SCU_BOOT_MODE0 132
> +#define SC_P_SCU_BOOT_MODE1 133
> +#define SC_P_SCU_BOOT_MODE2 134
> +#define SC_P_SCU_BOOT_MODE3 135
> +#define SC_P_CSI_D00 136
> +#define SC_P_CSI_D01 137
> +#define SC_P_CSI_D02 138
> +#define SC_P_CSI_D03 139
> +#define SC_P_CSI_D04 140
> +#define SC_P_CSI_D05 141
> +#define SC_P_CSI_D06 142
> +#define SC_P_CSI_D07 143
> +#define SC_P_CSI_HSYNC 144
> +#define SC_P_CSI_VSYNC 145
> +#define SC_P_CSI_PCLK 146
> +#define SC_P_CSI_MCLK 147
> +#define SC_P_CSI_EN 148
> +#define SC_P_CSI_RESET 149
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150
> +#define SC_P_MIPI_CSI0_MCLK_OUT 151
> +#define SC_P_MIPI_CSI0_I2C0_SCL 152
> +#define SC_P_MIPI_CSI0_I2C0_SDA 153
> +#define SC_P_MIPI_CSI0_GPIO0_01 154
> +#define SC_P_MIPI_CSI0_GPIO0_00 155
> +#define SC_P_QSPI0A_DATA0 156
> +#define SC_P_QSPI0A_DATA1 157
> +#define SC_P_QSPI0A_DATA2 158
> +#define SC_P_QSPI0A_DATA3 159
> +#define SC_P_QSPI0A_DQS 160
> +#define SC_P_QSPI0A_SS0_B 161
> +#define SC_P_QSPI0A_SS1_B 162
> +#define SC_P_QSPI0A_SCLK 163
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164
> +#define SC_P_QSPI0B_SCLK 165
> +#define SC_P_QSPI0B_DATA0 166
> +#define SC_P_QSPI0B_DATA1 167
> +#define SC_P_QSPI0B_DATA2 168
> +#define SC_P_QSPI0B_DATA3 169
> +#define SC_P_QSPI0B_DQS 170
> +#define SC_P_QSPI0B_SS0_B 171
> +#define SC_P_QSPI0B_SS1_B 172
> +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173
> +
> +/*
> + * format: <pin_id mux_mode>
> + */
> +#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0
> +#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 SC_P_PCIE_CTRL0_PERST_B 4
> +#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B SC_P_PCIE_CTRL0_CLKREQ_B 0
> +#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 SC_P_PCIE_CTRL0_CLKREQ_B 4
> +#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B SC_P_PCIE_CTRL0_WAKE_B 0
> +#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 SC_P_PCIE_CTRL0_WAKE_B 4
> +#define SC_P_USB_SS3_TC0_ADMA_I2C1_SCL SC_P_USB_SS3_TC0 0
> +#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR SC_P_USB_SS3_TC0 1
> +#define SC_P_USB_SS3_TC0_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC0 2
> +#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 SC_P_USB_SS3_TC0 4
> +#define SC_P_USB_SS3_TC1_ADMA_I2C1_SCL SC_P_USB_SS3_TC1 0
> +#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC1 1
> +#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 SC_P_USB_SS3_TC1 4
> +#define SC_P_USB_SS3_TC2_ADMA_I2C1_SDA SC_P_USB_SS3_TC2 0
> +#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC SC_P_USB_SS3_TC2 1
> +#define SC_P_USB_SS3_TC2_CONN_USB_OTG2_OC SC_P_USB_SS3_TC2 2
> +#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 SC_P_USB_SS3_TC2 4
> +#define SC_P_USB_SS3_TC3_ADMA_I2C1_SDA SC_P_USB_SS3_TC3 0
> +#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC SC_P_USB_SS3_TC3 1
> +#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 SC_P_USB_SS3_TC3 4
> +#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK SC_P_EMMC0_CLK 0
> +#define SC_P_EMMC0_CLK_CONN_NAND_READY_B SC_P_EMMC0_CLK 1
> +#define SC_P_EMMC0_CLK_LSIO_GPIO4_IO07 SC_P_EMMC0_CLK 4
> +#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD SC_P_EMMC0_CMD 0
> +#define SC_P_EMMC0_CMD_CONN_NAND_DQS SC_P_EMMC0_CMD 1
> +#define SC_P_EMMC0_CMD_LSIO_GPIO4_IO08 SC_P_EMMC0_CMD 4
> +#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 SC_P_EMMC0_DATA0 0
> +#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 SC_P_EMMC0_DATA0 1
> +#define SC_P_EMMC0_DATA0_LSIO_GPIO4_IO09 SC_P_EMMC0_DATA0 4
> +#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 SC_P_EMMC0_DATA1 0
> +#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 SC_P_EMMC0_DATA1 1
> +#define SC_P_EMMC0_DATA1_LSIO_GPIO4_IO10 SC_P_EMMC0_DATA1 4
> +#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 SC_P_EMMC0_DATA2 0
> +#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 SC_P_EMMC0_DATA2 1
> +#define SC_P_EMMC0_DATA2_LSIO_GPIO4_IO11 SC_P_EMMC0_DATA2 4
> +#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 SC_P_EMMC0_DATA3 0
> +#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 SC_P_EMMC0_DATA3 1
> +#define SC_P_EMMC0_DATA3_LSIO_GPIO4_IO12 SC_P_EMMC0_DATA3 4
> +#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 SC_P_EMMC0_DATA4 0
> +#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 SC_P_EMMC0_DATA4 1
> +#define SC_P_EMMC0_DATA4_CONN_EMMC0_WP SC_P_EMMC0_DATA4 3
> +#define SC_P_EMMC0_DATA4_LSIO_GPIO4_IO13 SC_P_EMMC0_DATA4 4
> +#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 SC_P_EMMC0_DATA5 0
> +#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 SC_P_EMMC0_DATA5 1
> +#define SC_P_EMMC0_DATA5_CONN_EMMC0_VSELECT SC_P_EMMC0_DATA5 3
> +#define SC_P_EMMC0_DATA5_LSIO_GPIO4_IO14 SC_P_EMMC0_DATA5 4
> +#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 SC_P_EMMC0_DATA6 0
> +#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 SC_P_EMMC0_DATA6 1
> +#define SC_P_EMMC0_DATA6_CONN_MLB_CLK SC_P_EMMC0_DATA6 3
> +#define SC_P_EMMC0_DATA6_LSIO_GPIO4_IO15 SC_P_EMMC0_DATA6 4
> +#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 SC_P_EMMC0_DATA7 0
> +#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 SC_P_EMMC0_DATA7 1
> +#define SC_P_EMMC0_DATA7_CONN_MLB_SIG SC_P_EMMC0_DATA7 3
> +#define SC_P_EMMC0_DATA7_LSIO_GPIO4_IO16 SC_P_EMMC0_DATA7 4
> +#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE SC_P_EMMC0_STROBE 0
> +#define SC_P_EMMC0_STROBE_CONN_NAND_CLE SC_P_EMMC0_STROBE 1
> +#define SC_P_EMMC0_STROBE_CONN_MLB_DATA SC_P_EMMC0_STROBE 3
> +#define SC_P_EMMC0_STROBE_LSIO_GPIO4_IO17 SC_P_EMMC0_STROBE 4
> +#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B SC_P_EMMC0_RESET_B 0
> +#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B SC_P_EMMC0_RESET_B 1
> +#define SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18 SC_P_EMMC0_RESET_B 4
> +#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B SC_P_USDHC1_RESET_B 0
> +#define SC_P_USDHC1_RESET_B_CONN_NAND_RE_N SC_P_USDHC1_RESET_B 1
> +#define SC_P_USDHC1_RESET_B_ADMA_SPI2_SCK SC_P_USDHC1_RESET_B 2
> +#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 SC_P_USDHC1_RESET_B 4
> +#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT SC_P_USDHC1_VSELECT 0
> +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_P SC_P_USDHC1_VSELECT 1
> +#define SC_P_USDHC1_VSELECT_ADMA_SPI2_SDO SC_P_USDHC1_VSELECT 2
> +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_B SC_P_USDHC1_VSELECT 3
> +#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO20 SC_P_USDHC1_VSELECT 4
> +#define SC_P_USDHC1_WP_CONN_USDHC1_WP SC_P_USDHC1_WP 0
> +#define SC_P_USDHC1_WP_CONN_NAND_DQS_N SC_P_USDHC1_WP 1
> +#define SC_P_USDHC1_WP_ADMA_SPI2_SDI SC_P_USDHC1_WP 2
> +#define SC_P_USDHC1_WP_LSIO_GPIO4_IO21 SC_P_USDHC1_WP 4
> +#define SC_P_USDHC1_CD_B_CONN_USDHC1_CD_B SC_P_USDHC1_CD_B 0
> +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS_P SC_P_USDHC1_CD_B 1
> +#define SC_P_USDHC1_CD_B_ADMA_SPI2_CS0 SC_P_USDHC1_CD_B 2
> +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS SC_P_USDHC1_CD_B 3
> +#define SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 SC_P_USDHC1_CD_B 4
> +#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK SC_P_USDHC1_CLK 0
> +#define SC_P_USDHC1_CLK_ADMA_UART3_RX SC_P_USDHC1_CLK 2
> +#define SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 SC_P_USDHC1_CLK 4
> +#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD SC_P_USDHC1_CMD 0
> +#define SC_P_USDHC1_CMD_CONN_NAND_CE0_B SC_P_USDHC1_CMD 1
> +#define SC_P_USDHC1_CMD_ADMA_MQS_R SC_P_USDHC1_CMD 2
> +#define SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 SC_P_USDHC1_CMD 4
> +#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 SC_P_USDHC1_DATA0 0
> +#define SC_P_USDHC1_DATA0_CONN_NAND_CE1_B SC_P_USDHC1_DATA0 1
> +#define SC_P_USDHC1_DATA0_ADMA_MQS_L SC_P_USDHC1_DATA0 2
> +#define SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 SC_P_USDHC1_DATA0 4
> +#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 SC_P_USDHC1_DATA1 0
> +#define SC_P_USDHC1_DATA1_CONN_NAND_RE_B SC_P_USDHC1_DATA1 1
> +#define SC_P_USDHC1_DATA1_ADMA_UART3_TX SC_P_USDHC1_DATA1 2
> +#define SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 SC_P_USDHC1_DATA1 4
> +#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 SC_P_USDHC1_DATA2 0
> +#define SC_P_USDHC1_DATA2_CONN_NAND_WE_B SC_P_USDHC1_DATA2 1
> +#define SC_P_USDHC1_DATA2_ADMA_UART3_CTS_B SC_P_USDHC1_DATA2 2
> +#define SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 SC_P_USDHC1_DATA2 4
> +#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 SC_P_USDHC1_DATA3 0
> +#define SC_P_USDHC1_DATA3_CONN_NAND_ALE SC_P_USDHC1_DATA3 1
> +#define SC_P_USDHC1_DATA3_ADMA_UART3_RTS_B SC_P_USDHC1_DATA3 2
> +#define SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 SC_P_USDHC1_DATA3 4
> +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC SC_P_ENET0_RGMII_TXC 0
> +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT SC_P_ENET0_RGMII_TXC 1
> +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN SC_P_ENET0_RGMII_TXC 2
> +#define SC_P_ENET0_RGMII_TXC_CONN_NAND_CE1_B SC_P_ENET0_RGMII_TXC 3
> +#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 SC_P_ENET0_RGMII_TXC 4
> +#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL SC_P_ENET0_RGMII_TX_CTL 0
> +#define SC_P_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B SC_P_ENET0_RGMII_TX_CTL 3
> +#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 SC_P_ENET0_RGMII_TX_CTL 4
> +#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 SC_P_ENET0_RGMII_TXD0 0
> +#define SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT SC_P_ENET0_RGMII_TXD0 3
> +#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 SC_P_ENET0_RGMII_TXD0 4
> +#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 SC_P_ENET0_RGMII_TXD1 0
> +#define SC_P_ENET0_RGMII_TXD1_CONN_USDHC1_WP SC_P_ENET0_RGMII_TXD1 3
> +#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 SC_P_ENET0_RGMII_TXD1 4
> +#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 SC_P_ENET0_RGMII_TXD2 0
> +#define SC_P_ENET0_RGMII_TXD2_CONN_MLB_CLK SC_P_ENET0_RGMII_TXD2 1
> +#define SC_P_ENET0_RGMII_TXD2_CONN_NAND_CE0_B SC_P_ENET0_RGMII_TXD2 2
> +#define SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B SC_P_ENET0_RGMII_TXD2 3
> +#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 SC_P_ENET0_RGMII_TXD2 4
> +#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 SC_P_ENET0_RGMII_TXD3 0
> +#define SC_P_ENET0_RGMII_TXD3_CONN_MLB_SIG SC_P_ENET0_RGMII_TXD3 1
> +#define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B SC_P_ENET0_RGMII_TXD3 2
> +#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 SC_P_ENET0_RGMII_TXD3 4
> +#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0
> +#define SC_P_ENET0_RGMII_RXC_CONN_MLB_DATA SC_P_ENET0_RGMII_RXC 1
> +#define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B SC_P_ENET0_RGMII_RXC 2
> +#define SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK SC_P_ENET0_RGMII_RXC 3
> +#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 SC_P_ENET0_RGMII_RXC 4
> +#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL SC_P_ENET0_RGMII_RX_CTL 0
> +#define SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD SC_P_ENET0_RGMII_RX_CTL 3
> +#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 SC_P_ENET0_RGMII_RX_CTL 4
> +#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 SC_P_ENET0_RGMII_RXD0 0
> +#define SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 SC_P_ENET0_RGMII_RXD0 3
> +#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 SC_P_ENET0_RGMII_RXD0 4
> +#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 SC_P_ENET0_RGMII_RXD1 0
> +#define SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 SC_P_ENET0_RGMII_RXD1 3
> +#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 SC_P_ENET0_RGMII_RXD1 4
> +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 SC_P_ENET0_RGMII_RXD2 0
> +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER SC_P_ENET0_RGMII_RXD2 1
> +#define SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 SC_P_ENET0_RGMII_RXD2 3
> +#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 SC_P_ENET0_RGMII_RXD2 4
> +#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 SC_P_ENET0_RGMII_RXD3 0
> +#define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE SC_P_ENET0_RGMII_RXD3 2
> +#define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 SC_P_ENET0_RGMII_RXD3 3
> +#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 SC_P_ENET0_RGMII_RXD3 4
> +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0
> +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1
> +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET0_REFCLK_125M_25M 2
> +#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 SC_P_ENET0_REFCLK_125M_25M 4
> +#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO SC_P_ENET0_MDIO 0
> +#define SC_P_ENET0_MDIO_ADMA_I2C3_SDA SC_P_ENET0_MDIO 1
> +#define SC_P_ENET0_MDIO_CONN_ENET1_MDIO SC_P_ENET0_MDIO 2
> +#define SC_P_ENET0_MDIO_LSIO_GPIO5_IO10 SC_P_ENET0_MDIO 4
> +#define SC_P_ENET0_MDC_CONN_ENET0_MDC SC_P_ENET0_MDC 0
> +#define SC_P_ENET0_MDC_ADMA_I2C3_SCL SC_P_ENET0_MDC 1
> +#define SC_P_ENET0_MDC_CONN_ENET1_MDC SC_P_ENET0_MDC 2
> +#define SC_P_ENET0_MDC_LSIO_GPIO5_IO11 SC_P_ENET0_MDC 4
> +#define SC_P_ESAI0_FSR_ADMA_ESAI0_FSR SC_P_ESAI0_FSR 0
> +#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT SC_P_ESAI0_FSR 1
> +#define SC_P_ESAI0_FSR_ADMA_LCDIF_D00 SC_P_ESAI0_FSR 2
> +#define SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC SC_P_ESAI0_FSR 3
> +#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN SC_P_ESAI0_FSR 4
> +#define SC_P_ESAI0_FST_ADMA_ESAI0_FST SC_P_ESAI0_FST 0
> +#define SC_P_ESAI0_FST_CONN_MLB_CLK SC_P_ESAI0_FST 1
> +#define SC_P_ESAI0_FST_ADMA_LCDIF_D01 SC_P_ESAI0_FST 2
> +#define SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 SC_P_ESAI0_FST 3
> +#define SC_P_ESAI0_FST_LSIO_GPIO0_IO01 SC_P_ESAI0_FST 4
> +#define SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR SC_P_ESAI0_SCKR 0
> +#define SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 SC_P_ESAI0_SCKR 2
> +#define SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL SC_P_ESAI0_SCKR 3
> +#define SC_P_ESAI0_SCKR_LSIO_GPIO0_IO02 SC_P_ESAI0_SCKR 4
> +#define SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT SC_P_ESAI0_SCKT 0
> +#define SC_P_ESAI0_SCKT_CONN_MLB_SIG SC_P_ESAI0_SCKT 1
> +#define SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 SC_P_ESAI0_SCKT 2
> +#define SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 SC_P_ESAI0_SCKT 3
> +#define SC_P_ESAI0_SCKT_LSIO_GPIO0_IO03 SC_P_ESAI0_SCKT 4
> +#define SC_P_ESAI0_TX0_ADMA_ESAI0_TX0 SC_P_ESAI0_TX0 0
> +#define SC_P_ESAI0_TX0_CONN_MLB_DATA SC_P_ESAI0_TX0 1
> +#define SC_P_ESAI0_TX0_ADMA_LCDIF_D04 SC_P_ESAI0_TX0 2
> +#define SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC SC_P_ESAI0_TX0 3
> +#define SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 SC_P_ESAI0_TX0 4
> +#define SC_P_ESAI0_TX1_ADMA_ESAI0_TX1 SC_P_ESAI0_TX1 0
> +#define SC_P_ESAI0_TX1_ADMA_LCDIF_D05 SC_P_ESAI0_TX1 2
> +#define SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 SC_P_ESAI0_TX1 3
> +#define SC_P_ESAI0_TX1_LSIO_GPIO0_IO05 SC_P_ESAI0_TX1 4
> +#define SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 SC_P_ESAI0_TX2_RX3 0
> +#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER SC_P_ESAI0_TX2_RX3 1
> +#define SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 SC_P_ESAI0_TX2_RX3 2
> +#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 SC_P_ESAI0_TX2_RX3 3
> +#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 SC_P_ESAI0_TX2_RX3 4
> +#define SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 SC_P_ESAI0_TX3_RX2 0
> +#define SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 SC_P_ESAI0_TX3_RX2 2
> +#define SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 SC_P_ESAI0_TX3_RX2 3
> +#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 SC_P_ESAI0_TX3_RX2 4
> +#define SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 SC_P_ESAI0_TX4_RX1 0
> +#define SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 SC_P_ESAI0_TX4_RX1 2
> +#define SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 SC_P_ESAI0_TX4_RX1 3
> +#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO0_IO08 SC_P_ESAI0_TX4_RX1 4
> +#define SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 SC_P_ESAI0_TX5_RX0 0
> +#define SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 SC_P_ESAI0_TX5_RX0 2
> +#define SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 SC_P_ESAI0_TX5_RX0 3
> +#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO0_IO09 SC_P_ESAI0_TX5_RX0 4
> +#define SC_P_SPDIF0_RX_ADMA_SPDIF0_RX SC_P_SPDIF0_RX 0
> +#define SC_P_SPDIF0_RX_ADMA_MQS_R SC_P_SPDIF0_RX 1
> +#define SC_P_SPDIF0_RX_ADMA_LCDIF_D10 SC_P_SPDIF0_RX 2
> +#define SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 SC_P_SPDIF0_RX 3
> +#define SC_P_SPDIF0_RX_LSIO_GPIO0_IO10 SC_P_SPDIF0_RX 4
> +#define SC_P_SPDIF0_TX_ADMA_SPDIF0_TX SC_P_SPDIF0_TX 0
> +#define SC_P_SPDIF0_TX_ADMA_MQS_L SC_P_SPDIF0_TX 1
> +#define SC_P_SPDIF0_TX_ADMA_LCDIF_D11 SC_P_SPDIF0_TX 2
> +#define SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL SC_P_SPDIF0_TX 3
> +#define SC_P_SPDIF0_TX_LSIO_GPIO0_IO11 SC_P_SPDIF0_TX 4
> +#define SC_P_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK SC_P_SPDIF0_EXT_CLK 0
> +#define SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 SC_P_SPDIF0_EXT_CLK 2
> +#define SC_P_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M SC_P_SPDIF0_EXT_CLK 3
> +#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 SC_P_SPDIF0_EXT_CLK 4
> +#define SC_P_SPI3_SCK_ADMA_SPI3_SCK SC_P_SPI3_SCK 0
> +#define SC_P_SPI3_SCK_ADMA_LCDIF_D13 SC_P_SPI3_SCK 2
> +#define SC_P_SPI3_SCK_LSIO_GPIO0_IO13 SC_P_SPI3_SCK 4
> +#define SC_P_SPI3_SDO_ADMA_SPI3_SDO SC_P_SPI3_SDO 0
> +#define SC_P_SPI3_SDO_ADMA_LCDIF_D14 SC_P_SPI3_SDO 2
> +#define SC_P_SPI3_SDO_LSIO_GPIO0_IO14 SC_P_SPI3_SDO 4
> +#define SC_P_SPI3_SDI_ADMA_SPI3_SDI SC_P_SPI3_SDI 0
> +#define SC_P_SPI3_SDI_ADMA_LCDIF_D15 SC_P_SPI3_SDI 2
> +#define SC_P_SPI3_SDI_LSIO_GPIO0_IO15 SC_P_SPI3_SDI 4
> +#define SC_P_SPI3_CS0_ADMA_SPI3_CS0 SC_P_SPI3_CS0 0
> +#define SC_P_SPI3_CS0_ADMA_ACM_MCLK_OUT1 SC_P_SPI3_CS0 1
> +#define SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC SC_P_SPI3_CS0 2
> +#define SC_P_SPI3_CS0_LSIO_GPIO0_IO16 SC_P_SPI3_CS0 4
> +#define SC_P_SPI3_CS1_ADMA_SPI3_CS1 SC_P_SPI3_CS1 0
> +#define SC_P_SPI3_CS1_ADMA_I2C3_SCL SC_P_SPI3_CS1 1
> +#define SC_P_SPI3_CS1_ADMA_LCDIF_RESET SC_P_SPI3_CS1 2
> +#define SC_P_SPI3_CS1_ADMA_SPI2_CS0 SC_P_SPI3_CS1 3
> +#define SC_P_SPI3_CS1_ADMA_LCDIF_D16 SC_P_SPI3_CS1 4
> +#define SC_P_MCLK_IN1_ADMA_ACM_MCLK_IN1 SC_P_MCLK_IN1 0
> +#define SC_P_MCLK_IN1_ADMA_I2C3_SDA SC_P_MCLK_IN1 1
> +#define SC_P_MCLK_IN1_ADMA_LCDIF_EN SC_P_MCLK_IN1 2
> +#define SC_P_MCLK_IN1_ADMA_SPI2_SCK SC_P_MCLK_IN1 3
> +#define SC_P_MCLK_IN1_ADMA_LCDIF_D17 SC_P_MCLK_IN1 4
> +#define SC_P_MCLK_IN0_ADMA_ACM_MCLK_IN0 SC_P_MCLK_IN0 0
> +#define SC_P_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK SC_P_MCLK_IN0 1
> +#define SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC SC_P_MCLK_IN0 2
> +#define SC_P_MCLK_IN0_ADMA_SPI2_SDI SC_P_MCLK_IN0 3
> +#define SC_P_MCLK_IN0_LSIO_GPIO0_IO19 SC_P_MCLK_IN0 4
> +#define SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 SC_P_MCLK_OUT0 0
> +#define SC_P_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK SC_P_MCLK_OUT0 1
> +#define SC_P_MCLK_OUT0_ADMA_LCDIF_CLK SC_P_MCLK_OUT0 2
> +#define SC_P_MCLK_OUT0_ADMA_SPI2_SDO SC_P_MCLK_OUT0 3
> +#define SC_P_MCLK_OUT0_LSIO_GPIO0_IO20 SC_P_MCLK_OUT0 4
> +#define SC_P_UART1_TX_ADMA_UART1_TX SC_P_UART1_TX 0
> +#define SC_P_UART1_TX_LSIO_PWM0_OUT SC_P_UART1_TX 1
> +#define SC_P_UART1_TX_LSIO_GPT0_CAPTURE SC_P_UART1_TX 2
> +#define SC_P_UART1_TX_LSIO_GPIO0_IO21 SC_P_UART1_TX 4
> +#define SC_P_UART1_RX_ADMA_UART1_RX SC_P_UART1_RX 0
> +#define SC_P_UART1_RX_LSIO_PWM1_OUT SC_P_UART1_RX 1
> +#define SC_P_UART1_RX_LSIO_GPT0_COMPARE SC_P_UART1_RX 2
> +#define SC_P_UART1_RX_LSIO_GPT1_CLK SC_P_UART1_RX 3
> +#define SC_P_UART1_RX_LSIO_GPIO0_IO22 SC_P_UART1_RX 4
> +#define SC_P_UART1_RTS_B_ADMA_UART1_RTS_B SC_P_UART1_RTS_B 0
> +#define SC_P_UART1_RTS_B_LSIO_PWM2_OUT SC_P_UART1_RTS_B 1
> +#define SC_P_UART1_RTS_B_ADMA_LCDIF_D16 SC_P_UART1_RTS_B 2
> +#define SC_P_UART1_RTS_B_LSIO_GPT1_CAPTURE SC_P_UART1_RTS_B 3
> +#define SC_P_UART1_RTS_B_LSIO_GPT0_CLK SC_P_UART1_RTS_B 4
> +#define SC_P_UART1_CTS_B_ADMA_UART1_CTS_B SC_P_UART1_CTS_B 0
> +#define SC_P_UART1_CTS_B_LSIO_PWM3_OUT SC_P_UART1_CTS_B 1
> +#define SC_P_UART1_CTS_B_ADMA_LCDIF_D17 SC_P_UART1_CTS_B 2
> +#define SC_P_UART1_CTS_B_LSIO_GPT1_COMPARE SC_P_UART1_CTS_B 3
> +#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO24 SC_P_UART1_CTS_B 4
> +#define SC_P_SAI0_TXD_ADMA_SAI0_TXD SC_P_SAI0_TXD 0
> +#define SC_P_SAI0_TXD_ADMA_SAI1_RXC SC_P_SAI0_TXD 1
> +#define SC_P_SAI0_TXD_ADMA_SPI1_SDO SC_P_SAI0_TXD 2
> +#define SC_P_SAI0_TXD_ADMA_LCDIF_D18 SC_P_SAI0_TXD 3
> +#define SC_P_SAI0_TXD_LSIO_GPIO0_IO25 SC_P_SAI0_TXD 4
> +#define SC_P_SAI0_TXC_ADMA_SAI0_TXC SC_P_SAI0_TXC 0
> +#define SC_P_SAI0_TXC_ADMA_SAI1_TXD SC_P_SAI0_TXC 1
> +#define SC_P_SAI0_TXC_ADMA_SPI1_SDI SC_P_SAI0_TXC 2
> +#define SC_P_SAI0_TXC_ADMA_LCDIF_D19 SC_P_SAI0_TXC 3
> +#define SC_P_SAI0_TXC_LSIO_GPIO0_IO26 SC_P_SAI0_TXC 4
> +#define SC_P_SAI0_RXD_ADMA_SAI0_RXD SC_P_SAI0_RXD 0
> +#define SC_P_SAI0_RXD_ADMA_SAI1_RXFS SC_P_SAI0_RXD 1
> +#define SC_P_SAI0_RXD_ADMA_SPI1_CS0 SC_P_SAI0_RXD 2
> +#define SC_P_SAI0_RXD_ADMA_LCDIF_D20 SC_P_SAI0_RXD 3
> +#define SC_P_SAI0_RXD_LSIO_GPIO0_IO27 SC_P_SAI0_RXD 4
> +#define SC_P_SAI0_TXFS_ADMA_SAI0_TXFS SC_P_SAI0_TXFS 0
> +#define SC_P_SAI0_TXFS_ADMA_SPI2_CS1 SC_P_SAI0_TXFS 1
> +#define SC_P_SAI0_TXFS_ADMA_SPI1_SCK SC_P_SAI0_TXFS 2
> +#define SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 SC_P_SAI0_TXFS 4
> +#define SC_P_SAI1_RXD_ADMA_SAI1_RXD SC_P_SAI1_RXD 0
> +#define SC_P_SAI1_RXD_ADMA_SAI0_RXFS SC_P_SAI1_RXD 1
> +#define SC_P_SAI1_RXD_ADMA_SPI1_CS1 SC_P_SAI1_RXD 2
> +#define SC_P_SAI1_RXD_ADMA_LCDIF_D21 SC_P_SAI1_RXD 3
> +#define SC_P_SAI1_RXD_LSIO_GPIO0_IO29 SC_P_SAI1_RXD 4
> +#define SC_P_SAI1_RXC_ADMA_SAI1_RXC SC_P_SAI1_RXC 0
> +#define SC_P_SAI1_RXC_ADMA_SAI1_TXC SC_P_SAI1_RXC 1
> +#define SC_P_SAI1_RXC_ADMA_LCDIF_D22 SC_P_SAI1_RXC 3
> +#define SC_P_SAI1_RXC_LSIO_GPIO0_IO30 SC_P_SAI1_RXC 4
> +#define SC_P_SAI1_RXFS_ADMA_SAI1_RXFS SC_P_SAI1_RXFS 0
> +#define SC_P_SAI1_RXFS_ADMA_SAI1_TXFS SC_P_SAI1_RXFS 1
> +#define SC_P_SAI1_RXFS_ADMA_LCDIF_D23 SC_P_SAI1_RXFS 3
> +#define SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 SC_P_SAI1_RXFS 4
> +#define SC_P_SPI2_CS0_ADMA_SPI2_CS0 SC_P_SPI2_CS0 0
> +#define SC_P_SPI2_CS0_LSIO_GPIO1_IO00 SC_P_SPI2_CS0 4
> +#define SC_P_SPI2_SDO_ADMA_SPI2_SDO SC_P_SPI2_SDO 0
> +#define SC_P_SPI2_SDO_LSIO_GPIO1_IO01 SC_P_SPI2_SDO 4
> +#define SC_P_SPI2_SDI_ADMA_SPI2_SDI SC_P_SPI2_SDI 0
> +#define SC_P_SPI2_SDI_LSIO_GPIO1_IO02 SC_P_SPI2_SDI 4
> +#define SC_P_SPI2_SCK_ADMA_SPI2_SCK SC_P_SPI2_SCK 0
> +#define SC_P_SPI2_SCK_LSIO_GPIO1_IO03 SC_P_SPI2_SCK 4
> +#define SC_P_SPI0_SCK_ADMA_SPI0_SCK SC_P_SPI0_SCK 0
> +#define SC_P_SPI0_SCK_ADMA_SAI0_TXC SC_P_SPI0_SCK 1
> +#define SC_P_SPI0_SCK_M40_I2C0_SCL SC_P_SPI0_SCK 2
> +#define SC_P_SPI0_SCK_M40_GPIO0_IO00 SC_P_SPI0_SCK 3
> +#define SC_P_SPI0_SCK_LSIO_GPIO1_IO04 SC_P_SPI0_SCK 4
> +#define SC_P_SPI0_SDI_ADMA_SPI0_SDI SC_P_SPI0_SDI 0
> +#define SC_P_SPI0_SDI_ADMA_SAI0_TXD SC_P_SPI0_SDI 1
> +#define SC_P_SPI0_SDI_M40_TPM0_CH0 SC_P_SPI0_SDI 2
> +#define SC_P_SPI0_SDI_M40_GPIO0_IO02 SC_P_SPI0_SDI 3
> +#define SC_P_SPI0_SDI_LSIO_GPIO1_IO05 SC_P_SPI0_SDI 4
> +#define SC_P_SPI0_SDO_ADMA_SPI0_SDO SC_P_SPI0_SDO 0
> +#define SC_P_SPI0_SDO_ADMA_SAI0_TXFS SC_P_SPI0_SDO 1
> +#define SC_P_SPI0_SDO_M40_I2C0_SDA SC_P_SPI0_SDO 2
> +#define SC_P_SPI0_SDO_M40_GPIO0_IO01 SC_P_SPI0_SDO 3
> +#define SC_P_SPI0_SDO_LSIO_GPIO1_IO06 SC_P_SPI0_SDO 4
> +#define SC_P_SPI0_CS1_ADMA_SPI0_CS1 SC_P_SPI0_CS1 0
> +#define SC_P_SPI0_CS1_ADMA_SAI0_RXC SC_P_SPI0_CS1 1
> +#define SC_P_SPI0_CS1_ADMA_SAI1_TXD SC_P_SPI0_CS1 2
> +#define SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT SC_P_SPI0_CS1 3
> +#define SC_P_SPI0_CS1_LSIO_GPIO1_IO07 SC_P_SPI0_CS1 4
> +#define SC_P_SPI0_CS0_ADMA_SPI0_CS0 SC_P_SPI0_CS0 0
> +#define SC_P_SPI0_CS0_ADMA_SAI0_RXD SC_P_SPI0_CS0 1
> +#define SC_P_SPI0_CS0_M40_TPM0_CH1 SC_P_SPI0_CS0 2
> +#define SC_P_SPI0_CS0_M40_GPIO0_IO03 SC_P_SPI0_CS0 3
> +#define SC_P_SPI0_CS0_LSIO_GPIO1_IO08 SC_P_SPI0_CS0 4
> +#define SC_P_ADC_IN1_ADMA_ADC_IN1 SC_P_ADC_IN1 0
> +#define SC_P_ADC_IN1_M40_I2C0_SDA SC_P_ADC_IN1 1
> +#define SC_P_ADC_IN1_M40_GPIO0_IO01 SC_P_ADC_IN1 2
> +#define SC_P_ADC_IN1_LSIO_GPIO1_IO09 SC_P_ADC_IN1 4
> +#define SC_P_ADC_IN0_ADMA_ADC_IN0 SC_P_ADC_IN0 0
> +#define SC_P_ADC_IN0_M40_I2C0_SCL SC_P_ADC_IN0 1
> +#define SC_P_ADC_IN0_M40_GPIO0_IO00 SC_P_ADC_IN0 2
> +#define SC_P_ADC_IN0_LSIO_GPIO1_IO10 SC_P_ADC_IN0 4
> +#define SC_P_ADC_IN3_ADMA_ADC_IN3 SC_P_ADC_IN3 0
> +#define SC_P_ADC_IN3_M40_UART0_TX SC_P_ADC_IN3 1
> +#define SC_P_ADC_IN3_M40_GPIO0_IO03 SC_P_ADC_IN3 2
> +#define SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0 SC_P_ADC_IN3 3
> +#define SC_P_ADC_IN3_LSIO_GPIO1_IO11 SC_P_ADC_IN3 4
> +#define SC_P_ADC_IN2_ADMA_ADC_IN2 SC_P_ADC_IN2 0
> +#define SC_P_ADC_IN2_M40_UART0_RX SC_P_ADC_IN2 1
> +#define SC_P_ADC_IN2_M40_GPIO0_IO02 SC_P_ADC_IN2 2
> +#define SC_P_ADC_IN2_ADMA_ACM_MCLK_IN0 SC_P_ADC_IN2 3
> +#define SC_P_ADC_IN2_LSIO_GPIO1_IO12 SC_P_ADC_IN2 4
> +#define SC_P_ADC_IN5_ADMA_ADC_IN5 SC_P_ADC_IN5 0
> +#define SC_P_ADC_IN5_M40_TPM0_CH1 SC_P_ADC_IN5 1
> +#define SC_P_ADC_IN5_M40_GPIO0_IO05 SC_P_ADC_IN5 2
> +#define SC_P_ADC_IN5_LSIO_GPIO1_IO13 SC_P_ADC_IN5 4
> +#define SC_P_ADC_IN4_ADMA_ADC_IN4 SC_P_ADC_IN4 0
> +#define SC_P_ADC_IN4_M40_TPM0_CH0 SC_P_ADC_IN4 1
> +#define SC_P_ADC_IN4_M40_GPIO0_IO04 SC_P_ADC_IN4 2
> +#define SC_P_ADC_IN4_LSIO_GPIO1_IO14 SC_P_ADC_IN4 4
> +#define SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX SC_P_FLEXCAN0_RX 0
> +#define SC_P_FLEXCAN0_RX_ADMA_SAI2_RXC SC_P_FLEXCAN0_RX 1
> +#define SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B SC_P_FLEXCAN0_RX 2
> +#define SC_P_FLEXCAN0_RX_ADMA_SAI1_TXC SC_P_FLEXCAN0_RX 3
> +#define SC_P_FLEXCAN0_RX_LSIO_GPIO1_IO15 SC_P_FLEXCAN0_RX 4
> +#define SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX SC_P_FLEXCAN0_TX 0
> +#define SC_P_FLEXCAN0_TX_ADMA_SAI2_RXD SC_P_FLEXCAN0_TX 1
> +#define SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B SC_P_FLEXCAN0_TX 2
> +#define SC_P_FLEXCAN0_TX_ADMA_SAI1_TXFS SC_P_FLEXCAN0_TX 3
> +#define SC_P_FLEXCAN0_TX_LSIO_GPIO1_IO16 SC_P_FLEXCAN0_TX 4
> +#define SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX SC_P_FLEXCAN1_RX 0
> +#define SC_P_FLEXCAN1_RX_ADMA_SAI2_RXFS SC_P_FLEXCAN1_RX 1
> +#define SC_P_FLEXCAN1_RX_ADMA_FTM_CH2 SC_P_FLEXCAN1_RX 2
> +#define SC_P_FLEXCAN1_RX_ADMA_SAI1_TXD SC_P_FLEXCAN1_RX 3
> +#define SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 SC_P_FLEXCAN1_RX 4
> +#define SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX SC_P_FLEXCAN1_TX 0
> +#define SC_P_FLEXCAN1_TX_ADMA_SAI3_RXC SC_P_FLEXCAN1_TX 1
> +#define SC_P_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 SC_P_FLEXCAN1_TX 2
> +#define SC_P_FLEXCAN1_TX_ADMA_SAI1_RXD SC_P_FLEXCAN1_TX 3
> +#define SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 SC_P_FLEXCAN1_TX 4
> +#define SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX SC_P_FLEXCAN2_RX 0
> +#define SC_P_FLEXCAN2_RX_ADMA_SAI3_RXD SC_P_FLEXCAN2_RX 1
> +#define SC_P_FLEXCAN2_RX_ADMA_UART3_RX SC_P_FLEXCAN2_RX 2
> +#define SC_P_FLEXCAN2_RX_ADMA_SAI1_RXFS SC_P_FLEXCAN2_RX 3
> +#define SC_P_FLEXCAN2_RX_LSIO_GPIO1_IO19 SC_P_FLEXCAN2_RX 4
> +#define SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX SC_P_FLEXCAN2_TX 0
> +#define SC_P_FLEXCAN2_TX_ADMA_SAI3_RXFS SC_P_FLEXCAN2_TX 1
> +#define SC_P_FLEXCAN2_TX_ADMA_UART3_TX SC_P_FLEXCAN2_TX 2
> +#define SC_P_FLEXCAN2_TX_ADMA_SAI1_RXC SC_P_FLEXCAN2_TX 3
> +#define SC_P_FLEXCAN2_TX_LSIO_GPIO1_IO20 SC_P_FLEXCAN2_TX 4
> +#define SC_P_UART0_RX_ADMA_UART0_RX SC_P_UART0_RX 0
> +#define SC_P_UART0_RX_ADMA_MQS_R SC_P_UART0_RX 1
> +#define SC_P_UART0_RX_ADMA_FLEXCAN0_RX SC_P_UART0_RX 2
> +#define SC_P_UART0_RX_LSIO_GPIO1_IO21 SC_P_UART0_RX 4
> +#define SC_P_UART0_TX_ADMA_UART0_TX SC_P_UART0_TX 0
> +#define SC_P_UART0_TX_ADMA_MQS_L SC_P_UART0_TX 1
> +#define SC_P_UART0_TX_ADMA_FLEXCAN0_TX SC_P_UART0_TX 2
> +#define SC_P_UART0_TX_LSIO_GPIO1_IO22 SC_P_UART0_TX 4
> +#define SC_P_UART2_TX_ADMA_UART2_TX SC_P_UART2_TX 0
> +#define SC_P_UART2_TX_ADMA_FTM_CH1 SC_P_UART2_TX 1
> +#define SC_P_UART2_TX_ADMA_FLEXCAN1_TX SC_P_UART2_TX 2
> +#define SC_P_UART2_TX_LSIO_GPIO1_IO23 SC_P_UART2_TX 4
> +#define SC_P_UART2_RX_ADMA_UART2_RX SC_P_UART2_RX 0
> +#define SC_P_UART2_RX_ADMA_FTM_CH0 SC_P_UART2_RX 1
> +#define SC_P_UART2_RX_ADMA_FLEXCAN1_RX SC_P_UART2_RX 2
> +#define SC_P_UART2_RX_LSIO_GPIO1_IO24 SC_P_UART2_RX 4
> +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL SC_P_MIPI_DSI0_I2C0_SCL 0
> +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02 SC_P_MIPI_DSI0_I2C0_SCL 1
> +#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 SC_P_MIPI_DSI0_I2C0_SCL 4
> +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA SC_P_MIPI_DSI0_I2C0_SDA 0
> +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03 SC_P_MIPI_DSI0_I2C0_SDA 1
> +#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 SC_P_MIPI_DSI0_I2C0_SDA 4
> +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 SC_P_MIPI_DSI0_GPIO0_00 0
> +#define SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL SC_P_MIPI_DSI0_GPIO0_00 1
> +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT SC_P_MIPI_DSI0_GPIO0_00 2
> +#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 SC_P_MIPI_DSI0_GPIO0_00 4
> +#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 SC_P_MIPI_DSI0_GPIO0_01 0
> +#define SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA SC_P_MIPI_DSI0_GPIO0_01 1
> +#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 SC_P_MIPI_DSI0_GPIO0_01 4
> +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL SC_P_MIPI_DSI1_I2C0_SCL 0
> +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02 SC_P_MIPI_DSI1_I2C0_SCL 1
> +#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29 SC_P_MIPI_DSI1_I2C0_SCL 4
> +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA SC_P_MIPI_DSI1_I2C0_SDA 0
> +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03 SC_P_MIPI_DSI1_I2C0_SDA 1
> +#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 SC_P_MIPI_DSI1_I2C0_SDA 4
> +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 SC_P_MIPI_DSI1_GPIO0_00 0
> +#define SC_P_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL SC_P_MIPI_DSI1_GPIO0_00 1
> +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT SC_P_MIPI_DSI1_GPIO0_00 2
> +#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 SC_P_MIPI_DSI1_GPIO0_00 4
> +#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 SC_P_MIPI_DSI1_GPIO0_01 0
> +#define SC_P_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA SC_P_MIPI_DSI1_GPIO0_01 1
> +#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 SC_P_MIPI_DSI1_GPIO0_01 4
> +#define SC_P_JTAG_TRST_B_SCU_JTAG_TRST_B SC_P_JTAG_TRST_B 0
> +#define SC_P_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT SC_P_JTAG_TRST_B 1
> +#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL SC_P_PMIC_I2C_SCL 0
> +#define SC_P_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON SC_P_PMIC_I2C_SCL 1
> +#define SC_P_PMIC_I2C_SCL_LSIO_GPIO2_IO01 SC_P_PMIC_I2C_SCL 4
> +#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA SC_P_PMIC_I2C_SDA 0
> +#define SC_P_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON SC_P_PMIC_I2C_SDA 1
> +#define SC_P_PMIC_I2C_SDA_LSIO_GPIO2_IO02 SC_P_PMIC_I2C_SDA 4
> +#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B SC_P_PMIC_INT_B 0
> +#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 SC_P_SCU_GPIO0_00 0
> +#define SC_P_SCU_GPIO0_00_SCU_UART0_RX SC_P_SCU_GPIO0_00 1
> +#define SC_P_SCU_GPIO0_00_M40_UART0_RX SC_P_SCU_GPIO0_00 2
> +#define SC_P_SCU_GPIO0_00_ADMA_UART3_RX SC_P_SCU_GPIO0_00 3
> +#define SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03 SC_P_SCU_GPIO0_00 4
> +#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 SC_P_SCU_GPIO0_01 0
> +#define SC_P_SCU_GPIO0_01_SCU_UART0_TX SC_P_SCU_GPIO0_01 1
> +#define SC_P_SCU_GPIO0_01_M40_UART0_TX SC_P_SCU_GPIO0_01 2
> +#define SC_P_SCU_GPIO0_01_ADMA_UART3_TX SC_P_SCU_GPIO0_01 3
> +#define SC_P_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT SC_P_SCU_GPIO0_01 4
> +#define SC_P_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY SC_P_SCU_PMIC_STANDBY 0
> +#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 SC_P_SCU_BOOT_MODE0 0
> +#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 SC_P_SCU_BOOT_MODE1 0
> +#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 SC_P_SCU_BOOT_MODE2 0
> +#define SC_P_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA SC_P_SCU_BOOT_MODE2 1
> +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 SC_P_SCU_BOOT_MODE3 0
> +#define SC_P_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL SC_P_SCU_BOOT_MODE3 1
> +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K SC_P_SCU_BOOT_MODE3 3
> +#define SC_P_CSI_D00_CI_PI_D02 SC_P_CSI_D00 0
> +#define SC_P_CSI_D00_ADMA_SAI0_RXC SC_P_CSI_D00 2
> +#define SC_P_CSI_D01_CI_PI_D03 SC_P_CSI_D01 0
> +#define SC_P_CSI_D01_ADMA_SAI0_RXD SC_P_CSI_D01 2
> +#define SC_P_CSI_D02_CI_PI_D04 SC_P_CSI_D02 0
> +#define SC_P_CSI_D02_ADMA_SAI0_RXFS SC_P_CSI_D02 2
> +#define SC_P_CSI_D03_CI_PI_D05 SC_P_CSI_D03 0
> +#define SC_P_CSI_D03_ADMA_SAI2_RXC SC_P_CSI_D03 2
> +#define SC_P_CSI_D04_CI_PI_D06 SC_P_CSI_D04 0
> +#define SC_P_CSI_D04_ADMA_SAI2_RXD SC_P_CSI_D04 2
> +#define SC_P_CSI_D05_CI_PI_D07 SC_P_CSI_D05 0
> +#define SC_P_CSI_D05_ADMA_SAI2_RXFS SC_P_CSI_D05 2
> +#define SC_P_CSI_D06_CI_PI_D08 SC_P_CSI_D06 0
> +#define SC_P_CSI_D06_ADMA_SAI3_RXC SC_P_CSI_D06 2
> +#define SC_P_CSI_D07_CI_PI_D09 SC_P_CSI_D07 0
> +#define SC_P_CSI_D07_ADMA_SAI3_RXD SC_P_CSI_D07 2
> +#define SC_P_CSI_HSYNC_CI_PI_HSYNC SC_P_CSI_HSYNC 0
> +#define SC_P_CSI_HSYNC_CI_PI_D00 SC_P_CSI_HSYNC 1
> +#define SC_P_CSI_HSYNC_ADMA_SAI3_RXFS SC_P_CSI_HSYNC 2
> +#define SC_P_CSI_VSYNC_CI_PI_VSYNC SC_P_CSI_VSYNC 0
> +#define SC_P_CSI_VSYNC_CI_PI_D01 SC_P_CSI_VSYNC 1
> +#define SC_P_CSI_PCLK_CI_PI_PCLK SC_P_CSI_PCLK 0
> +#define SC_P_CSI_PCLK_MIPI_CSI0_I2C0_SCL SC_P_CSI_PCLK 1
> +#define SC_P_CSI_PCLK_ADMA_SPI1_SCK SC_P_CSI_PCLK 3
> +#define SC_P_CSI_PCLK_LSIO_GPIO3_IO00 SC_P_CSI_PCLK 4
> +#define SC_P_CSI_MCLK_CI_PI_MCLK SC_P_CSI_MCLK 0
> +#define SC_P_CSI_MCLK_MIPI_CSI0_I2C0_SDA SC_P_CSI_MCLK 1
> +#define SC_P_CSI_MCLK_ADMA_SPI1_SDO SC_P_CSI_MCLK 3
> +#define SC_P_CSI_MCLK_LSIO_GPIO3_IO01 SC_P_CSI_MCLK 4
> +#define SC_P_CSI_EN_CI_PI_EN SC_P_CSI_EN 0
> +#define SC_P_CSI_EN_CI_PI_I2C_SCL SC_P_CSI_EN 1
> +#define SC_P_CSI_EN_ADMA_I2C3_SCL SC_P_CSI_EN 2
> +#define SC_P_CSI_EN_ADMA_SPI1_SDI SC_P_CSI_EN 3
> +#define SC_P_CSI_EN_LSIO_GPIO3_IO02 SC_P_CSI_EN 4
> +#define SC_P_CSI_RESET_CI_PI_RESET SC_P_CSI_RESET 0
> +#define SC_P_CSI_RESET_CI_PI_I2C_SDA SC_P_CSI_RESET 1
> +#define SC_P_CSI_RESET_ADMA_I2C3_SDA SC_P_CSI_RESET 2
> +#define SC_P_CSI_RESET_ADMA_SPI1_CS0 SC_P_CSI_RESET 3
> +#define SC_P_CSI_RESET_LSIO_GPIO3_IO03 SC_P_CSI_RESET 4
> +#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT SC_P_MIPI_CSI0_MCLK_OUT 0
> +#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 SC_P_MIPI_CSI0_MCLK_OUT 4
> +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL SC_P_MIPI_CSI0_I2C0_SCL 0
> +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02 SC_P_MIPI_CSI0_I2C0_SCL 1
> +#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 SC_P_MIPI_CSI0_I2C0_SCL 4
> +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA SC_P_MIPI_CSI0_I2C0_SDA 0
> +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03 SC_P_MIPI_CSI0_I2C0_SDA 1
> +#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 SC_P_MIPI_CSI0_I2C0_SDA 4
> +#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 SC_P_MIPI_CSI0_GPIO0_01 0
> +#define SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 1
> +#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 SC_P_MIPI_CSI0_GPIO0_01 4
> +#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 SC_P_MIPI_CSI0_GPIO0_00 0
> +#define SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 1
> +#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 SC_P_MIPI_CSI0_GPIO0_00 4
> +#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 SC_P_QSPI0A_DATA0 0
> +#define SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 SC_P_QSPI0A_DATA0 4
> +#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 SC_P_QSPI0A_DATA1 0
> +#define SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 SC_P_QSPI0A_DATA1 4
> +#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 SC_P_QSPI0A_DATA2 0
> +#define SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 SC_P_QSPI0A_DATA2 4
> +#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 SC_P_QSPI0A_DATA3 0
> +#define SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 SC_P_QSPI0A_DATA3 4
> +#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS SC_P_QSPI0A_DQS 0
> +#define SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 SC_P_QSPI0A_DQS 4
> +#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B SC_P_QSPI0A_SS0_B 0
> +#define SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 SC_P_QSPI0A_SS0_B 4
> +#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B SC_P_QSPI0A_SS1_B 0
> +#define SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 SC_P_QSPI0A_SS1_B 4
> +#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK SC_P_QSPI0A_SCLK 0
> +#define SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 SC_P_QSPI0A_SCLK 4
> +#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK SC_P_QSPI0B_SCLK 0
> +#define SC_P_QSPI0B_SCLK_LSIO_QSPI1A_SCLK SC_P_QSPI0B_SCLK 1
> +#define SC_P_QSPI0B_SCLK_LSIO_KPP0_COL0 SC_P_QSPI0B_SCLK 2
> +#define SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 SC_P_QSPI0B_SCLK 4
> +#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 SC_P_QSPI0B_DATA0 0
> +#define SC_P_QSPI0B_DATA0_LSIO_QSPI1A_DATA0 SC_P_QSPI0B_DATA0 1
> +#define SC_P_QSPI0B_DATA0_LSIO_KPP0_COL1 SC_P_QSPI0B_DATA0 2
> +#define SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 SC_P_QSPI0B_DATA0 4
> +#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 SC_P_QSPI0B_DATA1 0
> +#define SC_P_QSPI0B_DATA1_LSIO_QSPI1A_DATA1 SC_P_QSPI0B_DATA1 1
> +#define SC_P_QSPI0B_DATA1_LSIO_KPP0_COL2 SC_P_QSPI0B_DATA1 2
> +#define SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 SC_P_QSPI0B_DATA1 4
> +#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 SC_P_QSPI0B_DATA2 0
> +#define SC_P_QSPI0B_DATA2_LSIO_QSPI1A_DATA2 SC_P_QSPI0B_DATA2 1
> +#define SC_P_QSPI0B_DATA2_LSIO_KPP0_COL3 SC_P_QSPI0B_DATA2 2
> +#define SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 SC_P_QSPI0B_DATA2 4
> +#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 SC_P_QSPI0B_DATA3 0
> +#define SC_P_QSPI0B_DATA3_LSIO_QSPI1A_DATA3 SC_P_QSPI0B_DATA3 1
> +#define SC_P_QSPI0B_DATA3_LSIO_KPP0_ROW0 SC_P_QSPI0B_DATA3 2
> +#define SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 SC_P_QSPI0B_DATA3 4
> +#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS SC_P_QSPI0B_DQS 0
> +#define SC_P_QSPI0B_DQS_LSIO_QSPI1A_DQS SC_P_QSPI0B_DQS 1
> +#define SC_P_QSPI0B_DQS_LSIO_KPP0_ROW1 SC_P_QSPI0B_DQS 2
> +#define SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 SC_P_QSPI0B_DQS 4
> +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B SC_P_QSPI0B_SS0_B 0
> +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B SC_P_QSPI0B_SS0_B 1
> +#define SC_P_QSPI0B_SS0_B_LSIO_KPP0_ROW2 SC_P_QSPI0B_SS0_B 2
> +#define SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 SC_P_QSPI0B_SS0_B 4
> +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B SC_P_QSPI0B_SS1_B 0
> +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B SC_P_QSPI0B_SS1_B 1
> +#define SC_P_QSPI0B_SS1_B_LSIO_KPP0_ROW3 SC_P_QSPI0B_SS1_B 2
> +#define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 SC_P_QSPI0B_SS1_B 4
> +
> +#endif /* _SC_PADS_H */
> --
> 2.7.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 1/6] pinctrl: imx: fix unsigned check if nfuncs with less than or equal zero
2018-04-27 19:01 ` Dong Aisheng
@ 2018-05-02 12:22 ` Linus Walleij
-1 siblings, 0 replies; 36+ messages in thread
From: Linus Walleij @ 2018-05-02 12:22 UTC (permalink / raw)
To: Dong Aisheng
Cc: Dong Aisheng, Stefan Agner, open list:GPIO SUBSYSTEM,
NXP Linux Team, Sascha Hauer, Fabio Estevam, Shawn Guo,
Linux ARM
On Fri, Apr 27, 2018 at 9:01 PM, Dong Aisheng <aisheng.dong@nxp.com> wrote:
> The unsigned integer nfuncs is being error checked with a value less
> or equal to zero; this is always false if of_get_child_count returns a
> -ve for an error condition since nfuncs is not signed. Fix this by
> making variables nfuncs and i signed integers.
>
> Detected with Coccinelle:
> drivers/pinctrl/freescale/pinctrl-imx.c:620:6-12: WARNING: Unsigned
> expression compared with zero: nfuncs <= 0
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Reported-by: Colin Ian King <colin.king@canonical.com>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 1/6] pinctrl: imx: fix unsigned check if nfuncs with less than or equal zero
@ 2018-05-02 12:22 ` Linus Walleij
0 siblings, 0 replies; 36+ messages in thread
From: Linus Walleij @ 2018-05-02 12:22 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Apr 27, 2018 at 9:01 PM, Dong Aisheng <aisheng.dong@nxp.com> wrote:
> The unsigned integer nfuncs is being error checked with a value less
> or equal to zero; this is always false if of_get_child_count returns a
> -ve for an error condition since nfuncs is not signed. Fix this by
> making variables nfuncs and i signed integers.
>
> Detected with Coccinelle:
> drivers/pinctrl/freescale/pinctrl-imx.c:620:6-12: WARNING: Unsigned
> expression compared with zero: nfuncs <= 0
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Reported-by: Colin Ian King <colin.king@canonical.com>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 2/6] pinctrl: pinctrl-imx: improve the code comments of PIN_FUNC_ID
2018-04-27 19:01 ` Dong Aisheng
@ 2018-05-02 12:23 ` Linus Walleij
-1 siblings, 0 replies; 36+ messages in thread
From: Linus Walleij @ 2018-05-02 12:23 UTC (permalink / raw)
To: Dong Aisheng
Cc: Dong Aisheng, Fabio Estevam, Stefan Agner,
open list:GPIO SUBSYSTEM, NXP Linux Team, Sascha Hauer,
Fabio Estevam, Shawn Guo, Linux ARM
On Fri, Apr 27, 2018 at 9:01 PM, Dong Aisheng <aisheng.dong@nxp.com> wrote:
> The current code comments of PIN_FUNC_ID actually is not true for
> SHARE_MUX_CONF_REG case which should be a 4 u32 PIN_FUNC_ID.
> Fix the comments and re-org it a bit for better extendibility
> as we may add a different size for SCU based PIN_FUNC_ID later.
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 2/6] pinctrl: pinctrl-imx: improve the code comments of PIN_FUNC_ID
@ 2018-05-02 12:23 ` Linus Walleij
0 siblings, 0 replies; 36+ messages in thread
From: Linus Walleij @ 2018-05-02 12:23 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Apr 27, 2018 at 9:01 PM, Dong Aisheng <aisheng.dong@nxp.com> wrote:
> The current code comments of PIN_FUNC_ID actually is not true for
> SHARE_MUX_CONF_REG case which should be a 4 u32 PIN_FUNC_ID.
> Fix the comments and re-org it a bit for better extendibility
> as we may add a different size for SCU based PIN_FUNC_ID later.
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 3/6] pinctrl: imx: use seq_puts() instead of seq_printf()
2018-04-27 19:01 ` Dong Aisheng
@ 2018-05-02 12:24 ` Linus Walleij
-1 siblings, 0 replies; 36+ messages in thread
From: Linus Walleij @ 2018-05-02 12:24 UTC (permalink / raw)
To: Dong Aisheng
Cc: Dong Aisheng, Fabio Estevam, Stefan Agner,
open list:GPIO SUBSYSTEM, NXP Linux Team, Sascha Hauer,
Fabio Estevam, Shawn Guo, Linux ARM
On Fri, Apr 27, 2018 at 9:01 PM, Dong Aisheng <aisheng.dong@nxp.com> wrote:
> For a constant format without additional arguments, use seq_puts()
> instead of seq_printf(). Also, it fixes the following checkpatch
> warning.
>
> WARNING: Prefer seq_puts to seq_printf
> + seq_printf(s, "N/A");
>
> WARNING: Prefer seq_puts to seq_printf
> + seq_printf(s, "\n");
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 3/6] pinctrl: imx: use seq_puts() instead of seq_printf()
@ 2018-05-02 12:24 ` Linus Walleij
0 siblings, 0 replies; 36+ messages in thread
From: Linus Walleij @ 2018-05-02 12:24 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Apr 27, 2018 at 9:01 PM, Dong Aisheng <aisheng.dong@nxp.com> wrote:
> For a constant format without additional arguments, use seq_puts()
> instead of seq_printf(). Also, it fixes the following checkpatch
> warning.
>
> WARNING: Prefer seq_puts to seq_printf
> + seq_printf(s, "N/A");
>
> WARNING: Prefer seq_puts to seq_printf
> + seq_printf(s, "\n");
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 4/6] pinctrl: fsl: add scu based pinctrl support
2018-04-27 19:01 ` Dong Aisheng
@ 2018-05-02 12:27 ` Linus Walleij
-1 siblings, 0 replies; 36+ messages in thread
From: Linus Walleij @ 2018-05-02 12:27 UTC (permalink / raw)
To: Dong Aisheng
Cc: Dong Aisheng, Fabio Estevam, Stefan Agner,
open list:GPIO SUBSYSTEM, NXP Linux Team, Sascha Hauer,
Fabio Estevam, Shawn Guo, Linux ARM
On Fri, Apr 27, 2018 at 9:01 PM, Dong Aisheng <aisheng.dong@nxp.com> wrote:
> Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller
> that is responsible for controlling the pad setting of the IPs that
> are present. Communication between the host processor running an OS
> and the system controller happens through a SCU protocol.
> This patch adds SCU protocol based pinctrl drivers.
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Patch applied.
There was some controversy about i.MX pin control some time
back so I hope there is no annoyance from the other maintainers
that I just merge stuff from one maintainer.
If you don't like the patches you can always tell me to drop
them.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 4/6] pinctrl: fsl: add scu based pinctrl support
@ 2018-05-02 12:27 ` Linus Walleij
0 siblings, 0 replies; 36+ messages in thread
From: Linus Walleij @ 2018-05-02 12:27 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Apr 27, 2018 at 9:01 PM, Dong Aisheng <aisheng.dong@nxp.com> wrote:
> Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller
> that is responsible for controlling the pad setting of the IPs that
> are present. Communication between the host processor running an OS
> and the system controller happens through a SCU protocol.
> This patch adds SCU protocol based pinctrl drivers.
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Patch applied.
There was some controversy about i.MX pin control some time
back so I hope there is no annoyance from the other maintainers
that I just merge stuff from one maintainer.
If you don't like the patches you can always tell me to drop
them.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 4/6] pinctrl: fsl: add scu based pinctrl support
2018-05-02 12:27 ` Linus Walleij
@ 2018-05-02 12:29 ` Linus Walleij
-1 siblings, 0 replies; 36+ messages in thread
From: Linus Walleij @ 2018-05-02 12:29 UTC (permalink / raw)
To: Dong Aisheng
Cc: Dong Aisheng, Fabio Estevam, Stefan Agner,
open list:GPIO SUBSYSTEM, NXP Linux Team, Sascha Hauer,
Fabio Estevam, Shawn Guo, Linux ARM
On Wed, May 2, 2018 at 2:27 PM, Linus Walleij <linus.walleij@linaro.org> wrote:
> On Fri, Apr 27, 2018 at 9:01 PM, Dong Aisheng <aisheng.dong@nxp.com> wrote:
>
>> Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller
>> that is responsible for controlling the pad setting of the IPs that
>> are present. Communication between the host processor running an OS
>> and the system controller happens through a SCU protocol.
>> This patch adds SCU protocol based pinctrl drivers.
>>
>> Cc: Linus Walleij <linus.walleij@linaro.org>
>> Cc: Shawn Guo <shawnguo@kernel.org>
>> Cc: Fabio Estevam <festevam@gmail.com>
>> Cc: Stefan Agner <stefan@agner.ch>
>> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
>> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
>
> Patch applied.
Bah on second thought holding this back since I see thyere are
some discussions about the bindings in the next patch.
Anyway, it's nice if the other maintainers would like to get involved.
Dong: you only need to resend patches 4.5.6 next time.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 4/6] pinctrl: fsl: add scu based pinctrl support
@ 2018-05-02 12:29 ` Linus Walleij
0 siblings, 0 replies; 36+ messages in thread
From: Linus Walleij @ 2018-05-02 12:29 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, May 2, 2018 at 2:27 PM, Linus Walleij <linus.walleij@linaro.org> wrote:
> On Fri, Apr 27, 2018 at 9:01 PM, Dong Aisheng <aisheng.dong@nxp.com> wrote:
>
>> Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller
>> that is responsible for controlling the pad setting of the IPs that
>> are present. Communication between the host processor running an OS
>> and the system controller happens through a SCU protocol.
>> This patch adds SCU protocol based pinctrl drivers.
>>
>> Cc: Linus Walleij <linus.walleij@linaro.org>
>> Cc: Shawn Guo <shawnguo@kernel.org>
>> Cc: Fabio Estevam <festevam@gmail.com>
>> Cc: Stefan Agner <stefan@agner.ch>
>> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
>> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
>
> Patch applied.
Bah on second thought holding this back since I see thyere are
some discussions about the bindings in the next patch.
Anyway, it's nice if the other maintainers would like to get involved.
Dong: you only need to resend patches 4.5.6 next time.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 4/6] pinctrl: fsl: add scu based pinctrl support
2018-05-02 12:29 ` Linus Walleij
@ 2018-05-02 12:36 ` Sascha Hauer
-1 siblings, 0 replies; 36+ messages in thread
From: Sascha Hauer @ 2018-05-02 12:36 UTC (permalink / raw)
To: Linus Walleij
Cc: Dong Aisheng, Dong Aisheng, Shawn Guo, Stefan Agner,
open list:GPIO SUBSYSTEM, NXP Linux Team, Sascha Hauer,
Fabio Estevam, Fabio Estevam, Linux ARM
Hi Linus,
On Wed, May 02, 2018 at 02:29:04PM +0200, Linus Walleij wrote:
> On Wed, May 2, 2018 at 2:27 PM, Linus Walleij <linus.walleij@linaro.org> wrote:
> > On Fri, Apr 27, 2018 at 9:01 PM, Dong Aisheng <aisheng.dong@nxp.com> wrote:
> >
> >> Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller
> >> that is responsible for controlling the pad setting of the IPs that
> >> are present. Communication between the host processor running an OS
> >> and the system controller happens through a SCU protocol.
> >> This patch adds SCU protocol based pinctrl drivers.
> >>
> >> Cc: Linus Walleij <linus.walleij@linaro.org>
> >> Cc: Shawn Guo <shawnguo@kernel.org>
> >> Cc: Fabio Estevam <festevam@gmail.com>
> >> Cc: Stefan Agner <stefan@agner.ch>
> >> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> >> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> >
> > Patch applied.
>
> Bah on second thought holding this back since I see thyere are
> some discussions about the bindings in the next patch.
Also note that this patch depends on the SCU base support posted elsewhere
as Dong mentioned in his introductory mail.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 4/6] pinctrl: fsl: add scu based pinctrl support
@ 2018-05-02 12:36 ` Sascha Hauer
0 siblings, 0 replies; 36+ messages in thread
From: Sascha Hauer @ 2018-05-02 12:36 UTC (permalink / raw)
To: linux-arm-kernel
Hi Linus,
On Wed, May 02, 2018 at 02:29:04PM +0200, Linus Walleij wrote:
> On Wed, May 2, 2018 at 2:27 PM, Linus Walleij <linus.walleij@linaro.org> wrote:
> > On Fri, Apr 27, 2018 at 9:01 PM, Dong Aisheng <aisheng.dong@nxp.com> wrote:
> >
> >> Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller
> >> that is responsible for controlling the pad setting of the IPs that
> >> are present. Communication between the host processor running an OS
> >> and the system controller happens through a SCU protocol.
> >> This patch adds SCU protocol based pinctrl drivers.
> >>
> >> Cc: Linus Walleij <linus.walleij@linaro.org>
> >> Cc: Shawn Guo <shawnguo@kernel.org>
> >> Cc: Fabio Estevam <festevam@gmail.com>
> >> Cc: Stefan Agner <stefan@agner.ch>
> >> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> >> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> >
> > Patch applied.
>
> Bah on second thought holding this back since I see thyere are
> some discussions about the bindings in the next patch.
Also note that this patch depends on the SCU base support posted elsewhere
as Dong mentioned in his introductory mail.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 4/6] pinctrl: fsl: add scu based pinctrl support
2018-05-02 12:36 ` Sascha Hauer
@ 2018-05-02 13:03 ` Linus Walleij
-1 siblings, 0 replies; 36+ messages in thread
From: Linus Walleij @ 2018-05-02 13:03 UTC (permalink / raw)
To: Sascha Hauer
Cc: Dong Aisheng, Dong Aisheng, Shawn Guo, Stefan Agner,
open list:GPIO SUBSYSTEM, NXP Linux Team, Sascha Hauer,
Fabio Estevam, Fabio Estevam, Linux ARM
On Wed, May 2, 2018 at 2:36 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> Hi Linus,
>
> On Wed, May 02, 2018 at 02:29:04PM +0200, Linus Walleij wrote:
>> On Wed, May 2, 2018 at 2:27 PM, Linus Walleij <linus.walleij@linaro.org> wrote:
>> > On Fri, Apr 27, 2018 at 9:01 PM, Dong Aisheng <aisheng.dong@nxp.com> wrote:
>> >
>> >> Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller
>> >> that is responsible for controlling the pad setting of the IPs that
>> >> are present. Communication between the host processor running an OS
>> >> and the system controller happens through a SCU protocol.
>> >> This patch adds SCU protocol based pinctrl drivers.
>> >>
>> >> Cc: Linus Walleij <linus.walleij@linaro.org>
>> >> Cc: Shawn Guo <shawnguo@kernel.org>
>> >> Cc: Fabio Estevam <festevam@gmail.com>
>> >> Cc: Stefan Agner <stefan@agner.ch>
>> >> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
>> >> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
>> >
>> > Patch applied.
>>
>> Bah on second thought holding this back since I see thyere are
>> some discussions about the bindings in the next patch.
>
> Also note that this patch depends on the SCU base support posted elsewhere
> as Dong mentioned in his introductory mail.
Aha is that a compile-time dependence?
I guess it would be better if it is one big series if it is supposed
to be merged in one big series.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 4/6] pinctrl: fsl: add scu based pinctrl support
@ 2018-05-02 13:03 ` Linus Walleij
0 siblings, 0 replies; 36+ messages in thread
From: Linus Walleij @ 2018-05-02 13:03 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, May 2, 2018 at 2:36 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> Hi Linus,
>
> On Wed, May 02, 2018 at 02:29:04PM +0200, Linus Walleij wrote:
>> On Wed, May 2, 2018 at 2:27 PM, Linus Walleij <linus.walleij@linaro.org> wrote:
>> > On Fri, Apr 27, 2018 at 9:01 PM, Dong Aisheng <aisheng.dong@nxp.com> wrote:
>> >
>> >> Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller
>> >> that is responsible for controlling the pad setting of the IPs that
>> >> are present. Communication between the host processor running an OS
>> >> and the system controller happens through a SCU protocol.
>> >> This patch adds SCU protocol based pinctrl drivers.
>> >>
>> >> Cc: Linus Walleij <linus.walleij@linaro.org>
>> >> Cc: Shawn Guo <shawnguo@kernel.org>
>> >> Cc: Fabio Estevam <festevam@gmail.com>
>> >> Cc: Stefan Agner <stefan@agner.ch>
>> >> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
>> >> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
>> >
>> > Patch applied.
>>
>> Bah on second thought holding this back since I see thyere are
>> some discussions about the bindings in the next patch.
>
> Also note that this patch depends on the SCU base support posted elsewhere
> as Dong mentioned in his introductory mail.
Aha is that a compile-time dependence?
I guess it would be better if it is one big series if it is supposed
to be merged in one big series.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH 4/6] pinctrl: fsl: add scu based pinctrl support
2018-05-02 13:03 ` Linus Walleij
@ 2018-05-02 15:05 ` Sascha Hauer
-1 siblings, 0 replies; 36+ messages in thread
From: Sascha Hauer @ 2018-05-02 15:05 UTC (permalink / raw)
To: Linus Walleij
Cc: Dong Aisheng, Dong Aisheng, Shawn Guo, Stefan Agner,
open list:GPIO SUBSYSTEM, NXP Linux Team, Sascha Hauer,
Fabio Estevam, Fabio Estevam, Linux ARM
On Wed, May 02, 2018 at 03:03:04PM +0200, Linus Walleij wrote:
> On Wed, May 2, 2018 at 2:36 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > Hi Linus,
> >
> > On Wed, May 02, 2018 at 02:29:04PM +0200, Linus Walleij wrote:
> >> On Wed, May 2, 2018 at 2:27 PM, Linus Walleij <linus.walleij@linaro.org> wrote:
> >> > On Fri, Apr 27, 2018 at 9:01 PM, Dong Aisheng <aisheng.dong@nxp.com> wrote:
> >> >
> >> >> Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller
> >> >> that is responsible for controlling the pad setting of the IPs that
> >> >> are present. Communication between the host processor running an OS
> >> >> and the system controller happens through a SCU protocol.
> >> >> This patch adds SCU protocol based pinctrl drivers.
> >> >>
> >> >> Cc: Linus Walleij <linus.walleij@linaro.org>
> >> >> Cc: Shawn Guo <shawnguo@kernel.org>
> >> >> Cc: Fabio Estevam <festevam@gmail.com>
> >> >> Cc: Stefan Agner <stefan@agner.ch>
> >> >> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> >> >> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> >> >
> >> > Patch applied.
> >>
> >> Bah on second thought holding this back since I see thyere are
> >> some discussions about the bindings in the next patch.
> >
> > Also note that this patch depends on the SCU base support posted elsewhere
> > as Dong mentioned in his introductory mail.
>
> Aha is that a compile-time dependence?
Yes.
>
> I guess it would be better if it is one big series if it is supposed
> to be merged in one big series.
The SCU is a coprocessor that provides pinctrl, clk, power domain and
other misc stuff, so posting this as multiple series should be the way
to go.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 4/6] pinctrl: fsl: add scu based pinctrl support
@ 2018-05-02 15:05 ` Sascha Hauer
0 siblings, 0 replies; 36+ messages in thread
From: Sascha Hauer @ 2018-05-02 15:05 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, May 02, 2018 at 03:03:04PM +0200, Linus Walleij wrote:
> On Wed, May 2, 2018 at 2:36 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > Hi Linus,
> >
> > On Wed, May 02, 2018 at 02:29:04PM +0200, Linus Walleij wrote:
> >> On Wed, May 2, 2018 at 2:27 PM, Linus Walleij <linus.walleij@linaro.org> wrote:
> >> > On Fri, Apr 27, 2018 at 9:01 PM, Dong Aisheng <aisheng.dong@nxp.com> wrote:
> >> >
> >> >> Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller
> >> >> that is responsible for controlling the pad setting of the IPs that
> >> >> are present. Communication between the host processor running an OS
> >> >> and the system controller happens through a SCU protocol.
> >> >> This patch adds SCU protocol based pinctrl drivers.
> >> >>
> >> >> Cc: Linus Walleij <linus.walleij@linaro.org>
> >> >> Cc: Shawn Guo <shawnguo@kernel.org>
> >> >> Cc: Fabio Estevam <festevam@gmail.com>
> >> >> Cc: Stefan Agner <stefan@agner.ch>
> >> >> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> >> >> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> >> >
> >> > Patch applied.
> >>
> >> Bah on second thought holding this back since I see thyere are
> >> some discussions about the bindings in the next patch.
> >
> > Also note that this patch depends on the SCU base support posted elsewhere
> > as Dong mentioned in his introductory mail.
>
> Aha is that a compile-time dependence?
Yes.
>
> I guess it would be better if it is one big series if it is supposed
> to be merged in one big series.
The SCU is a coprocessor that provides pinctrl, clk, power domain and
other misc stuff, so posting this as multiple series should be the way
to go.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 36+ messages in thread
* RE: [PATCH 5/6] dt-bindings: pinctrl: add imx8qxp pinctrl binding doc
2018-05-01 15:58 ` Rob Herring
@ 2018-05-02 18:07 ` A.s. Dong
-1 siblings, 0 replies; 36+ messages in thread
From: A.s. Dong @ 2018-05-02 18:07 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, devicetree, dongas86, Fabio Estevam, linus.walleij,
stefan, linux-gpio, dl-linux-imx, kernel, Fabio Estevam,
shawnguo, linux-arm-kernel
> -----Original Message-----
> From: Rob Herring [mailto:robh@kernel.org]
> Sent: Tuesday, May 1, 2018 11:58 PM
> To: A.s. Dong <aisheng.dong@nxp.com>
> Cc: linux-gpio@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linus.walleij@linaro.org; shawnguo@kernel.org; stefan@agner.ch;
> dongas86@gmail.com; dl-linux-imx <linux-imx@nxp.com>;
> kernel@pengutronix.de; Fabio Estevam <fabio.estevam@nxp.com>; Mark
> Rutland <mark.rutland@arm.com>; devicetree@vger.kernel.org; Fabio
> Estevam <festevam@gmail.com>
> Subject: Re: [PATCH 5/6] dt-bindings: pinctrl: add imx8qxp pinctrl binding doc
>
> On Sat, Apr 28, 2018 at 03:01:52AM +0800, Dong Aisheng wrote:
> > Add imx8qxp pinctrl binding doc.
> >
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: Mark Rutland <mark.rutland@arm.com>
> > Cc: devicetree@vger.kernel.org
> > Cc: Linus Walleij <linus.walleij@linaro.org>
> > Cc: Shawn Guo <shawnguo@kernel.org>
> > Cc: Fabio Estevam <festevam@gmail.com>
> > Cc: Stefan Agner <stefan@agner.ch>
> > Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> > ---
> > Note: there's a checkpatch error as follows:
> > ERROR: Macros with complex values should be enclosed in parentheses
> > +#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B
> SC_P_PCIE_CTRL0_PERST_B 0
> >
> > However, this is the intended format. Seems checkpatch did not recognize
> > it well. Not sure if we could accept it.
> > ---
> > .../bindings/pinctrl/fsl,imx8qxp-pinctrl.txt | 39 ++
> > include/dt-bindings/pinctrl/pads-imx8qxp.h | 751
> +++++++++++++++++++++
> > 2 files changed, 790 insertions(+)
> > create mode 100644
> Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt
> > create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h
> >
> > diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-
> pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-
> pinctrl.txt
> > new file mode 100644
> > index 0000000..62c0f55
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt
> > @@ -0,0 +1,39 @@
> > +* NXP i.MX8QXP IOMUX Controller
> > +
> > +MX8QXP contains a system controller that is responsible for controlling
> > +the pad setting of the IPs that are present. Communication between the
> > +host processor running an OS and the system controller happens through
> > +a SCU protocol.
> > +
> > +Please also refer to fsl,imx-pinctrl.txt in this directory for i.MX common
> > +pinctrl binding.
> > +
> > +=== Pin Controller Node ===
> > +
> > +Required properties:
> > +- compatible: "fsl,imx8qxp-iomuxc"
>
> How is this block accessed?
>
> I see the answer in the dts is the SCU. Is this really a IOMUXC as
> defined by prior i.MX chips if it is hidden behind firmware?
>
Yes, it's just controlled by SCU firmware now and accessed via
SCU firmware call (API).
> > +
> > +=== Pin Configuration Node ===
> > +- fsl,pins: Each entry consists of 3 integers which represents the mux
> and
> > + config setting for one pin. The first 2 integers <pin_id
> mux_mode>
> > + are specified using a PIN_FUNC_ID macro, which can be
> found
> > + in <dt-bindings/pinctrl/pads-imx8qxp.h>. The last integer
> CONFIG
> > + is the pad setting value like pull-up on this pin.
> > + Please refer to i.MX8QXP Reference Manual for detailed
> > + CONFIG settings.
> > +
> > +Examples:
> > +#include <dt-bindings/pinctrl/pads-imx8qxp.h>
> > +
> > +/* Pin Controller Node */
> > +iomuxc: iomuxc {
>
> pinctrl {
>
Yes.
> > + compatible = "fsl,imx8qxp-iomuxc";
> > +
> > + /* Pin Configuration Node */
> > + pinctrl_lpuart0: lpuart0grp {
> > + fsl,pins = <
> > + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
> > + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
> > + >;
> > + };
> > +};
> > diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-
> bindings/pinctrl/pads-imx8qxp.h
> > new file mode 100644
> > index 0000000..8f477c3
> > --- /dev/null
> > +++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h
> > @@ -0,0 +1,751 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> > + * Copyright 2017~2018 NXP
> > + */
> > +
> > +#ifndef _SC_PADS_H
> > +#define _SC_PADS_H
> > +
> > +/* pin id */
> > +#define SC_P_PCIE_CTRL0_PERST_B 0
> > +#define SC_P_PCIE_CTRL0_CLKREQ_B 1
> > +#define SC_P_PCIE_CTRL0_WAKE_B 2
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3
> > +#define SC_P_USB_SS3_TC0 4
> > +#define SC_P_USB_SS3_TC1 5
> > +#define SC_P_USB_SS3_TC2 6
> > +#define SC_P_USB_SS3_TC3 7
> > +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8
> > +#define SC_P_EMMC0_CLK 9
> > +#define SC_P_EMMC0_CMD 10
> > +#define SC_P_EMMC0_DATA0 11
> > +#define SC_P_EMMC0_DATA1 12
> > +#define SC_P_EMMC0_DATA2 13
> > +#define SC_P_EMMC0_DATA3 14
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15
> > +#define SC_P_EMMC0_DATA4 16
> > +#define SC_P_EMMC0_DATA5 17
> > +#define SC_P_EMMC0_DATA6 18
> > +#define SC_P_EMMC0_DATA7 19
> > +#define SC_P_EMMC0_STROBE 20
> > +#define SC_P_EMMC0_RESET_B 21
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22
> > +#define SC_P_USDHC1_RESET_B 23
> > +#define SC_P_USDHC1_VSELECT 24
> > +#define SC_P_CTL_NAND_RE_P_N 25
> > +#define SC_P_USDHC1_WP 26
> > +#define SC_P_USDHC1_CD_B 27
> > +#define SC_P_CTL_NAND_DQS_P_N 28
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29
> > +#define SC_P_USDHC1_CLK 30
> > +#define SC_P_USDHC1_CMD 31
> > +#define SC_P_USDHC1_DATA0 32
> > +#define SC_P_USDHC1_DATA1 33
> > +#define SC_P_USDHC1_DATA2 34
> > +#define SC_P_USDHC1_DATA3 35
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36
> > +#define SC_P_ENET0_RGMII_TXC 37
> > +#define SC_P_ENET0_RGMII_TX_CTL 38
> > +#define SC_P_ENET0_RGMII_TXD0 39
> > +#define SC_P_ENET0_RGMII_TXD1 40
> > +#define SC_P_ENET0_RGMII_TXD2 41
> > +#define SC_P_ENET0_RGMII_TXD3 42
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43
> > +#define SC_P_ENET0_RGMII_RXC 44
> > +#define SC_P_ENET0_RGMII_RX_CTL 45
> > +#define SC_P_ENET0_RGMII_RXD0 46
> > +#define SC_P_ENET0_RGMII_RXD1 47
> > +#define SC_P_ENET0_RGMII_RXD2 48
> > +#define SC_P_ENET0_RGMII_RXD3 49
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50
> > +#define SC_P_ENET0_REFCLK_125M_25M 51
> > +#define SC_P_ENET0_MDIO 52
> > +#define SC_P_ENET0_MDC 53
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54
> > +#define SC_P_ESAI0_FSR 55
> > +#define SC_P_ESAI0_FST 56
> > +#define SC_P_ESAI0_SCKR 57
> > +#define SC_P_ESAI0_SCKT 58
> > +#define SC_P_ESAI0_TX0 59
> > +#define SC_P_ESAI0_TX1 60
> > +#define SC_P_ESAI0_TX2_RX3 61
> > +#define SC_P_ESAI0_TX3_RX2 62
> > +#define SC_P_ESAI0_TX4_RX1 63
> > +#define SC_P_ESAI0_TX5_RX0 64
> > +#define SC_P_SPDIF0_RX 65
> > +#define SC_P_SPDIF0_TX 66
> > +#define SC_P_SPDIF0_EXT_CLK 67
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68
> > +#define SC_P_SPI3_SCK 69
> > +#define SC_P_SPI3_SDO 70
> > +#define SC_P_SPI3_SDI 71
> > +#define SC_P_SPI3_CS0 72
> > +#define SC_P_SPI3_CS1 73
> > +#define SC_P_MCLK_IN1 74
> > +#define SC_P_MCLK_IN0 75
> > +#define SC_P_MCLK_OUT0 76
> > +#define SC_P_UART1_TX 77
> > +#define SC_P_UART1_RX 78
> > +#define SC_P_UART1_RTS_B 79
> > +#define SC_P_UART1_CTS_B 80
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81
> > +#define SC_P_SAI0_TXD 82
> > +#define SC_P_SAI0_TXC 83
> > +#define SC_P_SAI0_RXD 84
> > +#define SC_P_SAI0_TXFS 85
> > +#define SC_P_SAI1_RXD 86
> > +#define SC_P_SAI1_RXC 87
> > +#define SC_P_SAI1_RXFS 88
> > +#define SC_P_SPI2_CS0 89
> > +#define SC_P_SPI2_SDO 90
> > +#define SC_P_SPI2_SDI 91
> > +#define SC_P_SPI2_SCK 92
> > +#define SC_P_SPI0_SCK 93
> > +#define SC_P_SPI0_SDI 94
> > +#define SC_P_SPI0_SDO 95
> > +#define SC_P_SPI0_CS1 96
> > +#define SC_P_SPI0_CS0 97
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98
> > +#define SC_P_ADC_IN1 99
> > +#define SC_P_ADC_IN0 100
> > +#define SC_P_ADC_IN3 101
> > +#define SC_P_ADC_IN2 102
> > +#define SC_P_ADC_IN5 103
> > +#define SC_P_ADC_IN4 104
> > +#define SC_P_FLEXCAN0_RX 105
> > +#define SC_P_FLEXCAN0_TX 106
> > +#define SC_P_FLEXCAN1_RX 107
> > +#define SC_P_FLEXCAN1_TX 108
> > +#define SC_P_FLEXCAN2_RX 109
> > +#define SC_P_FLEXCAN2_TX 110
> > +#define SC_P_UART0_RX 111
> > +#define SC_P_UART0_TX 112
> > +#define SC_P_UART2_TX 113
> > +#define SC_P_UART2_RX 114
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115
> > +#define SC_P_MIPI_DSI0_I2C0_SCL 116
> > +#define SC_P_MIPI_DSI0_I2C0_SDA 117
> > +#define SC_P_MIPI_DSI0_GPIO0_00 118
> > +#define SC_P_MIPI_DSI0_GPIO0_01 119
> > +#define SC_P_MIPI_DSI1_I2C0_SCL 120
> > +#define SC_P_MIPI_DSI1_I2C0_SDA 121
> > +#define SC_P_MIPI_DSI1_GPIO0_00 122
> > +#define SC_P_MIPI_DSI1_GPIO0_01 123
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124
> > +#define SC_P_JTAG_TRST_B 125
> > +#define SC_P_PMIC_I2C_SCL 126
> > +#define SC_P_PMIC_I2C_SDA 127
> > +#define SC_P_PMIC_INT_B 128
> > +#define SC_P_SCU_GPIO0_00 129
> > +#define SC_P_SCU_GPIO0_01 130
> > +#define SC_P_SCU_PMIC_STANDBY 131
> > +#define SC_P_SCU_BOOT_MODE0 132
> > +#define SC_P_SCU_BOOT_MODE1 133
> > +#define SC_P_SCU_BOOT_MODE2 134
> > +#define SC_P_SCU_BOOT_MODE3 135
> > +#define SC_P_CSI_D00 136
> > +#define SC_P_CSI_D01 137
> > +#define SC_P_CSI_D02 138
> > +#define SC_P_CSI_D03 139
> > +#define SC_P_CSI_D04 140
> > +#define SC_P_CSI_D05 141
> > +#define SC_P_CSI_D06 142
> > +#define SC_P_CSI_D07 143
> > +#define SC_P_CSI_HSYNC 144
> > +#define SC_P_CSI_VSYNC 145
> > +#define SC_P_CSI_PCLK 146
> > +#define SC_P_CSI_MCLK 147
> > +#define SC_P_CSI_EN 148
> > +#define SC_P_CSI_RESET 149
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150
> > +#define SC_P_MIPI_CSI0_MCLK_OUT 151
> > +#define SC_P_MIPI_CSI0_I2C0_SCL 152
> > +#define SC_P_MIPI_CSI0_I2C0_SDA 153
> > +#define SC_P_MIPI_CSI0_GPIO0_01 154
> > +#define SC_P_MIPI_CSI0_GPIO0_00 155
> > +#define SC_P_QSPI0A_DATA0 156
> > +#define SC_P_QSPI0A_DATA1 157
> > +#define SC_P_QSPI0A_DATA2 158
> > +#define SC_P_QSPI0A_DATA3 159
> > +#define SC_P_QSPI0A_DQS 160
> > +#define SC_P_QSPI0A_SS0_B 161
> > +#define SC_P_QSPI0A_SS1_B 162
> > +#define SC_P_QSPI0A_SCLK 163
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164
> > +#define SC_P_QSPI0B_SCLK 165
> > +#define SC_P_QSPI0B_DATA0 166
> > +#define SC_P_QSPI0B_DATA1 167
> > +#define SC_P_QSPI0B_DATA2 168
> > +#define SC_P_QSPI0B_DATA3 169
> > +#define SC_P_QSPI0B_DQS 170
> > +#define SC_P_QSPI0B_SS0_B 171
> > +#define SC_P_QSPI0B_SS1_B 172
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173
> > +
> > +/*
> > + * format: <pin_id mux_mode>
> > + */
> > +#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B
> SC_P_PCIE_CTRL0_PERST_B 0
> > +#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00
> SC_P_PCIE_CTRL0_PERST_B 4
> > +#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B
> SC_P_PCIE_CTRL0_CLKREQ_B 0
> > +#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01
> SC_P_PCIE_CTRL0_CLKREQ_B 4
> > +#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B
> SC_P_PCIE_CTRL0_WAKE_B 0
> > +#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02
> SC_P_PCIE_CTRL0_WAKE_B 4
> > +#define SC_P_USB_SS3_TC0_ADMA_I2C1_SCL
> SC_P_USB_SS3_TC0 0
> > +#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR
> SC_P_USB_SS3_TC0 1
> > +#define SC_P_USB_SS3_TC0_CONN_USB_OTG2_PWR
> SC_P_USB_SS3_TC0 2
> > +#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03
> SC_P_USB_SS3_TC0 4
> > +#define SC_P_USB_SS3_TC1_ADMA_I2C1_SCL
> SC_P_USB_SS3_TC1 0
> > +#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR
> SC_P_USB_SS3_TC1 1
> > +#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04
> SC_P_USB_SS3_TC1 4
> > +#define SC_P_USB_SS3_TC2_ADMA_I2C1_SDA
> SC_P_USB_SS3_TC2 0
> > +#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC
> SC_P_USB_SS3_TC2 1
> > +#define SC_P_USB_SS3_TC2_CONN_USB_OTG2_OC
> SC_P_USB_SS3_TC2 2
> > +#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05
> SC_P_USB_SS3_TC2 4
> > +#define SC_P_USB_SS3_TC3_ADMA_I2C1_SDA
> SC_P_USB_SS3_TC3 0
> > +#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC
> SC_P_USB_SS3_TC3 1
> > +#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06
> SC_P_USB_SS3_TC3 4
> > +#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK
> SC_P_EMMC0_CLK 0
> > +#define SC_P_EMMC0_CLK_CONN_NAND_READY_B
> SC_P_EMMC0_CLK 1
> > +#define SC_P_EMMC0_CLK_LSIO_GPIO4_IO07
> SC_P_EMMC0_CLK 4
> > +#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD
> SC_P_EMMC0_CMD 0
> > +#define SC_P_EMMC0_CMD_CONN_NAND_DQS
> SC_P_EMMC0_CMD 1
> > +#define SC_P_EMMC0_CMD_LSIO_GPIO4_IO08
> SC_P_EMMC0_CMD 4
> > +#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0
> SC_P_EMMC0_DATA0 0
> > +#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00
> SC_P_EMMC0_DATA0 1
> > +#define SC_P_EMMC0_DATA0_LSIO_GPIO4_IO09
> SC_P_EMMC0_DATA0 4
> > +#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1
> SC_P_EMMC0_DATA1 0
> > +#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01
> SC_P_EMMC0_DATA1 1
> > +#define SC_P_EMMC0_DATA1_LSIO_GPIO4_IO10
> SC_P_EMMC0_DATA1 4
> > +#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2
> SC_P_EMMC0_DATA2 0
> > +#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02
> SC_P_EMMC0_DATA2 1
> > +#define SC_P_EMMC0_DATA2_LSIO_GPIO4_IO11
> SC_P_EMMC0_DATA2 4
> > +#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3
> SC_P_EMMC0_DATA3 0
> > +#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03
> SC_P_EMMC0_DATA3 1
> > +#define SC_P_EMMC0_DATA3_LSIO_GPIO4_IO12
> SC_P_EMMC0_DATA3 4
> > +#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4
> SC_P_EMMC0_DATA4 0
> > +#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04
> SC_P_EMMC0_DATA4 1
> > +#define SC_P_EMMC0_DATA4_CONN_EMMC0_WP
> SC_P_EMMC0_DATA4 3
> > +#define SC_P_EMMC0_DATA4_LSIO_GPIO4_IO13
> SC_P_EMMC0_DATA4 4
> > +#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5
> SC_P_EMMC0_DATA5 0
> > +#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05
> SC_P_EMMC0_DATA5 1
> > +#define SC_P_EMMC0_DATA5_CONN_EMMC0_VSELECT
> SC_P_EMMC0_DATA5 3
> > +#define SC_P_EMMC0_DATA5_LSIO_GPIO4_IO14
> SC_P_EMMC0_DATA5 4
> > +#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6
> SC_P_EMMC0_DATA6 0
> > +#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06
> SC_P_EMMC0_DATA6 1
> > +#define SC_P_EMMC0_DATA6_CONN_MLB_CLK
> SC_P_EMMC0_DATA6 3
> > +#define SC_P_EMMC0_DATA6_LSIO_GPIO4_IO15
> SC_P_EMMC0_DATA6 4
> > +#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7
> SC_P_EMMC0_DATA7 0
> > +#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07
> SC_P_EMMC0_DATA7 1
> > +#define SC_P_EMMC0_DATA7_CONN_MLB_SIG
> SC_P_EMMC0_DATA7 3
> > +#define SC_P_EMMC0_DATA7_LSIO_GPIO4_IO16
> SC_P_EMMC0_DATA7 4
> > +#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE
> SC_P_EMMC0_STROBE 0
> > +#define SC_P_EMMC0_STROBE_CONN_NAND_CLE
> SC_P_EMMC0_STROBE 1
> > +#define SC_P_EMMC0_STROBE_CONN_MLB_DATA
> SC_P_EMMC0_STROBE 3
> > +#define SC_P_EMMC0_STROBE_LSIO_GPIO4_IO17
> SC_P_EMMC0_STROBE 4
> > +#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B
> SC_P_EMMC0_RESET_B 0
> > +#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B
> SC_P_EMMC0_RESET_B 1
> > +#define SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18
> SC_P_EMMC0_RESET_B 4
> > +#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B
> SC_P_USDHC1_RESET_B 0
> > +#define SC_P_USDHC1_RESET_B_CONN_NAND_RE_N
> SC_P_USDHC1_RESET_B 1
> > +#define SC_P_USDHC1_RESET_B_ADMA_SPI2_SCK
> SC_P_USDHC1_RESET_B 2
> > +#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19
> SC_P_USDHC1_RESET_B 4
> > +#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT
> SC_P_USDHC1_VSELECT 0
> > +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_P
> SC_P_USDHC1_VSELECT 1
> > +#define SC_P_USDHC1_VSELECT_ADMA_SPI2_SDO
> SC_P_USDHC1_VSELECT 2
> > +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_B
> SC_P_USDHC1_VSELECT 3
> > +#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO20
> SC_P_USDHC1_VSELECT 4
> > +#define SC_P_USDHC1_WP_CONN_USDHC1_WP
> SC_P_USDHC1_WP 0
> > +#define SC_P_USDHC1_WP_CONN_NAND_DQS_N
> SC_P_USDHC1_WP 1
> > +#define SC_P_USDHC1_WP_ADMA_SPI2_SDI
> SC_P_USDHC1_WP 2
> > +#define SC_P_USDHC1_WP_LSIO_GPIO4_IO21
> SC_P_USDHC1_WP 4
> > +#define SC_P_USDHC1_CD_B_CONN_USDHC1_CD_B
> SC_P_USDHC1_CD_B 0
> > +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS_P
> SC_P_USDHC1_CD_B 1
> > +#define SC_P_USDHC1_CD_B_ADMA_SPI2_CS0
> SC_P_USDHC1_CD_B 2
> > +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS
> SC_P_USDHC1_CD_B 3
> > +#define SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22
> SC_P_USDHC1_CD_B 4
> > +#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK
> SC_P_USDHC1_CLK 0
> > +#define SC_P_USDHC1_CLK_ADMA_UART3_RX
> SC_P_USDHC1_CLK 2
> > +#define SC_P_USDHC1_CLK_LSIO_GPIO4_IO23
> SC_P_USDHC1_CLK 4
> > +#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD
> SC_P_USDHC1_CMD 0
> > +#define SC_P_USDHC1_CMD_CONN_NAND_CE0_B
> SC_P_USDHC1_CMD 1
> > +#define SC_P_USDHC1_CMD_ADMA_MQS_R
> SC_P_USDHC1_CMD 2
> > +#define SC_P_USDHC1_CMD_LSIO_GPIO4_IO24
> SC_P_USDHC1_CMD 4
> > +#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0
> SC_P_USDHC1_DATA0 0
> > +#define SC_P_USDHC1_DATA0_CONN_NAND_CE1_B
> SC_P_USDHC1_DATA0 1
> > +#define SC_P_USDHC1_DATA0_ADMA_MQS_L
> SC_P_USDHC1_DATA0 2
> > +#define SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25
> SC_P_USDHC1_DATA0 4
> > +#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1
> SC_P_USDHC1_DATA1 0
> > +#define SC_P_USDHC1_DATA1_CONN_NAND_RE_B
> SC_P_USDHC1_DATA1 1
> > +#define SC_P_USDHC1_DATA1_ADMA_UART3_TX
> SC_P_USDHC1_DATA1 2
> > +#define SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26
> SC_P_USDHC1_DATA1 4
> > +#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2
> SC_P_USDHC1_DATA2 0
> > +#define SC_P_USDHC1_DATA2_CONN_NAND_WE_B
> SC_P_USDHC1_DATA2 1
> > +#define SC_P_USDHC1_DATA2_ADMA_UART3_CTS_B
> SC_P_USDHC1_DATA2 2
> > +#define SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27
> SC_P_USDHC1_DATA2 4
> > +#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3
> SC_P_USDHC1_DATA3 0
> > +#define SC_P_USDHC1_DATA3_CONN_NAND_ALE
> SC_P_USDHC1_DATA3 1
> > +#define SC_P_USDHC1_DATA3_ADMA_UART3_RTS_B
> SC_P_USDHC1_DATA3 2
> > +#define SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28
> SC_P_USDHC1_DATA3 4
> > +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC
> SC_P_ENET0_RGMII_TXC 0
> > +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT
> SC_P_ENET0_RGMII_TXC 1
> > +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN
> SC_P_ENET0_RGMII_TXC 2
> > +#define SC_P_ENET0_RGMII_TXC_CONN_NAND_CE1_B
> SC_P_ENET0_RGMII_TXC 3
> > +#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29
> SC_P_ENET0_RGMII_TXC 4
> > +#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL
> SC_P_ENET0_RGMII_TX_CTL 0
> > +#define SC_P_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B
> SC_P_ENET0_RGMII_TX_CTL 3
> > +#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30
> SC_P_ENET0_RGMII_TX_CTL 4
> > +#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0
> SC_P_ENET0_RGMII_TXD0 0
> > +#define SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT
> SC_P_ENET0_RGMII_TXD0 3
> > +#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31
> SC_P_ENET0_RGMII_TXD0 4
> > +#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1
> SC_P_ENET0_RGMII_TXD1 0
> > +#define SC_P_ENET0_RGMII_TXD1_CONN_USDHC1_WP
> SC_P_ENET0_RGMII_TXD1 3
> > +#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00
> SC_P_ENET0_RGMII_TXD1 4
> > +#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2
> SC_P_ENET0_RGMII_TXD2 0
> > +#define SC_P_ENET0_RGMII_TXD2_CONN_MLB_CLK
> SC_P_ENET0_RGMII_TXD2 1
> > +#define SC_P_ENET0_RGMII_TXD2_CONN_NAND_CE0_B
> SC_P_ENET0_RGMII_TXD2 2
> > +#define SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B
> SC_P_ENET0_RGMII_TXD2 3
> > +#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01
> SC_P_ENET0_RGMII_TXD2 4
> > +#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3
> SC_P_ENET0_RGMII_TXD3 0
> > +#define SC_P_ENET0_RGMII_TXD3_CONN_MLB_SIG
> SC_P_ENET0_RGMII_TXD3 1
> > +#define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B
> SC_P_ENET0_RGMII_TXD3 2
> > +#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02
> SC_P_ENET0_RGMII_TXD3 4
> > +#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC
> SC_P_ENET0_RGMII_RXC 0
> > +#define SC_P_ENET0_RGMII_RXC_CONN_MLB_DATA
> SC_P_ENET0_RGMII_RXC 1
> > +#define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B
> SC_P_ENET0_RGMII_RXC 2
> > +#define SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK
> SC_P_ENET0_RGMII_RXC 3
> > +#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03
> SC_P_ENET0_RGMII_RXC 4
> > +#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL
> SC_P_ENET0_RGMII_RX_CTL 0
> > +#define SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD
> SC_P_ENET0_RGMII_RX_CTL 3
> > +#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04
> SC_P_ENET0_RGMII_RX_CTL 4
> > +#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0
> SC_P_ENET0_RGMII_RXD0 0
> > +#define SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0
> SC_P_ENET0_RGMII_RXD0 3
> > +#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05
> SC_P_ENET0_RGMII_RXD0 4
> > +#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1
> SC_P_ENET0_RGMII_RXD1 0
> > +#define SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1
> SC_P_ENET0_RGMII_RXD1 3
> > +#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06
> SC_P_ENET0_RGMII_RXD1 4
> > +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2
> SC_P_ENET0_RGMII_RXD2 0
> > +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER
> SC_P_ENET0_RGMII_RXD2 1
> > +#define SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2
> SC_P_ENET0_RGMII_RXD2 3
> > +#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07
> SC_P_ENET0_RGMII_RXD2 4
> > +#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3
> SC_P_ENET0_RGMII_RXD3 0
> > +#define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE
> SC_P_ENET0_RGMII_RXD3 2
> > +#define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3
> SC_P_ENET0_RGMII_RXD3 3
> > +#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08
> SC_P_ENET0_RGMII_RXD3 4
> > +#define
> SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M
> SC_P_ENET0_REFCLK_125M_25M 0
> > +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS
> SC_P_ENET0_REFCLK_125M_25M 1
> > +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS
> SC_P_ENET0_REFCLK_125M_25M 2
> > +#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09
> SC_P_ENET0_REFCLK_125M_25M 4
> > +#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO
> SC_P_ENET0_MDIO 0
> > +#define SC_P_ENET0_MDIO_ADMA_I2C3_SDA
> SC_P_ENET0_MDIO 1
> > +#define SC_P_ENET0_MDIO_CONN_ENET1_MDIO
> SC_P_ENET0_MDIO 2
> > +#define SC_P_ENET0_MDIO_LSIO_GPIO5_IO10
> SC_P_ENET0_MDIO 4
> > +#define SC_P_ENET0_MDC_CONN_ENET0_MDC
> SC_P_ENET0_MDC 0
> > +#define SC_P_ENET0_MDC_ADMA_I2C3_SCL
> SC_P_ENET0_MDC 1
> > +#define SC_P_ENET0_MDC_CONN_ENET1_MDC
> SC_P_ENET0_MDC 2
> > +#define SC_P_ENET0_MDC_LSIO_GPIO5_IO11
> SC_P_ENET0_MDC 4
> > +#define SC_P_ESAI0_FSR_ADMA_ESAI0_FSR
> SC_P_ESAI0_FSR 0
> > +#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT
> SC_P_ESAI0_FSR 1
> > +#define SC_P_ESAI0_FSR_ADMA_LCDIF_D00
> SC_P_ESAI0_FSR 2
> > +#define SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC
> SC_P_ESAI0_FSR 3
> > +#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN
> SC_P_ESAI0_FSR 4
> > +#define SC_P_ESAI0_FST_ADMA_ESAI0_FST
> SC_P_ESAI0_FST 0
> > +#define SC_P_ESAI0_FST_CONN_MLB_CLK
> SC_P_ESAI0_FST 1
> > +#define SC_P_ESAI0_FST_ADMA_LCDIF_D01
> SC_P_ESAI0_FST 2
> > +#define SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2
> SC_P_ESAI0_FST 3
> > +#define SC_P_ESAI0_FST_LSIO_GPIO0_IO01 SC_P_ESAI0_FST
> 4
> > +#define SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR
> SC_P_ESAI0_SCKR 0
> > +#define SC_P_ESAI0_SCKR_ADMA_LCDIF_D02
> SC_P_ESAI0_SCKR 2
> > +#define SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL
> SC_P_ESAI0_SCKR 3
> > +#define SC_P_ESAI0_SCKR_LSIO_GPIO0_IO02
> SC_P_ESAI0_SCKR 4
> > +#define SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT
> SC_P_ESAI0_SCKT 0
> > +#define SC_P_ESAI0_SCKT_CONN_MLB_SIG
> SC_P_ESAI0_SCKT 1
> > +#define SC_P_ESAI0_SCKT_ADMA_LCDIF_D03
> SC_P_ESAI0_SCKT 2
> > +#define SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3
> SC_P_ESAI0_SCKT 3
> > +#define SC_P_ESAI0_SCKT_LSIO_GPIO0_IO03
> SC_P_ESAI0_SCKT 4
> > +#define SC_P_ESAI0_TX0_ADMA_ESAI0_TX0
> SC_P_ESAI0_TX0 0
> > +#define SC_P_ESAI0_TX0_CONN_MLB_DATA
> SC_P_ESAI0_TX0 1
> > +#define SC_P_ESAI0_TX0_ADMA_LCDIF_D04
> SC_P_ESAI0_TX0 2
> > +#define SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC
> SC_P_ESAI0_TX0 3
> > +#define SC_P_ESAI0_TX0_LSIO_GPIO0_IO04
> SC_P_ESAI0_TX0 4
> > +#define SC_P_ESAI0_TX1_ADMA_ESAI0_TX1
> SC_P_ESAI0_TX1 0
> > +#define SC_P_ESAI0_TX1_ADMA_LCDIF_D05
> SC_P_ESAI0_TX1 2
> > +#define SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3
> SC_P_ESAI0_TX1 3
> > +#define SC_P_ESAI0_TX1_LSIO_GPIO0_IO05
> SC_P_ESAI0_TX1 4
> > +#define SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3
> SC_P_ESAI0_TX2_RX3 0
> > +#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER
> SC_P_ESAI0_TX2_RX3 1
> > +#define SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06
> SC_P_ESAI0_TX2_RX3 2
> > +#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2
> SC_P_ESAI0_TX2_RX3 3
> > +#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO0_IO06
> SC_P_ESAI0_TX2_RX3 4
> > +#define SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2
> SC_P_ESAI0_TX3_RX2 0
> > +#define SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07
> SC_P_ESAI0_TX3_RX2 2
> > +#define SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1
> SC_P_ESAI0_TX3_RX2 3
> > +#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO0_IO07
> SC_P_ESAI0_TX3_RX2 4
> > +#define SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1
> SC_P_ESAI0_TX4_RX1 0
> > +#define SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08
> SC_P_ESAI0_TX4_RX1 2
> > +#define SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0
> SC_P_ESAI0_TX4_RX1 3
> > +#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO0_IO08
> SC_P_ESAI0_TX4_RX1 4
> > +#define SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0
> SC_P_ESAI0_TX5_RX0 0
> > +#define SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09
> SC_P_ESAI0_TX5_RX0 2
> > +#define SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1
> SC_P_ESAI0_TX5_RX0 3
> > +#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO0_IO09
> SC_P_ESAI0_TX5_RX0 4
> > +#define SC_P_SPDIF0_RX_ADMA_SPDIF0_RX
> SC_P_SPDIF0_RX 0
> > +#define SC_P_SPDIF0_RX_ADMA_MQS_R
> SC_P_SPDIF0_RX 1
> > +#define SC_P_SPDIF0_RX_ADMA_LCDIF_D10
> SC_P_SPDIF0_RX 2
> > +#define SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0
> SC_P_SPDIF0_RX 3
> > +#define SC_P_SPDIF0_RX_LSIO_GPIO0_IO10
> SC_P_SPDIF0_RX 4
> > +#define SC_P_SPDIF0_TX_ADMA_SPDIF0_TX
> SC_P_SPDIF0_TX 0
> > +#define SC_P_SPDIF0_TX_ADMA_MQS_L
> SC_P_SPDIF0_TX 1
> > +#define SC_P_SPDIF0_TX_ADMA_LCDIF_D11
> SC_P_SPDIF0_TX 2
> > +#define SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL
> SC_P_SPDIF0_TX 3
> > +#define SC_P_SPDIF0_TX_LSIO_GPIO0_IO11
> SC_P_SPDIF0_TX 4
> > +#define SC_P_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK
> SC_P_SPDIF0_EXT_CLK 0
> > +#define SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12
> SC_P_SPDIF0_EXT_CLK 2
> > +#define SC_P_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M
> SC_P_SPDIF0_EXT_CLK 3
> > +#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12
> SC_P_SPDIF0_EXT_CLK 4
> > +#define SC_P_SPI3_SCK_ADMA_SPI3_SCK SC_P_SPI3_SCK
> 0
> > +#define SC_P_SPI3_SCK_ADMA_LCDIF_D13 SC_P_SPI3_SCK
> 2
> > +#define SC_P_SPI3_SCK_LSIO_GPIO0_IO13 SC_P_SPI3_SCK
> 4
> > +#define SC_P_SPI3_SDO_ADMA_SPI3_SDO
> SC_P_SPI3_SDO 0
> > +#define SC_P_SPI3_SDO_ADMA_LCDIF_D14
> SC_P_SPI3_SDO 2
> > +#define SC_P_SPI3_SDO_LSIO_GPIO0_IO14 SC_P_SPI3_SDO
> 4
> > +#define SC_P_SPI3_SDI_ADMA_SPI3_SDI SC_P_SPI3_SDI
> 0
> > +#define SC_P_SPI3_SDI_ADMA_LCDIF_D15 SC_P_SPI3_SDI
> 2
> > +#define SC_P_SPI3_SDI_LSIO_GPIO0_IO15 SC_P_SPI3_SDI
> 4
> > +#define SC_P_SPI3_CS0_ADMA_SPI3_CS0 SC_P_SPI3_CS0
> 0
> > +#define SC_P_SPI3_CS0_ADMA_ACM_MCLK_OUT1
> SC_P_SPI3_CS0 1
> > +#define SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC
> SC_P_SPI3_CS0 2
> > +#define SC_P_SPI3_CS0_LSIO_GPIO0_IO16 SC_P_SPI3_CS0
> 4
> > +#define SC_P_SPI3_CS1_ADMA_SPI3_CS1 SC_P_SPI3_CS1
> 0
> > +#define SC_P_SPI3_CS1_ADMA_I2C3_SCL SC_P_SPI3_CS1
> 1
> > +#define SC_P_SPI3_CS1_ADMA_LCDIF_RESET
> SC_P_SPI3_CS1 2
> > +#define SC_P_SPI3_CS1_ADMA_SPI2_CS0 SC_P_SPI3_CS1
> 3
> > +#define SC_P_SPI3_CS1_ADMA_LCDIF_D16 SC_P_SPI3_CS1
> 4
> > +#define SC_P_MCLK_IN1_ADMA_ACM_MCLK_IN1
> SC_P_MCLK_IN1 0
> > +#define SC_P_MCLK_IN1_ADMA_I2C3_SDA
> SC_P_MCLK_IN1 1
> > +#define SC_P_MCLK_IN1_ADMA_LCDIF_EN
> SC_P_MCLK_IN1 2
> > +#define SC_P_MCLK_IN1_ADMA_SPI2_SCK
> SC_P_MCLK_IN1 3
> > +#define SC_P_MCLK_IN1_ADMA_LCDIF_D17
> SC_P_MCLK_IN1 4
> > +#define SC_P_MCLK_IN0_ADMA_ACM_MCLK_IN0
> SC_P_MCLK_IN0 0
> > +#define SC_P_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK
> SC_P_MCLK_IN0 1
> > +#define SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC
> SC_P_MCLK_IN0 2
> > +#define SC_P_MCLK_IN0_ADMA_SPI2_SDI
> SC_P_MCLK_IN0 3
> > +#define SC_P_MCLK_IN0_LSIO_GPIO0_IO19
> SC_P_MCLK_IN0 4
> > +#define SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0
> SC_P_MCLK_OUT0 0
> > +#define SC_P_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK
> SC_P_MCLK_OUT0 1
> > +#define SC_P_MCLK_OUT0_ADMA_LCDIF_CLK
> SC_P_MCLK_OUT0 2
> > +#define SC_P_MCLK_OUT0_ADMA_SPI2_SDO
> SC_P_MCLK_OUT0 3
> > +#define SC_P_MCLK_OUT0_LSIO_GPIO0_IO20
> SC_P_MCLK_OUT0 4
> > +#define SC_P_UART1_TX_ADMA_UART1_TX
> SC_P_UART1_TX 0
> > +#define SC_P_UART1_TX_LSIO_PWM0_OUT
> SC_P_UART1_TX 1
> > +#define SC_P_UART1_TX_LSIO_GPT0_CAPTURE
> SC_P_UART1_TX 2
> > +#define SC_P_UART1_TX_LSIO_GPIO0_IO21
> SC_P_UART1_TX 4
> > +#define SC_P_UART1_RX_ADMA_UART1_RX
> SC_P_UART1_RX 0
> > +#define SC_P_UART1_RX_LSIO_PWM1_OUT
> SC_P_UART1_RX 1
> > +#define SC_P_UART1_RX_LSIO_GPT0_COMPARE
> SC_P_UART1_RX 2
> > +#define SC_P_UART1_RX_LSIO_GPT1_CLK SC_P_UART1_RX
> 3
> > +#define SC_P_UART1_RX_LSIO_GPIO0_IO22
> SC_P_UART1_RX 4
> > +#define SC_P_UART1_RTS_B_ADMA_UART1_RTS_B
> SC_P_UART1_RTS_B 0
> > +#define SC_P_UART1_RTS_B_LSIO_PWM2_OUT
> SC_P_UART1_RTS_B 1
> > +#define SC_P_UART1_RTS_B_ADMA_LCDIF_D16
> SC_P_UART1_RTS_B 2
> > +#define SC_P_UART1_RTS_B_LSIO_GPT1_CAPTURE
> SC_P_UART1_RTS_B 3
> > +#define SC_P_UART1_RTS_B_LSIO_GPT0_CLK
> SC_P_UART1_RTS_B 4
> > +#define SC_P_UART1_CTS_B_ADMA_UART1_CTS_B
> SC_P_UART1_CTS_B 0
> > +#define SC_P_UART1_CTS_B_LSIO_PWM3_OUT
> SC_P_UART1_CTS_B 1
> > +#define SC_P_UART1_CTS_B_ADMA_LCDIF_D17
> SC_P_UART1_CTS_B 2
> > +#define SC_P_UART1_CTS_B_LSIO_GPT1_COMPARE
> SC_P_UART1_CTS_B 3
> > +#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO24
> SC_P_UART1_CTS_B 4
> > +#define SC_P_SAI0_TXD_ADMA_SAI0_TXD SC_P_SAI0_TXD
> 0
> > +#define SC_P_SAI0_TXD_ADMA_SAI1_RXC SC_P_SAI0_TXD
> 1
> > +#define SC_P_SAI0_TXD_ADMA_SPI1_SDO SC_P_SAI0_TXD
> 2
> > +#define SC_P_SAI0_TXD_ADMA_LCDIF_D18
> SC_P_SAI0_TXD 3
> > +#define SC_P_SAI0_TXD_LSIO_GPIO0_IO25 SC_P_SAI0_TXD
> 4
> > +#define SC_P_SAI0_TXC_ADMA_SAI0_TXC SC_P_SAI0_TXC
> 0
> > +#define SC_P_SAI0_TXC_ADMA_SAI1_TXD SC_P_SAI0_TXC
> 1
> > +#define SC_P_SAI0_TXC_ADMA_SPI1_SDI SC_P_SAI0_TXC
> 2
> > +#define SC_P_SAI0_TXC_ADMA_LCDIF_D19 SC_P_SAI0_TXC
> 3
> > +#define SC_P_SAI0_TXC_LSIO_GPIO0_IO26 SC_P_SAI0_TXC
> 4
> > +#define SC_P_SAI0_RXD_ADMA_SAI0_RXD
> SC_P_SAI0_RXD 0
> > +#define SC_P_SAI0_RXD_ADMA_SAI1_RXFS
> SC_P_SAI0_RXD 1
> > +#define SC_P_SAI0_RXD_ADMA_SPI1_CS0 SC_P_SAI0_RXD
> 2
> > +#define SC_P_SAI0_RXD_ADMA_LCDIF_D20
> SC_P_SAI0_RXD 3
> > +#define SC_P_SAI0_RXD_LSIO_GPIO0_IO27 SC_P_SAI0_RXD
> 4
> > +#define SC_P_SAI0_TXFS_ADMA_SAI0_TXFS
> SC_P_SAI0_TXFS 0
> > +#define SC_P_SAI0_TXFS_ADMA_SPI2_CS1
> SC_P_SAI0_TXFS 1
> > +#define SC_P_SAI0_TXFS_ADMA_SPI1_SCK
> SC_P_SAI0_TXFS 2
> > +#define SC_P_SAI0_TXFS_LSIO_GPIO0_IO28
> SC_P_SAI0_TXFS 4
> > +#define SC_P_SAI1_RXD_ADMA_SAI1_RXD
> SC_P_SAI1_RXD 0
> > +#define SC_P_SAI1_RXD_ADMA_SAI0_RXFS
> SC_P_SAI1_RXD 1
> > +#define SC_P_SAI1_RXD_ADMA_SPI1_CS1 SC_P_SAI1_RXD
> 2
> > +#define SC_P_SAI1_RXD_ADMA_LCDIF_D21
> SC_P_SAI1_RXD 3
> > +#define SC_P_SAI1_RXD_LSIO_GPIO0_IO29 SC_P_SAI1_RXD
> 4
> > +#define SC_P_SAI1_RXC_ADMA_SAI1_RXC SC_P_SAI1_RXC
> 0
> > +#define SC_P_SAI1_RXC_ADMA_SAI1_TXC SC_P_SAI1_RXC
> 1
> > +#define SC_P_SAI1_RXC_ADMA_LCDIF_D22
> SC_P_SAI1_RXC 3
> > +#define SC_P_SAI1_RXC_LSIO_GPIO0_IO30 SC_P_SAI1_RXC
> 4
> > +#define SC_P_SAI1_RXFS_ADMA_SAI1_RXFS
> SC_P_SAI1_RXFS 0
> > +#define SC_P_SAI1_RXFS_ADMA_SAI1_TXFS
> SC_P_SAI1_RXFS 1
> > +#define SC_P_SAI1_RXFS_ADMA_LCDIF_D23
> SC_P_SAI1_RXFS 3
> > +#define SC_P_SAI1_RXFS_LSIO_GPIO0_IO31
> SC_P_SAI1_RXFS 4
> > +#define SC_P_SPI2_CS0_ADMA_SPI2_CS0 SC_P_SPI2_CS0
> 0
> > +#define SC_P_SPI2_CS0_LSIO_GPIO1_IO00 SC_P_SPI2_CS0
> 4
> > +#define SC_P_SPI2_SDO_ADMA_SPI2_SDO
> SC_P_SPI2_SDO 0
> > +#define SC_P_SPI2_SDO_LSIO_GPIO1_IO01 SC_P_SPI2_SDO
> 4
> > +#define SC_P_SPI2_SDI_ADMA_SPI2_SDI SC_P_SPI2_SDI
> 0
> > +#define SC_P_SPI2_SDI_LSIO_GPIO1_IO02 SC_P_SPI2_SDI
> 4
> > +#define SC_P_SPI2_SCK_ADMA_SPI2_SCK SC_P_SPI2_SCK
> 0
> > +#define SC_P_SPI2_SCK_LSIO_GPIO1_IO03 SC_P_SPI2_SCK
> 4
> > +#define SC_P_SPI0_SCK_ADMA_SPI0_SCK SC_P_SPI0_SCK
> 0
> > +#define SC_P_SPI0_SCK_ADMA_SAI0_TXC SC_P_SPI0_SCK
> 1
> > +#define SC_P_SPI0_SCK_M40_I2C0_SCL SC_P_SPI0_SCK
> 2
> > +#define SC_P_SPI0_SCK_M40_GPIO0_IO00 SC_P_SPI0_SCK
> 3
> > +#define SC_P_SPI0_SCK_LSIO_GPIO1_IO04 SC_P_SPI0_SCK
> 4
> > +#define SC_P_SPI0_SDI_ADMA_SPI0_SDI SC_P_SPI0_SDI
> 0
> > +#define SC_P_SPI0_SDI_ADMA_SAI0_TXD SC_P_SPI0_SDI
> 1
> > +#define SC_P_SPI0_SDI_M40_TPM0_CH0 SC_P_SPI0_SDI
> 2
> > +#define SC_P_SPI0_SDI_M40_GPIO0_IO02 SC_P_SPI0_SDI
> 3
> > +#define SC_P_SPI0_SDI_LSIO_GPIO1_IO05 SC_P_SPI0_SDI
> 4
> > +#define SC_P_SPI0_SDO_ADMA_SPI0_SDO
> SC_P_SPI0_SDO 0
> > +#define SC_P_SPI0_SDO_ADMA_SAI0_TXFS
> SC_P_SPI0_SDO 1
> > +#define SC_P_SPI0_SDO_M40_I2C0_SDA SC_P_SPI0_SDO
> 2
> > +#define SC_P_SPI0_SDO_M40_GPIO0_IO01 SC_P_SPI0_SDO
> 3
> > +#define SC_P_SPI0_SDO_LSIO_GPIO1_IO06 SC_P_SPI0_SDO
> 4
> > +#define SC_P_SPI0_CS1_ADMA_SPI0_CS1 SC_P_SPI0_CS1
> 0
> > +#define SC_P_SPI0_CS1_ADMA_SAI0_RXC SC_P_SPI0_CS1
> 1
> > +#define SC_P_SPI0_CS1_ADMA_SAI1_TXD SC_P_SPI0_CS1
> 2
> > +#define SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT
> SC_P_SPI0_CS1 3
> > +#define SC_P_SPI0_CS1_LSIO_GPIO1_IO07 SC_P_SPI0_CS1
> 4
> > +#define SC_P_SPI0_CS0_ADMA_SPI0_CS0 SC_P_SPI0_CS0
> 0
> > +#define SC_P_SPI0_CS0_ADMA_SAI0_RXD SC_P_SPI0_CS0
> 1
> > +#define SC_P_SPI0_CS0_M40_TPM0_CH1 SC_P_SPI0_CS0
> 2
> > +#define SC_P_SPI0_CS0_M40_GPIO0_IO03 SC_P_SPI0_CS0
> 3
> > +#define SC_P_SPI0_CS0_LSIO_GPIO1_IO08 SC_P_SPI0_CS0
> 4
> > +#define SC_P_ADC_IN1_ADMA_ADC_IN1 SC_P_ADC_IN1
> 0
> > +#define SC_P_ADC_IN1_M40_I2C0_SDA SC_P_ADC_IN1
> 1
> > +#define SC_P_ADC_IN1_M40_GPIO0_IO01 SC_P_ADC_IN1
> 2
> > +#define SC_P_ADC_IN1_LSIO_GPIO1_IO09 SC_P_ADC_IN1
> 4
> > +#define SC_P_ADC_IN0_ADMA_ADC_IN0 SC_P_ADC_IN0
> 0
> > +#define SC_P_ADC_IN0_M40_I2C0_SCL SC_P_ADC_IN0
> 1
> > +#define SC_P_ADC_IN0_M40_GPIO0_IO00 SC_P_ADC_IN0
> 2
> > +#define SC_P_ADC_IN0_LSIO_GPIO1_IO10 SC_P_ADC_IN0
> 4
> > +#define SC_P_ADC_IN3_ADMA_ADC_IN3 SC_P_ADC_IN3
> 0
> > +#define SC_P_ADC_IN3_M40_UART0_TX SC_P_ADC_IN3
> 1
> > +#define SC_P_ADC_IN3_M40_GPIO0_IO03 SC_P_ADC_IN3
> 2
> > +#define SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0
> SC_P_ADC_IN3 3
> > +#define SC_P_ADC_IN3_LSIO_GPIO1_IO11 SC_P_ADC_IN3
> 4
> > +#define SC_P_ADC_IN2_ADMA_ADC_IN2 SC_P_ADC_IN2
> 0
> > +#define SC_P_ADC_IN2_M40_UART0_RX SC_P_ADC_IN2
> 1
> > +#define SC_P_ADC_IN2_M40_GPIO0_IO02 SC_P_ADC_IN2
> 2
> > +#define SC_P_ADC_IN2_ADMA_ACM_MCLK_IN0
> SC_P_ADC_IN2 3
> > +#define SC_P_ADC_IN2_LSIO_GPIO1_IO12 SC_P_ADC_IN2
> 4
> > +#define SC_P_ADC_IN5_ADMA_ADC_IN5 SC_P_ADC_IN5
> 0
> > +#define SC_P_ADC_IN5_M40_TPM0_CH1 SC_P_ADC_IN5
> 1
> > +#define SC_P_ADC_IN5_M40_GPIO0_IO05 SC_P_ADC_IN5
> 2
> > +#define SC_P_ADC_IN5_LSIO_GPIO1_IO13 SC_P_ADC_IN5
> 4
> > +#define SC_P_ADC_IN4_ADMA_ADC_IN4 SC_P_ADC_IN4
> 0
> > +#define SC_P_ADC_IN4_M40_TPM0_CH0 SC_P_ADC_IN4
> 1
> > +#define SC_P_ADC_IN4_M40_GPIO0_IO04 SC_P_ADC_IN4
> 2
> > +#define SC_P_ADC_IN4_LSIO_GPIO1_IO14 SC_P_ADC_IN4
> 4
> > +#define SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX
> SC_P_FLEXCAN0_RX 0
> > +#define SC_P_FLEXCAN0_RX_ADMA_SAI2_RXC
> SC_P_FLEXCAN0_RX 1
> > +#define SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B
> SC_P_FLEXCAN0_RX 2
> > +#define SC_P_FLEXCAN0_RX_ADMA_SAI1_TXC
> SC_P_FLEXCAN0_RX 3
> > +#define SC_P_FLEXCAN0_RX_LSIO_GPIO1_IO15
> SC_P_FLEXCAN0_RX 4
> > +#define SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX
> SC_P_FLEXCAN0_TX 0
> > +#define SC_P_FLEXCAN0_TX_ADMA_SAI2_RXD
> SC_P_FLEXCAN0_TX 1
> > +#define SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B
> SC_P_FLEXCAN0_TX 2
> > +#define SC_P_FLEXCAN0_TX_ADMA_SAI1_TXFS
> SC_P_FLEXCAN0_TX 3
> > +#define SC_P_FLEXCAN0_TX_LSIO_GPIO1_IO16
> SC_P_FLEXCAN0_TX 4
> > +#define SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX
> SC_P_FLEXCAN1_RX 0
> > +#define SC_P_FLEXCAN1_RX_ADMA_SAI2_RXFS
> SC_P_FLEXCAN1_RX 1
> > +#define SC_P_FLEXCAN1_RX_ADMA_FTM_CH2
> SC_P_FLEXCAN1_RX 2
> > +#define SC_P_FLEXCAN1_RX_ADMA_SAI1_TXD
> SC_P_FLEXCAN1_RX 3
> > +#define SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17
> SC_P_FLEXCAN1_RX 4
> > +#define SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX
> SC_P_FLEXCAN1_TX 0
> > +#define SC_P_FLEXCAN1_TX_ADMA_SAI3_RXC
> SC_P_FLEXCAN1_TX 1
> > +#define SC_P_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0
> SC_P_FLEXCAN1_TX 2
> > +#define SC_P_FLEXCAN1_TX_ADMA_SAI1_RXD
> SC_P_FLEXCAN1_TX 3
> > +#define SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18
> SC_P_FLEXCAN1_TX 4
> > +#define SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX
> SC_P_FLEXCAN2_RX 0
> > +#define SC_P_FLEXCAN2_RX_ADMA_SAI3_RXD
> SC_P_FLEXCAN2_RX 1
> > +#define SC_P_FLEXCAN2_RX_ADMA_UART3_RX
> SC_P_FLEXCAN2_RX 2
> > +#define SC_P_FLEXCAN2_RX_ADMA_SAI1_RXFS
> SC_P_FLEXCAN2_RX 3
> > +#define SC_P_FLEXCAN2_RX_LSIO_GPIO1_IO19
> SC_P_FLEXCAN2_RX 4
> > +#define SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX
> SC_P_FLEXCAN2_TX 0
> > +#define SC_P_FLEXCAN2_TX_ADMA_SAI3_RXFS
> SC_P_FLEXCAN2_TX 1
> > +#define SC_P_FLEXCAN2_TX_ADMA_UART3_TX
> SC_P_FLEXCAN2_TX 2
> > +#define SC_P_FLEXCAN2_TX_ADMA_SAI1_RXC
> SC_P_FLEXCAN2_TX 3
> > +#define SC_P_FLEXCAN2_TX_LSIO_GPIO1_IO20
> SC_P_FLEXCAN2_TX 4
> > +#define SC_P_UART0_RX_ADMA_UART0_RX
> SC_P_UART0_RX 0
> > +#define SC_P_UART0_RX_ADMA_MQS_R
> SC_P_UART0_RX 1
> > +#define SC_P_UART0_RX_ADMA_FLEXCAN0_RX
> SC_P_UART0_RX 2
> > +#define SC_P_UART0_RX_LSIO_GPIO1_IO21
> SC_P_UART0_RX 4
> > +#define SC_P_UART0_TX_ADMA_UART0_TX
> SC_P_UART0_TX 0
> > +#define SC_P_UART0_TX_ADMA_MQS_L
> SC_P_UART0_TX 1
> > +#define SC_P_UART0_TX_ADMA_FLEXCAN0_TX
> SC_P_UART0_TX 2
> > +#define SC_P_UART0_TX_LSIO_GPIO1_IO22
> SC_P_UART0_TX 4
> > +#define SC_P_UART2_TX_ADMA_UART2_TX
> SC_P_UART2_TX 0
> > +#define SC_P_UART2_TX_ADMA_FTM_CH1
> SC_P_UART2_TX 1
> > +#define SC_P_UART2_TX_ADMA_FLEXCAN1_TX
> SC_P_UART2_TX 2
> > +#define SC_P_UART2_TX_LSIO_GPIO1_IO23
> SC_P_UART2_TX 4
> > +#define SC_P_UART2_RX_ADMA_UART2_RX
> SC_P_UART2_RX 0
> > +#define SC_P_UART2_RX_ADMA_FTM_CH0
> SC_P_UART2_RX 1
> > +#define SC_P_UART2_RX_ADMA_FLEXCAN1_RX
> SC_P_UART2_RX 2
> > +#define SC_P_UART2_RX_LSIO_GPIO1_IO24
> SC_P_UART2_RX 4
> > +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL
> SC_P_MIPI_DSI0_I2C0_SCL 0
> > +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02
> SC_P_MIPI_DSI0_I2C0_SCL 1
> > +#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25
> SC_P_MIPI_DSI0_I2C0_SCL 4
> > +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA
> SC_P_MIPI_DSI0_I2C0_SDA 0
> > +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03
> SC_P_MIPI_DSI0_I2C0_SDA 1
> > +#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26
> SC_P_MIPI_DSI0_I2C0_SDA 4
> > +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00
> SC_P_MIPI_DSI0_GPIO0_00 0
> > +#define SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL
> SC_P_MIPI_DSI0_GPIO0_00 1
> > +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT
> SC_P_MIPI_DSI0_GPIO0_00 2
> > +#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27
> SC_P_MIPI_DSI0_GPIO0_00 4
> > +#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01
> SC_P_MIPI_DSI0_GPIO0_01 0
> > +#define SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA
> SC_P_MIPI_DSI0_GPIO0_01 1
> > +#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28
> SC_P_MIPI_DSI0_GPIO0_01 4
> > +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL
> SC_P_MIPI_DSI1_I2C0_SCL 0
> > +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02
> SC_P_MIPI_DSI1_I2C0_SCL 1
> > +#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29
> SC_P_MIPI_DSI1_I2C0_SCL 4
> > +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA
> SC_P_MIPI_DSI1_I2C0_SDA 0
> > +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03
> SC_P_MIPI_DSI1_I2C0_SDA 1
> > +#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30
> SC_P_MIPI_DSI1_I2C0_SDA 4
> > +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00
> SC_P_MIPI_DSI1_GPIO0_00 0
> > +#define SC_P_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL
> SC_P_MIPI_DSI1_GPIO0_00 1
> > +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT
> SC_P_MIPI_DSI1_GPIO0_00 2
> > +#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31
> SC_P_MIPI_DSI1_GPIO0_00 4
> > +#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01
> SC_P_MIPI_DSI1_GPIO0_01 0
> > +#define SC_P_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA
> SC_P_MIPI_DSI1_GPIO0_01 1
> > +#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00
> SC_P_MIPI_DSI1_GPIO0_01 4
> > +#define SC_P_JTAG_TRST_B_SCU_JTAG_TRST_B
> SC_P_JTAG_TRST_B 0
> > +#define SC_P_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT
> SC_P_JTAG_TRST_B 1
> > +#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL
> SC_P_PMIC_I2C_SCL 0
> > +#define SC_P_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON
> SC_P_PMIC_I2C_SCL 1
> > +#define SC_P_PMIC_I2C_SCL_LSIO_GPIO2_IO01
> SC_P_PMIC_I2C_SCL 4
> > +#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA
> SC_P_PMIC_I2C_SDA 0
> > +#define SC_P_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON
> SC_P_PMIC_I2C_SDA 1
> > +#define SC_P_PMIC_I2C_SDA_LSIO_GPIO2_IO02
> SC_P_PMIC_I2C_SDA 4
> > +#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B
> SC_P_PMIC_INT_B 0
> > +#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00
> SC_P_SCU_GPIO0_00 0
> > +#define SC_P_SCU_GPIO0_00_SCU_UART0_RX
> SC_P_SCU_GPIO0_00 1
> > +#define SC_P_SCU_GPIO0_00_M40_UART0_RX
> SC_P_SCU_GPIO0_00 2
> > +#define SC_P_SCU_GPIO0_00_ADMA_UART3_RX
> SC_P_SCU_GPIO0_00 3
> > +#define SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03
> SC_P_SCU_GPIO0_00 4
> > +#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01
> SC_P_SCU_GPIO0_01 0
> > +#define SC_P_SCU_GPIO0_01_SCU_UART0_TX
> SC_P_SCU_GPIO0_01 1
> > +#define SC_P_SCU_GPIO0_01_M40_UART0_TX
> SC_P_SCU_GPIO0_01 2
> > +#define SC_P_SCU_GPIO0_01_ADMA_UART3_TX
> SC_P_SCU_GPIO0_01 3
> > +#define SC_P_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT
> SC_P_SCU_GPIO0_01 4
> > +#define SC_P_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY
> SC_P_SCU_PMIC_STANDBY 0
> > +#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0
> SC_P_SCU_BOOT_MODE0 0
> > +#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1
> SC_P_SCU_BOOT_MODE1 0
> > +#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2
> SC_P_SCU_BOOT_MODE2 0
> > +#define SC_P_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA
> SC_P_SCU_BOOT_MODE2 1
> > +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3
> SC_P_SCU_BOOT_MODE3 0
> > +#define SC_P_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL
> SC_P_SCU_BOOT_MODE3 1
> > +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K
> SC_P_SCU_BOOT_MODE3 3
> > +#define SC_P_CSI_D00_CI_PI_D02 SC_P_CSI_D00
> 0
> > +#define SC_P_CSI_D00_ADMA_SAI0_RXC SC_P_CSI_D00
> 2
> > +#define SC_P_CSI_D01_CI_PI_D03 SC_P_CSI_D01
> 0
> > +#define SC_P_CSI_D01_ADMA_SAI0_RXD SC_P_CSI_D01
> 2
> > +#define SC_P_CSI_D02_CI_PI_D04 SC_P_CSI_D02
> 0
> > +#define SC_P_CSI_D02_ADMA_SAI0_RXFS SC_P_CSI_D02
> 2
> > +#define SC_P_CSI_D03_CI_PI_D05 SC_P_CSI_D03
> 0
> > +#define SC_P_CSI_D03_ADMA_SAI2_RXC SC_P_CSI_D03
> 2
> > +#define SC_P_CSI_D04_CI_PI_D06 SC_P_CSI_D04
> 0
> > +#define SC_P_CSI_D04_ADMA_SAI2_RXD SC_P_CSI_D04
> 2
> > +#define SC_P_CSI_D05_CI_PI_D07 SC_P_CSI_D05
> 0
> > +#define SC_P_CSI_D05_ADMA_SAI2_RXFS SC_P_CSI_D05
> 2
> > +#define SC_P_CSI_D06_CI_PI_D08 SC_P_CSI_D06
> 0
> > +#define SC_P_CSI_D06_ADMA_SAI3_RXC SC_P_CSI_D06
> 2
> > +#define SC_P_CSI_D07_CI_PI_D09 SC_P_CSI_D07
> 0
> > +#define SC_P_CSI_D07_ADMA_SAI3_RXD SC_P_CSI_D07
> 2
> > +#define SC_P_CSI_HSYNC_CI_PI_HSYNC SC_P_CSI_HSYNC
> 0
> > +#define SC_P_CSI_HSYNC_CI_PI_D00 SC_P_CSI_HSYNC
> 1
> > +#define SC_P_CSI_HSYNC_ADMA_SAI3_RXFS
> SC_P_CSI_HSYNC 2
> > +#define SC_P_CSI_VSYNC_CI_PI_VSYNC SC_P_CSI_VSYNC
> 0
> > +#define SC_P_CSI_VSYNC_CI_PI_D01 SC_P_CSI_VSYNC
> 1
> > +#define SC_P_CSI_PCLK_CI_PI_PCLK SC_P_CSI_PCLK
> 0
> > +#define SC_P_CSI_PCLK_MIPI_CSI0_I2C0_SCL SC_P_CSI_PCLK
> 1
> > +#define SC_P_CSI_PCLK_ADMA_SPI1_SCK SC_P_CSI_PCLK
> 3
> > +#define SC_P_CSI_PCLK_LSIO_GPIO3_IO00 SC_P_CSI_PCLK
> 4
> > +#define SC_P_CSI_MCLK_CI_PI_MCLK SC_P_CSI_MCLK
> 0
> > +#define SC_P_CSI_MCLK_MIPI_CSI0_I2C0_SDA
> SC_P_CSI_MCLK 1
> > +#define SC_P_CSI_MCLK_ADMA_SPI1_SDO
> SC_P_CSI_MCLK 3
> > +#define SC_P_CSI_MCLK_LSIO_GPIO3_IO01
> SC_P_CSI_MCLK 4
> > +#define SC_P_CSI_EN_CI_PI_EN SC_P_CSI_EN
> 0
> > +#define SC_P_CSI_EN_CI_PI_I2C_SCL SC_P_CSI_EN
> 1
> > +#define SC_P_CSI_EN_ADMA_I2C3_SCL SC_P_CSI_EN
> 2
> > +#define SC_P_CSI_EN_ADMA_SPI1_SDI SC_P_CSI_EN
> 3
> > +#define SC_P_CSI_EN_LSIO_GPIO3_IO02 SC_P_CSI_EN
> 4
> > +#define SC_P_CSI_RESET_CI_PI_RESET SC_P_CSI_RESET
> 0
> > +#define SC_P_CSI_RESET_CI_PI_I2C_SDA SC_P_CSI_RESET
> 1
> > +#define SC_P_CSI_RESET_ADMA_I2C3_SDA
> SC_P_CSI_RESET 2
> > +#define SC_P_CSI_RESET_ADMA_SPI1_CS0 SC_P_CSI_RESET
> 3
> > +#define SC_P_CSI_RESET_LSIO_GPIO3_IO03 SC_P_CSI_RESET
> 4
> > +#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT
> SC_P_MIPI_CSI0_MCLK_OUT 0
> > +#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04
> SC_P_MIPI_CSI0_MCLK_OUT 4
> > +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL
> SC_P_MIPI_CSI0_I2C0_SCL 0
> > +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02
> SC_P_MIPI_CSI0_I2C0_SCL 1
> > +#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05
> SC_P_MIPI_CSI0_I2C0_SCL 4
> > +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA
> SC_P_MIPI_CSI0_I2C0_SDA 0
> > +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03
> SC_P_MIPI_CSI0_I2C0_SDA 1
> > +#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06
> SC_P_MIPI_CSI0_I2C0_SDA 4
> > +#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01
> SC_P_MIPI_CSI0_GPIO0_01 0
> > +#define SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA
> SC_P_MIPI_CSI0_GPIO0_01 1
> > +#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07
> SC_P_MIPI_CSI0_GPIO0_01 4
> > +#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00
> SC_P_MIPI_CSI0_GPIO0_00 0
> > +#define SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL
> SC_P_MIPI_CSI0_GPIO0_00 1
> > +#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08
> SC_P_MIPI_CSI0_GPIO0_00 4
> > +#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0
> SC_P_QSPI0A_DATA0 0
> > +#define SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09
> SC_P_QSPI0A_DATA0 4
> > +#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1
> SC_P_QSPI0A_DATA1 0
> > +#define SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10
> SC_P_QSPI0A_DATA1 4
> > +#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2
> SC_P_QSPI0A_DATA2 0
> > +#define SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11
> SC_P_QSPI0A_DATA2 4
> > +#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3
> SC_P_QSPI0A_DATA3 0
> > +#define SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12
> SC_P_QSPI0A_DATA3 4
> > +#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS
> SC_P_QSPI0A_DQS 0
> > +#define SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13
> SC_P_QSPI0A_DQS 4
> > +#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B
> SC_P_QSPI0A_SS0_B 0
> > +#define SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14
> SC_P_QSPI0A_SS0_B 4
> > +#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B
> SC_P_QSPI0A_SS1_B 0
> > +#define SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15
> SC_P_QSPI0A_SS1_B 4
> > +#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK
> SC_P_QSPI0A_SCLK 0
> > +#define SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16
> SC_P_QSPI0A_SCLK 4
> > +#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK
> SC_P_QSPI0B_SCLK 0
> > +#define SC_P_QSPI0B_SCLK_LSIO_QSPI1A_SCLK
> SC_P_QSPI0B_SCLK 1
> > +#define SC_P_QSPI0B_SCLK_LSIO_KPP0_COL0
> SC_P_QSPI0B_SCLK 2
> > +#define SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17
> SC_P_QSPI0B_SCLK 4
> > +#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0
> SC_P_QSPI0B_DATA0 0
> > +#define SC_P_QSPI0B_DATA0_LSIO_QSPI1A_DATA0
> SC_P_QSPI0B_DATA0 1
> > +#define SC_P_QSPI0B_DATA0_LSIO_KPP0_COL1
> SC_P_QSPI0B_DATA0 2
> > +#define SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18
> SC_P_QSPI0B_DATA0 4
> > +#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1
> SC_P_QSPI0B_DATA1 0
> > +#define SC_P_QSPI0B_DATA1_LSIO_QSPI1A_DATA1
> SC_P_QSPI0B_DATA1 1
> > +#define SC_P_QSPI0B_DATA1_LSIO_KPP0_COL2
> SC_P_QSPI0B_DATA1 2
> > +#define SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19
> SC_P_QSPI0B_DATA1 4
> > +#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2
> SC_P_QSPI0B_DATA2 0
> > +#define SC_P_QSPI0B_DATA2_LSIO_QSPI1A_DATA2
> SC_P_QSPI0B_DATA2 1
> > +#define SC_P_QSPI0B_DATA2_LSIO_KPP0_COL3
> SC_P_QSPI0B_DATA2 2
> > +#define SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20
> SC_P_QSPI0B_DATA2 4
> > +#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3
> SC_P_QSPI0B_DATA3 0
> > +#define SC_P_QSPI0B_DATA3_LSIO_QSPI1A_DATA3
> SC_P_QSPI0B_DATA3 1
> > +#define SC_P_QSPI0B_DATA3_LSIO_KPP0_ROW0
> SC_P_QSPI0B_DATA3 2
> > +#define SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21
> SC_P_QSPI0B_DATA3 4
> > +#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS
> SC_P_QSPI0B_DQS 0
> > +#define SC_P_QSPI0B_DQS_LSIO_QSPI1A_DQS
> SC_P_QSPI0B_DQS 1
> > +#define SC_P_QSPI0B_DQS_LSIO_KPP0_ROW1
> SC_P_QSPI0B_DQS 2
> > +#define SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22
> SC_P_QSPI0B_DQS 4
> > +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B
> SC_P_QSPI0B_SS0_B 0
> > +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B
> SC_P_QSPI0B_SS0_B 1
> > +#define SC_P_QSPI0B_SS0_B_LSIO_KPP0_ROW2
> SC_P_QSPI0B_SS0_B 2
> > +#define SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23
> SC_P_QSPI0B_SS0_B 4
> > +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B
> SC_P_QSPI0B_SS1_B 0
> > +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B
> SC_P_QSPI0B_SS1_B 1
> > +#define SC_P_QSPI0B_SS1_B_LSIO_KPP0_ROW3
> SC_P_QSPI0B_SS1_B 2
> > +#define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24
> SC_P_QSPI0B_SS1_B 4
> > +
> > +#endif /* _SC_PADS_H */
> > --
> > 2.7.4
> >
> > --
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^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 5/6] dt-bindings: pinctrl: add imx8qxp pinctrl binding doc
@ 2018-05-02 18:07 ` A.s. Dong
0 siblings, 0 replies; 36+ messages in thread
From: A.s. Dong @ 2018-05-02 18:07 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Rob Herring [mailto:robh at kernel.org]
> Sent: Tuesday, May 1, 2018 11:58 PM
> To: A.s. Dong <aisheng.dong@nxp.com>
> Cc: linux-gpio at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> linus.walleij at linaro.org; shawnguo at kernel.org; stefan at agner.ch;
> dongas86 at gmail.com; dl-linux-imx <linux-imx@nxp.com>;
> kernel at pengutronix.de; Fabio Estevam <fabio.estevam@nxp.com>; Mark
> Rutland <mark.rutland@arm.com>; devicetree at vger.kernel.org; Fabio
> Estevam <festevam@gmail.com>
> Subject: Re: [PATCH 5/6] dt-bindings: pinctrl: add imx8qxp pinctrl binding doc
>
> On Sat, Apr 28, 2018 at 03:01:52AM +0800, Dong Aisheng wrote:
> > Add imx8qxp pinctrl binding doc.
> >
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: Mark Rutland <mark.rutland@arm.com>
> > Cc: devicetree at vger.kernel.org
> > Cc: Linus Walleij <linus.walleij@linaro.org>
> > Cc: Shawn Guo <shawnguo@kernel.org>
> > Cc: Fabio Estevam <festevam@gmail.com>
> > Cc: Stefan Agner <stefan@agner.ch>
> > Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> > ---
> > Note: there's a checkpatch error as follows:
> > ERROR: Macros with complex values should be enclosed in parentheses
> > +#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B
> SC_P_PCIE_CTRL0_PERST_B 0
> >
> > However, this is the intended format. Seems checkpatch did not recognize
> > it well. Not sure if we could accept it.
> > ---
> > .../bindings/pinctrl/fsl,imx8qxp-pinctrl.txt | 39 ++
> > include/dt-bindings/pinctrl/pads-imx8qxp.h | 751
> +++++++++++++++++++++
> > 2 files changed, 790 insertions(+)
> > create mode 100644
> Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt
> > create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h
> >
> > diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-
> pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-
> pinctrl.txt
> > new file mode 100644
> > index 0000000..62c0f55
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8qxp-pinctrl.txt
> > @@ -0,0 +1,39 @@
> > +* NXP i.MX8QXP IOMUX Controller
> > +
> > +MX8QXP contains a system controller that is responsible for controlling
> > +the pad setting of the IPs that are present. Communication between the
> > +host processor running an OS and the system controller happens through
> > +a SCU protocol.
> > +
> > +Please also refer to fsl,imx-pinctrl.txt in this directory for i.MX common
> > +pinctrl binding.
> > +
> > +=== Pin Controller Node ===
> > +
> > +Required properties:
> > +- compatible: "fsl,imx8qxp-iomuxc"
>
> How is this block accessed?
>
> I see the answer in the dts is the SCU. Is this really a IOMUXC as
> defined by prior i.MX chips if it is hidden behind firmware?
>
Yes, it's just controlled by SCU firmware now and accessed via
SCU firmware call (API).
> > +
> > +=== Pin Configuration Node ===
> > +- fsl,pins: Each entry consists of 3 integers which represents the mux
> and
> > + config setting for one pin. The first 2 integers <pin_id
> mux_mode>
> > + are specified using a PIN_FUNC_ID macro, which can be
> found
> > + in <dt-bindings/pinctrl/pads-imx8qxp.h>. The last integer
> CONFIG
> > + is the pad setting value like pull-up on this pin.
> > + Please refer to i.MX8QXP Reference Manual for detailed
> > + CONFIG settings.
> > +
> > +Examples:
> > +#include <dt-bindings/pinctrl/pads-imx8qxp.h>
> > +
> > +/* Pin Controller Node */
> > +iomuxc: iomuxc {
>
> pinctrl {
>
Yes.
> > + compatible = "fsl,imx8qxp-iomuxc";
> > +
> > + /* Pin Configuration Node */
> > + pinctrl_lpuart0: lpuart0grp {
> > + fsl,pins = <
> > + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
> > + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
> > + >;
> > + };
> > +};
> > diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-
> bindings/pinctrl/pads-imx8qxp.h
> > new file mode 100644
> > index 0000000..8f477c3
> > --- /dev/null
> > +++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h
> > @@ -0,0 +1,751 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> > + * Copyright 2017~2018 NXP
> > + */
> > +
> > +#ifndef _SC_PADS_H
> > +#define _SC_PADS_H
> > +
> > +/* pin id */
> > +#define SC_P_PCIE_CTRL0_PERST_B 0
> > +#define SC_P_PCIE_CTRL0_CLKREQ_B 1
> > +#define SC_P_PCIE_CTRL0_WAKE_B 2
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3
> > +#define SC_P_USB_SS3_TC0 4
> > +#define SC_P_USB_SS3_TC1 5
> > +#define SC_P_USB_SS3_TC2 6
> > +#define SC_P_USB_SS3_TC3 7
> > +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8
> > +#define SC_P_EMMC0_CLK 9
> > +#define SC_P_EMMC0_CMD 10
> > +#define SC_P_EMMC0_DATA0 11
> > +#define SC_P_EMMC0_DATA1 12
> > +#define SC_P_EMMC0_DATA2 13
> > +#define SC_P_EMMC0_DATA3 14
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15
> > +#define SC_P_EMMC0_DATA4 16
> > +#define SC_P_EMMC0_DATA5 17
> > +#define SC_P_EMMC0_DATA6 18
> > +#define SC_P_EMMC0_DATA7 19
> > +#define SC_P_EMMC0_STROBE 20
> > +#define SC_P_EMMC0_RESET_B 21
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22
> > +#define SC_P_USDHC1_RESET_B 23
> > +#define SC_P_USDHC1_VSELECT 24
> > +#define SC_P_CTL_NAND_RE_P_N 25
> > +#define SC_P_USDHC1_WP 26
> > +#define SC_P_USDHC1_CD_B 27
> > +#define SC_P_CTL_NAND_DQS_P_N 28
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29
> > +#define SC_P_USDHC1_CLK 30
> > +#define SC_P_USDHC1_CMD 31
> > +#define SC_P_USDHC1_DATA0 32
> > +#define SC_P_USDHC1_DATA1 33
> > +#define SC_P_USDHC1_DATA2 34
> > +#define SC_P_USDHC1_DATA3 35
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36
> > +#define SC_P_ENET0_RGMII_TXC 37
> > +#define SC_P_ENET0_RGMII_TX_CTL 38
> > +#define SC_P_ENET0_RGMII_TXD0 39
> > +#define SC_P_ENET0_RGMII_TXD1 40
> > +#define SC_P_ENET0_RGMII_TXD2 41
> > +#define SC_P_ENET0_RGMII_TXD3 42
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43
> > +#define SC_P_ENET0_RGMII_RXC 44
> > +#define SC_P_ENET0_RGMII_RX_CTL 45
> > +#define SC_P_ENET0_RGMII_RXD0 46
> > +#define SC_P_ENET0_RGMII_RXD1 47
> > +#define SC_P_ENET0_RGMII_RXD2 48
> > +#define SC_P_ENET0_RGMII_RXD3 49
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50
> > +#define SC_P_ENET0_REFCLK_125M_25M 51
> > +#define SC_P_ENET0_MDIO 52
> > +#define SC_P_ENET0_MDC 53
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54
> > +#define SC_P_ESAI0_FSR 55
> > +#define SC_P_ESAI0_FST 56
> > +#define SC_P_ESAI0_SCKR 57
> > +#define SC_P_ESAI0_SCKT 58
> > +#define SC_P_ESAI0_TX0 59
> > +#define SC_P_ESAI0_TX1 60
> > +#define SC_P_ESAI0_TX2_RX3 61
> > +#define SC_P_ESAI0_TX3_RX2 62
> > +#define SC_P_ESAI0_TX4_RX1 63
> > +#define SC_P_ESAI0_TX5_RX0 64
> > +#define SC_P_SPDIF0_RX 65
> > +#define SC_P_SPDIF0_TX 66
> > +#define SC_P_SPDIF0_EXT_CLK 67
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68
> > +#define SC_P_SPI3_SCK 69
> > +#define SC_P_SPI3_SDO 70
> > +#define SC_P_SPI3_SDI 71
> > +#define SC_P_SPI3_CS0 72
> > +#define SC_P_SPI3_CS1 73
> > +#define SC_P_MCLK_IN1 74
> > +#define SC_P_MCLK_IN0 75
> > +#define SC_P_MCLK_OUT0 76
> > +#define SC_P_UART1_TX 77
> > +#define SC_P_UART1_RX 78
> > +#define SC_P_UART1_RTS_B 79
> > +#define SC_P_UART1_CTS_B 80
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81
> > +#define SC_P_SAI0_TXD 82
> > +#define SC_P_SAI0_TXC 83
> > +#define SC_P_SAI0_RXD 84
> > +#define SC_P_SAI0_TXFS 85
> > +#define SC_P_SAI1_RXD 86
> > +#define SC_P_SAI1_RXC 87
> > +#define SC_P_SAI1_RXFS 88
> > +#define SC_P_SPI2_CS0 89
> > +#define SC_P_SPI2_SDO 90
> > +#define SC_P_SPI2_SDI 91
> > +#define SC_P_SPI2_SCK 92
> > +#define SC_P_SPI0_SCK 93
> > +#define SC_P_SPI0_SDI 94
> > +#define SC_P_SPI0_SDO 95
> > +#define SC_P_SPI0_CS1 96
> > +#define SC_P_SPI0_CS0 97
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98
> > +#define SC_P_ADC_IN1 99
> > +#define SC_P_ADC_IN0 100
> > +#define SC_P_ADC_IN3 101
> > +#define SC_P_ADC_IN2 102
> > +#define SC_P_ADC_IN5 103
> > +#define SC_P_ADC_IN4 104
> > +#define SC_P_FLEXCAN0_RX 105
> > +#define SC_P_FLEXCAN0_TX 106
> > +#define SC_P_FLEXCAN1_RX 107
> > +#define SC_P_FLEXCAN1_TX 108
> > +#define SC_P_FLEXCAN2_RX 109
> > +#define SC_P_FLEXCAN2_TX 110
> > +#define SC_P_UART0_RX 111
> > +#define SC_P_UART0_TX 112
> > +#define SC_P_UART2_TX 113
> > +#define SC_P_UART2_RX 114
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115
> > +#define SC_P_MIPI_DSI0_I2C0_SCL 116
> > +#define SC_P_MIPI_DSI0_I2C0_SDA 117
> > +#define SC_P_MIPI_DSI0_GPIO0_00 118
> > +#define SC_P_MIPI_DSI0_GPIO0_01 119
> > +#define SC_P_MIPI_DSI1_I2C0_SCL 120
> > +#define SC_P_MIPI_DSI1_I2C0_SDA 121
> > +#define SC_P_MIPI_DSI1_GPIO0_00 122
> > +#define SC_P_MIPI_DSI1_GPIO0_01 123
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124
> > +#define SC_P_JTAG_TRST_B 125
> > +#define SC_P_PMIC_I2C_SCL 126
> > +#define SC_P_PMIC_I2C_SDA 127
> > +#define SC_P_PMIC_INT_B 128
> > +#define SC_P_SCU_GPIO0_00 129
> > +#define SC_P_SCU_GPIO0_01 130
> > +#define SC_P_SCU_PMIC_STANDBY 131
> > +#define SC_P_SCU_BOOT_MODE0 132
> > +#define SC_P_SCU_BOOT_MODE1 133
> > +#define SC_P_SCU_BOOT_MODE2 134
> > +#define SC_P_SCU_BOOT_MODE3 135
> > +#define SC_P_CSI_D00 136
> > +#define SC_P_CSI_D01 137
> > +#define SC_P_CSI_D02 138
> > +#define SC_P_CSI_D03 139
> > +#define SC_P_CSI_D04 140
> > +#define SC_P_CSI_D05 141
> > +#define SC_P_CSI_D06 142
> > +#define SC_P_CSI_D07 143
> > +#define SC_P_CSI_HSYNC 144
> > +#define SC_P_CSI_VSYNC 145
> > +#define SC_P_CSI_PCLK 146
> > +#define SC_P_CSI_MCLK 147
> > +#define SC_P_CSI_EN 148
> > +#define SC_P_CSI_RESET 149
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150
> > +#define SC_P_MIPI_CSI0_MCLK_OUT 151
> > +#define SC_P_MIPI_CSI0_I2C0_SCL 152
> > +#define SC_P_MIPI_CSI0_I2C0_SDA 153
> > +#define SC_P_MIPI_CSI0_GPIO0_01 154
> > +#define SC_P_MIPI_CSI0_GPIO0_00 155
> > +#define SC_P_QSPI0A_DATA0 156
> > +#define SC_P_QSPI0A_DATA1 157
> > +#define SC_P_QSPI0A_DATA2 158
> > +#define SC_P_QSPI0A_DATA3 159
> > +#define SC_P_QSPI0A_DQS 160
> > +#define SC_P_QSPI0A_SS0_B 161
> > +#define SC_P_QSPI0A_SS1_B 162
> > +#define SC_P_QSPI0A_SCLK 163
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164
> > +#define SC_P_QSPI0B_SCLK 165
> > +#define SC_P_QSPI0B_DATA0 166
> > +#define SC_P_QSPI0B_DATA1 167
> > +#define SC_P_QSPI0B_DATA2 168
> > +#define SC_P_QSPI0B_DATA3 169
> > +#define SC_P_QSPI0B_DQS 170
> > +#define SC_P_QSPI0B_SS0_B 171
> > +#define SC_P_QSPI0B_SS1_B 172
> > +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173
> > +
> > +/*
> > + * format: <pin_id mux_mode>
> > + */
> > +#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B
> SC_P_PCIE_CTRL0_PERST_B 0
> > +#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00
> SC_P_PCIE_CTRL0_PERST_B 4
> > +#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B
> SC_P_PCIE_CTRL0_CLKREQ_B 0
> > +#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01
> SC_P_PCIE_CTRL0_CLKREQ_B 4
> > +#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B
> SC_P_PCIE_CTRL0_WAKE_B 0
> > +#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02
> SC_P_PCIE_CTRL0_WAKE_B 4
> > +#define SC_P_USB_SS3_TC0_ADMA_I2C1_SCL
> SC_P_USB_SS3_TC0 0
> > +#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR
> SC_P_USB_SS3_TC0 1
> > +#define SC_P_USB_SS3_TC0_CONN_USB_OTG2_PWR
> SC_P_USB_SS3_TC0 2
> > +#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03
> SC_P_USB_SS3_TC0 4
> > +#define SC_P_USB_SS3_TC1_ADMA_I2C1_SCL
> SC_P_USB_SS3_TC1 0
> > +#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR
> SC_P_USB_SS3_TC1 1
> > +#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04
> SC_P_USB_SS3_TC1 4
> > +#define SC_P_USB_SS3_TC2_ADMA_I2C1_SDA
> SC_P_USB_SS3_TC2 0
> > +#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC
> SC_P_USB_SS3_TC2 1
> > +#define SC_P_USB_SS3_TC2_CONN_USB_OTG2_OC
> SC_P_USB_SS3_TC2 2
> > +#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05
> SC_P_USB_SS3_TC2 4
> > +#define SC_P_USB_SS3_TC3_ADMA_I2C1_SDA
> SC_P_USB_SS3_TC3 0
> > +#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC
> SC_P_USB_SS3_TC3 1
> > +#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06
> SC_P_USB_SS3_TC3 4
> > +#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK
> SC_P_EMMC0_CLK 0
> > +#define SC_P_EMMC0_CLK_CONN_NAND_READY_B
> SC_P_EMMC0_CLK 1
> > +#define SC_P_EMMC0_CLK_LSIO_GPIO4_IO07
> SC_P_EMMC0_CLK 4
> > +#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD
> SC_P_EMMC0_CMD 0
> > +#define SC_P_EMMC0_CMD_CONN_NAND_DQS
> SC_P_EMMC0_CMD 1
> > +#define SC_P_EMMC0_CMD_LSIO_GPIO4_IO08
> SC_P_EMMC0_CMD 4
> > +#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0
> SC_P_EMMC0_DATA0 0
> > +#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00
> SC_P_EMMC0_DATA0 1
> > +#define SC_P_EMMC0_DATA0_LSIO_GPIO4_IO09
> SC_P_EMMC0_DATA0 4
> > +#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1
> SC_P_EMMC0_DATA1 0
> > +#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01
> SC_P_EMMC0_DATA1 1
> > +#define SC_P_EMMC0_DATA1_LSIO_GPIO4_IO10
> SC_P_EMMC0_DATA1 4
> > +#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2
> SC_P_EMMC0_DATA2 0
> > +#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02
> SC_P_EMMC0_DATA2 1
> > +#define SC_P_EMMC0_DATA2_LSIO_GPIO4_IO11
> SC_P_EMMC0_DATA2 4
> > +#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3
> SC_P_EMMC0_DATA3 0
> > +#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03
> SC_P_EMMC0_DATA3 1
> > +#define SC_P_EMMC0_DATA3_LSIO_GPIO4_IO12
> SC_P_EMMC0_DATA3 4
> > +#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4
> SC_P_EMMC0_DATA4 0
> > +#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04
> SC_P_EMMC0_DATA4 1
> > +#define SC_P_EMMC0_DATA4_CONN_EMMC0_WP
> SC_P_EMMC0_DATA4 3
> > +#define SC_P_EMMC0_DATA4_LSIO_GPIO4_IO13
> SC_P_EMMC0_DATA4 4
> > +#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5
> SC_P_EMMC0_DATA5 0
> > +#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05
> SC_P_EMMC0_DATA5 1
> > +#define SC_P_EMMC0_DATA5_CONN_EMMC0_VSELECT
> SC_P_EMMC0_DATA5 3
> > +#define SC_P_EMMC0_DATA5_LSIO_GPIO4_IO14
> SC_P_EMMC0_DATA5 4
> > +#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6
> SC_P_EMMC0_DATA6 0
> > +#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06
> SC_P_EMMC0_DATA6 1
> > +#define SC_P_EMMC0_DATA6_CONN_MLB_CLK
> SC_P_EMMC0_DATA6 3
> > +#define SC_P_EMMC0_DATA6_LSIO_GPIO4_IO15
> SC_P_EMMC0_DATA6 4
> > +#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7
> SC_P_EMMC0_DATA7 0
> > +#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07
> SC_P_EMMC0_DATA7 1
> > +#define SC_P_EMMC0_DATA7_CONN_MLB_SIG
> SC_P_EMMC0_DATA7 3
> > +#define SC_P_EMMC0_DATA7_LSIO_GPIO4_IO16
> SC_P_EMMC0_DATA7 4
> > +#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE
> SC_P_EMMC0_STROBE 0
> > +#define SC_P_EMMC0_STROBE_CONN_NAND_CLE
> SC_P_EMMC0_STROBE 1
> > +#define SC_P_EMMC0_STROBE_CONN_MLB_DATA
> SC_P_EMMC0_STROBE 3
> > +#define SC_P_EMMC0_STROBE_LSIO_GPIO4_IO17
> SC_P_EMMC0_STROBE 4
> > +#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B
> SC_P_EMMC0_RESET_B 0
> > +#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B
> SC_P_EMMC0_RESET_B 1
> > +#define SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18
> SC_P_EMMC0_RESET_B 4
> > +#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B
> SC_P_USDHC1_RESET_B 0
> > +#define SC_P_USDHC1_RESET_B_CONN_NAND_RE_N
> SC_P_USDHC1_RESET_B 1
> > +#define SC_P_USDHC1_RESET_B_ADMA_SPI2_SCK
> SC_P_USDHC1_RESET_B 2
> > +#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19
> SC_P_USDHC1_RESET_B 4
> > +#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT
> SC_P_USDHC1_VSELECT 0
> > +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_P
> SC_P_USDHC1_VSELECT 1
> > +#define SC_P_USDHC1_VSELECT_ADMA_SPI2_SDO
> SC_P_USDHC1_VSELECT 2
> > +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_B
> SC_P_USDHC1_VSELECT 3
> > +#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO20
> SC_P_USDHC1_VSELECT 4
> > +#define SC_P_USDHC1_WP_CONN_USDHC1_WP
> SC_P_USDHC1_WP 0
> > +#define SC_P_USDHC1_WP_CONN_NAND_DQS_N
> SC_P_USDHC1_WP 1
> > +#define SC_P_USDHC1_WP_ADMA_SPI2_SDI
> SC_P_USDHC1_WP 2
> > +#define SC_P_USDHC1_WP_LSIO_GPIO4_IO21
> SC_P_USDHC1_WP 4
> > +#define SC_P_USDHC1_CD_B_CONN_USDHC1_CD_B
> SC_P_USDHC1_CD_B 0
> > +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS_P
> SC_P_USDHC1_CD_B 1
> > +#define SC_P_USDHC1_CD_B_ADMA_SPI2_CS0
> SC_P_USDHC1_CD_B 2
> > +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS
> SC_P_USDHC1_CD_B 3
> > +#define SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22
> SC_P_USDHC1_CD_B 4
> > +#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK
> SC_P_USDHC1_CLK 0
> > +#define SC_P_USDHC1_CLK_ADMA_UART3_RX
> SC_P_USDHC1_CLK 2
> > +#define SC_P_USDHC1_CLK_LSIO_GPIO4_IO23
> SC_P_USDHC1_CLK 4
> > +#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD
> SC_P_USDHC1_CMD 0
> > +#define SC_P_USDHC1_CMD_CONN_NAND_CE0_B
> SC_P_USDHC1_CMD 1
> > +#define SC_P_USDHC1_CMD_ADMA_MQS_R
> SC_P_USDHC1_CMD 2
> > +#define SC_P_USDHC1_CMD_LSIO_GPIO4_IO24
> SC_P_USDHC1_CMD 4
> > +#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0
> SC_P_USDHC1_DATA0 0
> > +#define SC_P_USDHC1_DATA0_CONN_NAND_CE1_B
> SC_P_USDHC1_DATA0 1
> > +#define SC_P_USDHC1_DATA0_ADMA_MQS_L
> SC_P_USDHC1_DATA0 2
> > +#define SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25
> SC_P_USDHC1_DATA0 4
> > +#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1
> SC_P_USDHC1_DATA1 0
> > +#define SC_P_USDHC1_DATA1_CONN_NAND_RE_B
> SC_P_USDHC1_DATA1 1
> > +#define SC_P_USDHC1_DATA1_ADMA_UART3_TX
> SC_P_USDHC1_DATA1 2
> > +#define SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26
> SC_P_USDHC1_DATA1 4
> > +#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2
> SC_P_USDHC1_DATA2 0
> > +#define SC_P_USDHC1_DATA2_CONN_NAND_WE_B
> SC_P_USDHC1_DATA2 1
> > +#define SC_P_USDHC1_DATA2_ADMA_UART3_CTS_B
> SC_P_USDHC1_DATA2 2
> > +#define SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27
> SC_P_USDHC1_DATA2 4
> > +#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3
> SC_P_USDHC1_DATA3 0
> > +#define SC_P_USDHC1_DATA3_CONN_NAND_ALE
> SC_P_USDHC1_DATA3 1
> > +#define SC_P_USDHC1_DATA3_ADMA_UART3_RTS_B
> SC_P_USDHC1_DATA3 2
> > +#define SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28
> SC_P_USDHC1_DATA3 4
> > +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC
> SC_P_ENET0_RGMII_TXC 0
> > +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT
> SC_P_ENET0_RGMII_TXC 1
> > +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN
> SC_P_ENET0_RGMII_TXC 2
> > +#define SC_P_ENET0_RGMII_TXC_CONN_NAND_CE1_B
> SC_P_ENET0_RGMII_TXC 3
> > +#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29
> SC_P_ENET0_RGMII_TXC 4
> > +#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL
> SC_P_ENET0_RGMII_TX_CTL 0
> > +#define SC_P_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B
> SC_P_ENET0_RGMII_TX_CTL 3
> > +#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30
> SC_P_ENET0_RGMII_TX_CTL 4
> > +#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0
> SC_P_ENET0_RGMII_TXD0 0
> > +#define SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT
> SC_P_ENET0_RGMII_TXD0 3
> > +#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31
> SC_P_ENET0_RGMII_TXD0 4
> > +#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1
> SC_P_ENET0_RGMII_TXD1 0
> > +#define SC_P_ENET0_RGMII_TXD1_CONN_USDHC1_WP
> SC_P_ENET0_RGMII_TXD1 3
> > +#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00
> SC_P_ENET0_RGMII_TXD1 4
> > +#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2
> SC_P_ENET0_RGMII_TXD2 0
> > +#define SC_P_ENET0_RGMII_TXD2_CONN_MLB_CLK
> SC_P_ENET0_RGMII_TXD2 1
> > +#define SC_P_ENET0_RGMII_TXD2_CONN_NAND_CE0_B
> SC_P_ENET0_RGMII_TXD2 2
> > +#define SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B
> SC_P_ENET0_RGMII_TXD2 3
> > +#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01
> SC_P_ENET0_RGMII_TXD2 4
> > +#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3
> SC_P_ENET0_RGMII_TXD3 0
> > +#define SC_P_ENET0_RGMII_TXD3_CONN_MLB_SIG
> SC_P_ENET0_RGMII_TXD3 1
> > +#define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B
> SC_P_ENET0_RGMII_TXD3 2
> > +#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02
> SC_P_ENET0_RGMII_TXD3 4
> > +#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC
> SC_P_ENET0_RGMII_RXC 0
> > +#define SC_P_ENET0_RGMII_RXC_CONN_MLB_DATA
> SC_P_ENET0_RGMII_RXC 1
> > +#define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B
> SC_P_ENET0_RGMII_RXC 2
> > +#define SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK
> SC_P_ENET0_RGMII_RXC 3
> > +#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03
> SC_P_ENET0_RGMII_RXC 4
> > +#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL
> SC_P_ENET0_RGMII_RX_CTL 0
> > +#define SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD
> SC_P_ENET0_RGMII_RX_CTL 3
> > +#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04
> SC_P_ENET0_RGMII_RX_CTL 4
> > +#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0
> SC_P_ENET0_RGMII_RXD0 0
> > +#define SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0
> SC_P_ENET0_RGMII_RXD0 3
> > +#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05
> SC_P_ENET0_RGMII_RXD0 4
> > +#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1
> SC_P_ENET0_RGMII_RXD1 0
> > +#define SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1
> SC_P_ENET0_RGMII_RXD1 3
> > +#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06
> SC_P_ENET0_RGMII_RXD1 4
> > +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2
> SC_P_ENET0_RGMII_RXD2 0
> > +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER
> SC_P_ENET0_RGMII_RXD2 1
> > +#define SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2
> SC_P_ENET0_RGMII_RXD2 3
> > +#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07
> SC_P_ENET0_RGMII_RXD2 4
> > +#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3
> SC_P_ENET0_RGMII_RXD3 0
> > +#define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE
> SC_P_ENET0_RGMII_RXD3 2
> > +#define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3
> SC_P_ENET0_RGMII_RXD3 3
> > +#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08
> SC_P_ENET0_RGMII_RXD3 4
> > +#define
> SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M
> SC_P_ENET0_REFCLK_125M_25M 0
> > +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS
> SC_P_ENET0_REFCLK_125M_25M 1
> > +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS
> SC_P_ENET0_REFCLK_125M_25M 2
> > +#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09
> SC_P_ENET0_REFCLK_125M_25M 4
> > +#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO
> SC_P_ENET0_MDIO 0
> > +#define SC_P_ENET0_MDIO_ADMA_I2C3_SDA
> SC_P_ENET0_MDIO 1
> > +#define SC_P_ENET0_MDIO_CONN_ENET1_MDIO
> SC_P_ENET0_MDIO 2
> > +#define SC_P_ENET0_MDIO_LSIO_GPIO5_IO10
> SC_P_ENET0_MDIO 4
> > +#define SC_P_ENET0_MDC_CONN_ENET0_MDC
> SC_P_ENET0_MDC 0
> > +#define SC_P_ENET0_MDC_ADMA_I2C3_SCL
> SC_P_ENET0_MDC 1
> > +#define SC_P_ENET0_MDC_CONN_ENET1_MDC
> SC_P_ENET0_MDC 2
> > +#define SC_P_ENET0_MDC_LSIO_GPIO5_IO11
> SC_P_ENET0_MDC 4
> > +#define SC_P_ESAI0_FSR_ADMA_ESAI0_FSR
> SC_P_ESAI0_FSR 0
> > +#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT
> SC_P_ESAI0_FSR 1
> > +#define SC_P_ESAI0_FSR_ADMA_LCDIF_D00
> SC_P_ESAI0_FSR 2
> > +#define SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC
> SC_P_ESAI0_FSR 3
> > +#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN
> SC_P_ESAI0_FSR 4
> > +#define SC_P_ESAI0_FST_ADMA_ESAI0_FST
> SC_P_ESAI0_FST 0
> > +#define SC_P_ESAI0_FST_CONN_MLB_CLK
> SC_P_ESAI0_FST 1
> > +#define SC_P_ESAI0_FST_ADMA_LCDIF_D01
> SC_P_ESAI0_FST 2
> > +#define SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2
> SC_P_ESAI0_FST 3
> > +#define SC_P_ESAI0_FST_LSIO_GPIO0_IO01 SC_P_ESAI0_FST
> 4
> > +#define SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR
> SC_P_ESAI0_SCKR 0
> > +#define SC_P_ESAI0_SCKR_ADMA_LCDIF_D02
> SC_P_ESAI0_SCKR 2
> > +#define SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL
> SC_P_ESAI0_SCKR 3
> > +#define SC_P_ESAI0_SCKR_LSIO_GPIO0_IO02
> SC_P_ESAI0_SCKR 4
> > +#define SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT
> SC_P_ESAI0_SCKT 0
> > +#define SC_P_ESAI0_SCKT_CONN_MLB_SIG
> SC_P_ESAI0_SCKT 1
> > +#define SC_P_ESAI0_SCKT_ADMA_LCDIF_D03
> SC_P_ESAI0_SCKT 2
> > +#define SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3
> SC_P_ESAI0_SCKT 3
> > +#define SC_P_ESAI0_SCKT_LSIO_GPIO0_IO03
> SC_P_ESAI0_SCKT 4
> > +#define SC_P_ESAI0_TX0_ADMA_ESAI0_TX0
> SC_P_ESAI0_TX0 0
> > +#define SC_P_ESAI0_TX0_CONN_MLB_DATA
> SC_P_ESAI0_TX0 1
> > +#define SC_P_ESAI0_TX0_ADMA_LCDIF_D04
> SC_P_ESAI0_TX0 2
> > +#define SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC
> SC_P_ESAI0_TX0 3
> > +#define SC_P_ESAI0_TX0_LSIO_GPIO0_IO04
> SC_P_ESAI0_TX0 4
> > +#define SC_P_ESAI0_TX1_ADMA_ESAI0_TX1
> SC_P_ESAI0_TX1 0
> > +#define SC_P_ESAI0_TX1_ADMA_LCDIF_D05
> SC_P_ESAI0_TX1 2
> > +#define SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3
> SC_P_ESAI0_TX1 3
> > +#define SC_P_ESAI0_TX1_LSIO_GPIO0_IO05
> SC_P_ESAI0_TX1 4
> > +#define SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3
> SC_P_ESAI0_TX2_RX3 0
> > +#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER
> SC_P_ESAI0_TX2_RX3 1
> > +#define SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06
> SC_P_ESAI0_TX2_RX3 2
> > +#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2
> SC_P_ESAI0_TX2_RX3 3
> > +#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO0_IO06
> SC_P_ESAI0_TX2_RX3 4
> > +#define SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2
> SC_P_ESAI0_TX3_RX2 0
> > +#define SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07
> SC_P_ESAI0_TX3_RX2 2
> > +#define SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1
> SC_P_ESAI0_TX3_RX2 3
> > +#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO0_IO07
> SC_P_ESAI0_TX3_RX2 4
> > +#define SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1
> SC_P_ESAI0_TX4_RX1 0
> > +#define SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08
> SC_P_ESAI0_TX4_RX1 2
> > +#define SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0
> SC_P_ESAI0_TX4_RX1 3
> > +#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO0_IO08
> SC_P_ESAI0_TX4_RX1 4
> > +#define SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0
> SC_P_ESAI0_TX5_RX0 0
> > +#define SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09
> SC_P_ESAI0_TX5_RX0 2
> > +#define SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1
> SC_P_ESAI0_TX5_RX0 3
> > +#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO0_IO09
> SC_P_ESAI0_TX5_RX0 4
> > +#define SC_P_SPDIF0_RX_ADMA_SPDIF0_RX
> SC_P_SPDIF0_RX 0
> > +#define SC_P_SPDIF0_RX_ADMA_MQS_R
> SC_P_SPDIF0_RX 1
> > +#define SC_P_SPDIF0_RX_ADMA_LCDIF_D10
> SC_P_SPDIF0_RX 2
> > +#define SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0
> SC_P_SPDIF0_RX 3
> > +#define SC_P_SPDIF0_RX_LSIO_GPIO0_IO10
> SC_P_SPDIF0_RX 4
> > +#define SC_P_SPDIF0_TX_ADMA_SPDIF0_TX
> SC_P_SPDIF0_TX 0
> > +#define SC_P_SPDIF0_TX_ADMA_MQS_L
> SC_P_SPDIF0_TX 1
> > +#define SC_P_SPDIF0_TX_ADMA_LCDIF_D11
> SC_P_SPDIF0_TX 2
> > +#define SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL
> SC_P_SPDIF0_TX 3
> > +#define SC_P_SPDIF0_TX_LSIO_GPIO0_IO11
> SC_P_SPDIF0_TX 4
> > +#define SC_P_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK
> SC_P_SPDIF0_EXT_CLK 0
> > +#define SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12
> SC_P_SPDIF0_EXT_CLK 2
> > +#define SC_P_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M
> SC_P_SPDIF0_EXT_CLK 3
> > +#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12
> SC_P_SPDIF0_EXT_CLK 4
> > +#define SC_P_SPI3_SCK_ADMA_SPI3_SCK SC_P_SPI3_SCK
> 0
> > +#define SC_P_SPI3_SCK_ADMA_LCDIF_D13 SC_P_SPI3_SCK
> 2
> > +#define SC_P_SPI3_SCK_LSIO_GPIO0_IO13 SC_P_SPI3_SCK
> 4
> > +#define SC_P_SPI3_SDO_ADMA_SPI3_SDO
> SC_P_SPI3_SDO 0
> > +#define SC_P_SPI3_SDO_ADMA_LCDIF_D14
> SC_P_SPI3_SDO 2
> > +#define SC_P_SPI3_SDO_LSIO_GPIO0_IO14 SC_P_SPI3_SDO
> 4
> > +#define SC_P_SPI3_SDI_ADMA_SPI3_SDI SC_P_SPI3_SDI
> 0
> > +#define SC_P_SPI3_SDI_ADMA_LCDIF_D15 SC_P_SPI3_SDI
> 2
> > +#define SC_P_SPI3_SDI_LSIO_GPIO0_IO15 SC_P_SPI3_SDI
> 4
> > +#define SC_P_SPI3_CS0_ADMA_SPI3_CS0 SC_P_SPI3_CS0
> 0
> > +#define SC_P_SPI3_CS0_ADMA_ACM_MCLK_OUT1
> SC_P_SPI3_CS0 1
> > +#define SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC
> SC_P_SPI3_CS0 2
> > +#define SC_P_SPI3_CS0_LSIO_GPIO0_IO16 SC_P_SPI3_CS0
> 4
> > +#define SC_P_SPI3_CS1_ADMA_SPI3_CS1 SC_P_SPI3_CS1
> 0
> > +#define SC_P_SPI3_CS1_ADMA_I2C3_SCL SC_P_SPI3_CS1
> 1
> > +#define SC_P_SPI3_CS1_ADMA_LCDIF_RESET
> SC_P_SPI3_CS1 2
> > +#define SC_P_SPI3_CS1_ADMA_SPI2_CS0 SC_P_SPI3_CS1
> 3
> > +#define SC_P_SPI3_CS1_ADMA_LCDIF_D16 SC_P_SPI3_CS1
> 4
> > +#define SC_P_MCLK_IN1_ADMA_ACM_MCLK_IN1
> SC_P_MCLK_IN1 0
> > +#define SC_P_MCLK_IN1_ADMA_I2C3_SDA
> SC_P_MCLK_IN1 1
> > +#define SC_P_MCLK_IN1_ADMA_LCDIF_EN
> SC_P_MCLK_IN1 2
> > +#define SC_P_MCLK_IN1_ADMA_SPI2_SCK
> SC_P_MCLK_IN1 3
> > +#define SC_P_MCLK_IN1_ADMA_LCDIF_D17
> SC_P_MCLK_IN1 4
> > +#define SC_P_MCLK_IN0_ADMA_ACM_MCLK_IN0
> SC_P_MCLK_IN0 0
> > +#define SC_P_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK
> SC_P_MCLK_IN0 1
> > +#define SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC
> SC_P_MCLK_IN0 2
> > +#define SC_P_MCLK_IN0_ADMA_SPI2_SDI
> SC_P_MCLK_IN0 3
> > +#define SC_P_MCLK_IN0_LSIO_GPIO0_IO19
> SC_P_MCLK_IN0 4
> > +#define SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0
> SC_P_MCLK_OUT0 0
> > +#define SC_P_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK
> SC_P_MCLK_OUT0 1
> > +#define SC_P_MCLK_OUT0_ADMA_LCDIF_CLK
> SC_P_MCLK_OUT0 2
> > +#define SC_P_MCLK_OUT0_ADMA_SPI2_SDO
> SC_P_MCLK_OUT0 3
> > +#define SC_P_MCLK_OUT0_LSIO_GPIO0_IO20
> SC_P_MCLK_OUT0 4
> > +#define SC_P_UART1_TX_ADMA_UART1_TX
> SC_P_UART1_TX 0
> > +#define SC_P_UART1_TX_LSIO_PWM0_OUT
> SC_P_UART1_TX 1
> > +#define SC_P_UART1_TX_LSIO_GPT0_CAPTURE
> SC_P_UART1_TX 2
> > +#define SC_P_UART1_TX_LSIO_GPIO0_IO21
> SC_P_UART1_TX 4
> > +#define SC_P_UART1_RX_ADMA_UART1_RX
> SC_P_UART1_RX 0
> > +#define SC_P_UART1_RX_LSIO_PWM1_OUT
> SC_P_UART1_RX 1
> > +#define SC_P_UART1_RX_LSIO_GPT0_COMPARE
> SC_P_UART1_RX 2
> > +#define SC_P_UART1_RX_LSIO_GPT1_CLK SC_P_UART1_RX
> 3
> > +#define SC_P_UART1_RX_LSIO_GPIO0_IO22
> SC_P_UART1_RX 4
> > +#define SC_P_UART1_RTS_B_ADMA_UART1_RTS_B
> SC_P_UART1_RTS_B 0
> > +#define SC_P_UART1_RTS_B_LSIO_PWM2_OUT
> SC_P_UART1_RTS_B 1
> > +#define SC_P_UART1_RTS_B_ADMA_LCDIF_D16
> SC_P_UART1_RTS_B 2
> > +#define SC_P_UART1_RTS_B_LSIO_GPT1_CAPTURE
> SC_P_UART1_RTS_B 3
> > +#define SC_P_UART1_RTS_B_LSIO_GPT0_CLK
> SC_P_UART1_RTS_B 4
> > +#define SC_P_UART1_CTS_B_ADMA_UART1_CTS_B
> SC_P_UART1_CTS_B 0
> > +#define SC_P_UART1_CTS_B_LSIO_PWM3_OUT
> SC_P_UART1_CTS_B 1
> > +#define SC_P_UART1_CTS_B_ADMA_LCDIF_D17
> SC_P_UART1_CTS_B 2
> > +#define SC_P_UART1_CTS_B_LSIO_GPT1_COMPARE
> SC_P_UART1_CTS_B 3
> > +#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO24
> SC_P_UART1_CTS_B 4
> > +#define SC_P_SAI0_TXD_ADMA_SAI0_TXD SC_P_SAI0_TXD
> 0
> > +#define SC_P_SAI0_TXD_ADMA_SAI1_RXC SC_P_SAI0_TXD
> 1
> > +#define SC_P_SAI0_TXD_ADMA_SPI1_SDO SC_P_SAI0_TXD
> 2
> > +#define SC_P_SAI0_TXD_ADMA_LCDIF_D18
> SC_P_SAI0_TXD 3
> > +#define SC_P_SAI0_TXD_LSIO_GPIO0_IO25 SC_P_SAI0_TXD
> 4
> > +#define SC_P_SAI0_TXC_ADMA_SAI0_TXC SC_P_SAI0_TXC
> 0
> > +#define SC_P_SAI0_TXC_ADMA_SAI1_TXD SC_P_SAI0_TXC
> 1
> > +#define SC_P_SAI0_TXC_ADMA_SPI1_SDI SC_P_SAI0_TXC
> 2
> > +#define SC_P_SAI0_TXC_ADMA_LCDIF_D19 SC_P_SAI0_TXC
> 3
> > +#define SC_P_SAI0_TXC_LSIO_GPIO0_IO26 SC_P_SAI0_TXC
> 4
> > +#define SC_P_SAI0_RXD_ADMA_SAI0_RXD
> SC_P_SAI0_RXD 0
> > +#define SC_P_SAI0_RXD_ADMA_SAI1_RXFS
> SC_P_SAI0_RXD 1
> > +#define SC_P_SAI0_RXD_ADMA_SPI1_CS0 SC_P_SAI0_RXD
> 2
> > +#define SC_P_SAI0_RXD_ADMA_LCDIF_D20
> SC_P_SAI0_RXD 3
> > +#define SC_P_SAI0_RXD_LSIO_GPIO0_IO27 SC_P_SAI0_RXD
> 4
> > +#define SC_P_SAI0_TXFS_ADMA_SAI0_TXFS
> SC_P_SAI0_TXFS 0
> > +#define SC_P_SAI0_TXFS_ADMA_SPI2_CS1
> SC_P_SAI0_TXFS 1
> > +#define SC_P_SAI0_TXFS_ADMA_SPI1_SCK
> SC_P_SAI0_TXFS 2
> > +#define SC_P_SAI0_TXFS_LSIO_GPIO0_IO28
> SC_P_SAI0_TXFS 4
> > +#define SC_P_SAI1_RXD_ADMA_SAI1_RXD
> SC_P_SAI1_RXD 0
> > +#define SC_P_SAI1_RXD_ADMA_SAI0_RXFS
> SC_P_SAI1_RXD 1
> > +#define SC_P_SAI1_RXD_ADMA_SPI1_CS1 SC_P_SAI1_RXD
> 2
> > +#define SC_P_SAI1_RXD_ADMA_LCDIF_D21
> SC_P_SAI1_RXD 3
> > +#define SC_P_SAI1_RXD_LSIO_GPIO0_IO29 SC_P_SAI1_RXD
> 4
> > +#define SC_P_SAI1_RXC_ADMA_SAI1_RXC SC_P_SAI1_RXC
> 0
> > +#define SC_P_SAI1_RXC_ADMA_SAI1_TXC SC_P_SAI1_RXC
> 1
> > +#define SC_P_SAI1_RXC_ADMA_LCDIF_D22
> SC_P_SAI1_RXC 3
> > +#define SC_P_SAI1_RXC_LSIO_GPIO0_IO30 SC_P_SAI1_RXC
> 4
> > +#define SC_P_SAI1_RXFS_ADMA_SAI1_RXFS
> SC_P_SAI1_RXFS 0
> > +#define SC_P_SAI1_RXFS_ADMA_SAI1_TXFS
> SC_P_SAI1_RXFS 1
> > +#define SC_P_SAI1_RXFS_ADMA_LCDIF_D23
> SC_P_SAI1_RXFS 3
> > +#define SC_P_SAI1_RXFS_LSIO_GPIO0_IO31
> SC_P_SAI1_RXFS 4
> > +#define SC_P_SPI2_CS0_ADMA_SPI2_CS0 SC_P_SPI2_CS0
> 0
> > +#define SC_P_SPI2_CS0_LSIO_GPIO1_IO00 SC_P_SPI2_CS0
> 4
> > +#define SC_P_SPI2_SDO_ADMA_SPI2_SDO
> SC_P_SPI2_SDO 0
> > +#define SC_P_SPI2_SDO_LSIO_GPIO1_IO01 SC_P_SPI2_SDO
> 4
> > +#define SC_P_SPI2_SDI_ADMA_SPI2_SDI SC_P_SPI2_SDI
> 0
> > +#define SC_P_SPI2_SDI_LSIO_GPIO1_IO02 SC_P_SPI2_SDI
> 4
> > +#define SC_P_SPI2_SCK_ADMA_SPI2_SCK SC_P_SPI2_SCK
> 0
> > +#define SC_P_SPI2_SCK_LSIO_GPIO1_IO03 SC_P_SPI2_SCK
> 4
> > +#define SC_P_SPI0_SCK_ADMA_SPI0_SCK SC_P_SPI0_SCK
> 0
> > +#define SC_P_SPI0_SCK_ADMA_SAI0_TXC SC_P_SPI0_SCK
> 1
> > +#define SC_P_SPI0_SCK_M40_I2C0_SCL SC_P_SPI0_SCK
> 2
> > +#define SC_P_SPI0_SCK_M40_GPIO0_IO00 SC_P_SPI0_SCK
> 3
> > +#define SC_P_SPI0_SCK_LSIO_GPIO1_IO04 SC_P_SPI0_SCK
> 4
> > +#define SC_P_SPI0_SDI_ADMA_SPI0_SDI SC_P_SPI0_SDI
> 0
> > +#define SC_P_SPI0_SDI_ADMA_SAI0_TXD SC_P_SPI0_SDI
> 1
> > +#define SC_P_SPI0_SDI_M40_TPM0_CH0 SC_P_SPI0_SDI
> 2
> > +#define SC_P_SPI0_SDI_M40_GPIO0_IO02 SC_P_SPI0_SDI
> 3
> > +#define SC_P_SPI0_SDI_LSIO_GPIO1_IO05 SC_P_SPI0_SDI
> 4
> > +#define SC_P_SPI0_SDO_ADMA_SPI0_SDO
> SC_P_SPI0_SDO 0
> > +#define SC_P_SPI0_SDO_ADMA_SAI0_TXFS
> SC_P_SPI0_SDO 1
> > +#define SC_P_SPI0_SDO_M40_I2C0_SDA SC_P_SPI0_SDO
> 2
> > +#define SC_P_SPI0_SDO_M40_GPIO0_IO01 SC_P_SPI0_SDO
> 3
> > +#define SC_P_SPI0_SDO_LSIO_GPIO1_IO06 SC_P_SPI0_SDO
> 4
> > +#define SC_P_SPI0_CS1_ADMA_SPI0_CS1 SC_P_SPI0_CS1
> 0
> > +#define SC_P_SPI0_CS1_ADMA_SAI0_RXC SC_P_SPI0_CS1
> 1
> > +#define SC_P_SPI0_CS1_ADMA_SAI1_TXD SC_P_SPI0_CS1
> 2
> > +#define SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT
> SC_P_SPI0_CS1 3
> > +#define SC_P_SPI0_CS1_LSIO_GPIO1_IO07 SC_P_SPI0_CS1
> 4
> > +#define SC_P_SPI0_CS0_ADMA_SPI0_CS0 SC_P_SPI0_CS0
> 0
> > +#define SC_P_SPI0_CS0_ADMA_SAI0_RXD SC_P_SPI0_CS0
> 1
> > +#define SC_P_SPI0_CS0_M40_TPM0_CH1 SC_P_SPI0_CS0
> 2
> > +#define SC_P_SPI0_CS0_M40_GPIO0_IO03 SC_P_SPI0_CS0
> 3
> > +#define SC_P_SPI0_CS0_LSIO_GPIO1_IO08 SC_P_SPI0_CS0
> 4
> > +#define SC_P_ADC_IN1_ADMA_ADC_IN1 SC_P_ADC_IN1
> 0
> > +#define SC_P_ADC_IN1_M40_I2C0_SDA SC_P_ADC_IN1
> 1
> > +#define SC_P_ADC_IN1_M40_GPIO0_IO01 SC_P_ADC_IN1
> 2
> > +#define SC_P_ADC_IN1_LSIO_GPIO1_IO09 SC_P_ADC_IN1
> 4
> > +#define SC_P_ADC_IN0_ADMA_ADC_IN0 SC_P_ADC_IN0
> 0
> > +#define SC_P_ADC_IN0_M40_I2C0_SCL SC_P_ADC_IN0
> 1
> > +#define SC_P_ADC_IN0_M40_GPIO0_IO00 SC_P_ADC_IN0
> 2
> > +#define SC_P_ADC_IN0_LSIO_GPIO1_IO10 SC_P_ADC_IN0
> 4
> > +#define SC_P_ADC_IN3_ADMA_ADC_IN3 SC_P_ADC_IN3
> 0
> > +#define SC_P_ADC_IN3_M40_UART0_TX SC_P_ADC_IN3
> 1
> > +#define SC_P_ADC_IN3_M40_GPIO0_IO03 SC_P_ADC_IN3
> 2
> > +#define SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0
> SC_P_ADC_IN3 3
> > +#define SC_P_ADC_IN3_LSIO_GPIO1_IO11 SC_P_ADC_IN3
> 4
> > +#define SC_P_ADC_IN2_ADMA_ADC_IN2 SC_P_ADC_IN2
> 0
> > +#define SC_P_ADC_IN2_M40_UART0_RX SC_P_ADC_IN2
> 1
> > +#define SC_P_ADC_IN2_M40_GPIO0_IO02 SC_P_ADC_IN2
> 2
> > +#define SC_P_ADC_IN2_ADMA_ACM_MCLK_IN0
> SC_P_ADC_IN2 3
> > +#define SC_P_ADC_IN2_LSIO_GPIO1_IO12 SC_P_ADC_IN2
> 4
> > +#define SC_P_ADC_IN5_ADMA_ADC_IN5 SC_P_ADC_IN5
> 0
> > +#define SC_P_ADC_IN5_M40_TPM0_CH1 SC_P_ADC_IN5
> 1
> > +#define SC_P_ADC_IN5_M40_GPIO0_IO05 SC_P_ADC_IN5
> 2
> > +#define SC_P_ADC_IN5_LSIO_GPIO1_IO13 SC_P_ADC_IN5
> 4
> > +#define SC_P_ADC_IN4_ADMA_ADC_IN4 SC_P_ADC_IN4
> 0
> > +#define SC_P_ADC_IN4_M40_TPM0_CH0 SC_P_ADC_IN4
> 1
> > +#define SC_P_ADC_IN4_M40_GPIO0_IO04 SC_P_ADC_IN4
> 2
> > +#define SC_P_ADC_IN4_LSIO_GPIO1_IO14 SC_P_ADC_IN4
> 4
> > +#define SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX
> SC_P_FLEXCAN0_RX 0
> > +#define SC_P_FLEXCAN0_RX_ADMA_SAI2_RXC
> SC_P_FLEXCAN0_RX 1
> > +#define SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B
> SC_P_FLEXCAN0_RX 2
> > +#define SC_P_FLEXCAN0_RX_ADMA_SAI1_TXC
> SC_P_FLEXCAN0_RX 3
> > +#define SC_P_FLEXCAN0_RX_LSIO_GPIO1_IO15
> SC_P_FLEXCAN0_RX 4
> > +#define SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX
> SC_P_FLEXCAN0_TX 0
> > +#define SC_P_FLEXCAN0_TX_ADMA_SAI2_RXD
> SC_P_FLEXCAN0_TX 1
> > +#define SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B
> SC_P_FLEXCAN0_TX 2
> > +#define SC_P_FLEXCAN0_TX_ADMA_SAI1_TXFS
> SC_P_FLEXCAN0_TX 3
> > +#define SC_P_FLEXCAN0_TX_LSIO_GPIO1_IO16
> SC_P_FLEXCAN0_TX 4
> > +#define SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX
> SC_P_FLEXCAN1_RX 0
> > +#define SC_P_FLEXCAN1_RX_ADMA_SAI2_RXFS
> SC_P_FLEXCAN1_RX 1
> > +#define SC_P_FLEXCAN1_RX_ADMA_FTM_CH2
> SC_P_FLEXCAN1_RX 2
> > +#define SC_P_FLEXCAN1_RX_ADMA_SAI1_TXD
> SC_P_FLEXCAN1_RX 3
> > +#define SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17
> SC_P_FLEXCAN1_RX 4
> > +#define SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX
> SC_P_FLEXCAN1_TX 0
> > +#define SC_P_FLEXCAN1_TX_ADMA_SAI3_RXC
> SC_P_FLEXCAN1_TX 1
> > +#define SC_P_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0
> SC_P_FLEXCAN1_TX 2
> > +#define SC_P_FLEXCAN1_TX_ADMA_SAI1_RXD
> SC_P_FLEXCAN1_TX 3
> > +#define SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18
> SC_P_FLEXCAN1_TX 4
> > +#define SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX
> SC_P_FLEXCAN2_RX 0
> > +#define SC_P_FLEXCAN2_RX_ADMA_SAI3_RXD
> SC_P_FLEXCAN2_RX 1
> > +#define SC_P_FLEXCAN2_RX_ADMA_UART3_RX
> SC_P_FLEXCAN2_RX 2
> > +#define SC_P_FLEXCAN2_RX_ADMA_SAI1_RXFS
> SC_P_FLEXCAN2_RX 3
> > +#define SC_P_FLEXCAN2_RX_LSIO_GPIO1_IO19
> SC_P_FLEXCAN2_RX 4
> > +#define SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX
> SC_P_FLEXCAN2_TX 0
> > +#define SC_P_FLEXCAN2_TX_ADMA_SAI3_RXFS
> SC_P_FLEXCAN2_TX 1
> > +#define SC_P_FLEXCAN2_TX_ADMA_UART3_TX
> SC_P_FLEXCAN2_TX 2
> > +#define SC_P_FLEXCAN2_TX_ADMA_SAI1_RXC
> SC_P_FLEXCAN2_TX 3
> > +#define SC_P_FLEXCAN2_TX_LSIO_GPIO1_IO20
> SC_P_FLEXCAN2_TX 4
> > +#define SC_P_UART0_RX_ADMA_UART0_RX
> SC_P_UART0_RX 0
> > +#define SC_P_UART0_RX_ADMA_MQS_R
> SC_P_UART0_RX 1
> > +#define SC_P_UART0_RX_ADMA_FLEXCAN0_RX
> SC_P_UART0_RX 2
> > +#define SC_P_UART0_RX_LSIO_GPIO1_IO21
> SC_P_UART0_RX 4
> > +#define SC_P_UART0_TX_ADMA_UART0_TX
> SC_P_UART0_TX 0
> > +#define SC_P_UART0_TX_ADMA_MQS_L
> SC_P_UART0_TX 1
> > +#define SC_P_UART0_TX_ADMA_FLEXCAN0_TX
> SC_P_UART0_TX 2
> > +#define SC_P_UART0_TX_LSIO_GPIO1_IO22
> SC_P_UART0_TX 4
> > +#define SC_P_UART2_TX_ADMA_UART2_TX
> SC_P_UART2_TX 0
> > +#define SC_P_UART2_TX_ADMA_FTM_CH1
> SC_P_UART2_TX 1
> > +#define SC_P_UART2_TX_ADMA_FLEXCAN1_TX
> SC_P_UART2_TX 2
> > +#define SC_P_UART2_TX_LSIO_GPIO1_IO23
> SC_P_UART2_TX 4
> > +#define SC_P_UART2_RX_ADMA_UART2_RX
> SC_P_UART2_RX 0
> > +#define SC_P_UART2_RX_ADMA_FTM_CH0
> SC_P_UART2_RX 1
> > +#define SC_P_UART2_RX_ADMA_FLEXCAN1_RX
> SC_P_UART2_RX 2
> > +#define SC_P_UART2_RX_LSIO_GPIO1_IO24
> SC_P_UART2_RX 4
> > +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL
> SC_P_MIPI_DSI0_I2C0_SCL 0
> > +#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02
> SC_P_MIPI_DSI0_I2C0_SCL 1
> > +#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25
> SC_P_MIPI_DSI0_I2C0_SCL 4
> > +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA
> SC_P_MIPI_DSI0_I2C0_SDA 0
> > +#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03
> SC_P_MIPI_DSI0_I2C0_SDA 1
> > +#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26
> SC_P_MIPI_DSI0_I2C0_SDA 4
> > +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00
> SC_P_MIPI_DSI0_GPIO0_00 0
> > +#define SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL
> SC_P_MIPI_DSI0_GPIO0_00 1
> > +#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT
> SC_P_MIPI_DSI0_GPIO0_00 2
> > +#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27
> SC_P_MIPI_DSI0_GPIO0_00 4
> > +#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01
> SC_P_MIPI_DSI0_GPIO0_01 0
> > +#define SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA
> SC_P_MIPI_DSI0_GPIO0_01 1
> > +#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28
> SC_P_MIPI_DSI0_GPIO0_01 4
> > +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL
> SC_P_MIPI_DSI1_I2C0_SCL 0
> > +#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02
> SC_P_MIPI_DSI1_I2C0_SCL 1
> > +#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29
> SC_P_MIPI_DSI1_I2C0_SCL 4
> > +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA
> SC_P_MIPI_DSI1_I2C0_SDA 0
> > +#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03
> SC_P_MIPI_DSI1_I2C0_SDA 1
> > +#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30
> SC_P_MIPI_DSI1_I2C0_SDA 4
> > +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00
> SC_P_MIPI_DSI1_GPIO0_00 0
> > +#define SC_P_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL
> SC_P_MIPI_DSI1_GPIO0_00 1
> > +#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT
> SC_P_MIPI_DSI1_GPIO0_00 2
> > +#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31
> SC_P_MIPI_DSI1_GPIO0_00 4
> > +#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01
> SC_P_MIPI_DSI1_GPIO0_01 0
> > +#define SC_P_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA
> SC_P_MIPI_DSI1_GPIO0_01 1
> > +#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00
> SC_P_MIPI_DSI1_GPIO0_01 4
> > +#define SC_P_JTAG_TRST_B_SCU_JTAG_TRST_B
> SC_P_JTAG_TRST_B 0
> > +#define SC_P_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT
> SC_P_JTAG_TRST_B 1
> > +#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL
> SC_P_PMIC_I2C_SCL 0
> > +#define SC_P_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON
> SC_P_PMIC_I2C_SCL 1
> > +#define SC_P_PMIC_I2C_SCL_LSIO_GPIO2_IO01
> SC_P_PMIC_I2C_SCL 4
> > +#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA
> SC_P_PMIC_I2C_SDA 0
> > +#define SC_P_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON
> SC_P_PMIC_I2C_SDA 1
> > +#define SC_P_PMIC_I2C_SDA_LSIO_GPIO2_IO02
> SC_P_PMIC_I2C_SDA 4
> > +#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B
> SC_P_PMIC_INT_B 0
> > +#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00
> SC_P_SCU_GPIO0_00 0
> > +#define SC_P_SCU_GPIO0_00_SCU_UART0_RX
> SC_P_SCU_GPIO0_00 1
> > +#define SC_P_SCU_GPIO0_00_M40_UART0_RX
> SC_P_SCU_GPIO0_00 2
> > +#define SC_P_SCU_GPIO0_00_ADMA_UART3_RX
> SC_P_SCU_GPIO0_00 3
> > +#define SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03
> SC_P_SCU_GPIO0_00 4
> > +#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01
> SC_P_SCU_GPIO0_01 0
> > +#define SC_P_SCU_GPIO0_01_SCU_UART0_TX
> SC_P_SCU_GPIO0_01 1
> > +#define SC_P_SCU_GPIO0_01_M40_UART0_TX
> SC_P_SCU_GPIO0_01 2
> > +#define SC_P_SCU_GPIO0_01_ADMA_UART3_TX
> SC_P_SCU_GPIO0_01 3
> > +#define SC_P_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT
> SC_P_SCU_GPIO0_01 4
> > +#define SC_P_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY
> SC_P_SCU_PMIC_STANDBY 0
> > +#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0
> SC_P_SCU_BOOT_MODE0 0
> > +#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1
> SC_P_SCU_BOOT_MODE1 0
> > +#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2
> SC_P_SCU_BOOT_MODE2 0
> > +#define SC_P_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA
> SC_P_SCU_BOOT_MODE2 1
> > +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3
> SC_P_SCU_BOOT_MODE3 0
> > +#define SC_P_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL
> SC_P_SCU_BOOT_MODE3 1
> > +#define SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K
> SC_P_SCU_BOOT_MODE3 3
> > +#define SC_P_CSI_D00_CI_PI_D02 SC_P_CSI_D00
> 0
> > +#define SC_P_CSI_D00_ADMA_SAI0_RXC SC_P_CSI_D00
> 2
> > +#define SC_P_CSI_D01_CI_PI_D03 SC_P_CSI_D01
> 0
> > +#define SC_P_CSI_D01_ADMA_SAI0_RXD SC_P_CSI_D01
> 2
> > +#define SC_P_CSI_D02_CI_PI_D04 SC_P_CSI_D02
> 0
> > +#define SC_P_CSI_D02_ADMA_SAI0_RXFS SC_P_CSI_D02
> 2
> > +#define SC_P_CSI_D03_CI_PI_D05 SC_P_CSI_D03
> 0
> > +#define SC_P_CSI_D03_ADMA_SAI2_RXC SC_P_CSI_D03
> 2
> > +#define SC_P_CSI_D04_CI_PI_D06 SC_P_CSI_D04
> 0
> > +#define SC_P_CSI_D04_ADMA_SAI2_RXD SC_P_CSI_D04
> 2
> > +#define SC_P_CSI_D05_CI_PI_D07 SC_P_CSI_D05
> 0
> > +#define SC_P_CSI_D05_ADMA_SAI2_RXFS SC_P_CSI_D05
> 2
> > +#define SC_P_CSI_D06_CI_PI_D08 SC_P_CSI_D06
> 0
> > +#define SC_P_CSI_D06_ADMA_SAI3_RXC SC_P_CSI_D06
> 2
> > +#define SC_P_CSI_D07_CI_PI_D09 SC_P_CSI_D07
> 0
> > +#define SC_P_CSI_D07_ADMA_SAI3_RXD SC_P_CSI_D07
> 2
> > +#define SC_P_CSI_HSYNC_CI_PI_HSYNC SC_P_CSI_HSYNC
> 0
> > +#define SC_P_CSI_HSYNC_CI_PI_D00 SC_P_CSI_HSYNC
> 1
> > +#define SC_P_CSI_HSYNC_ADMA_SAI3_RXFS
> SC_P_CSI_HSYNC 2
> > +#define SC_P_CSI_VSYNC_CI_PI_VSYNC SC_P_CSI_VSYNC
> 0
> > +#define SC_P_CSI_VSYNC_CI_PI_D01 SC_P_CSI_VSYNC
> 1
> > +#define SC_P_CSI_PCLK_CI_PI_PCLK SC_P_CSI_PCLK
> 0
> > +#define SC_P_CSI_PCLK_MIPI_CSI0_I2C0_SCL SC_P_CSI_PCLK
> 1
> > +#define SC_P_CSI_PCLK_ADMA_SPI1_SCK SC_P_CSI_PCLK
> 3
> > +#define SC_P_CSI_PCLK_LSIO_GPIO3_IO00 SC_P_CSI_PCLK
> 4
> > +#define SC_P_CSI_MCLK_CI_PI_MCLK SC_P_CSI_MCLK
> 0
> > +#define SC_P_CSI_MCLK_MIPI_CSI0_I2C0_SDA
> SC_P_CSI_MCLK 1
> > +#define SC_P_CSI_MCLK_ADMA_SPI1_SDO
> SC_P_CSI_MCLK 3
> > +#define SC_P_CSI_MCLK_LSIO_GPIO3_IO01
> SC_P_CSI_MCLK 4
> > +#define SC_P_CSI_EN_CI_PI_EN SC_P_CSI_EN
> 0
> > +#define SC_P_CSI_EN_CI_PI_I2C_SCL SC_P_CSI_EN
> 1
> > +#define SC_P_CSI_EN_ADMA_I2C3_SCL SC_P_CSI_EN
> 2
> > +#define SC_P_CSI_EN_ADMA_SPI1_SDI SC_P_CSI_EN
> 3
> > +#define SC_P_CSI_EN_LSIO_GPIO3_IO02 SC_P_CSI_EN
> 4
> > +#define SC_P_CSI_RESET_CI_PI_RESET SC_P_CSI_RESET
> 0
> > +#define SC_P_CSI_RESET_CI_PI_I2C_SDA SC_P_CSI_RESET
> 1
> > +#define SC_P_CSI_RESET_ADMA_I2C3_SDA
> SC_P_CSI_RESET 2
> > +#define SC_P_CSI_RESET_ADMA_SPI1_CS0 SC_P_CSI_RESET
> 3
> > +#define SC_P_CSI_RESET_LSIO_GPIO3_IO03 SC_P_CSI_RESET
> 4
> > +#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT
> SC_P_MIPI_CSI0_MCLK_OUT 0
> > +#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04
> SC_P_MIPI_CSI0_MCLK_OUT 4
> > +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL
> SC_P_MIPI_CSI0_I2C0_SCL 0
> > +#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02
> SC_P_MIPI_CSI0_I2C0_SCL 1
> > +#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05
> SC_P_MIPI_CSI0_I2C0_SCL 4
> > +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA
> SC_P_MIPI_CSI0_I2C0_SDA 0
> > +#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03
> SC_P_MIPI_CSI0_I2C0_SDA 1
> > +#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06
> SC_P_MIPI_CSI0_I2C0_SDA 4
> > +#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01
> SC_P_MIPI_CSI0_GPIO0_01 0
> > +#define SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA
> SC_P_MIPI_CSI0_GPIO0_01 1
> > +#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07
> SC_P_MIPI_CSI0_GPIO0_01 4
> > +#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00
> SC_P_MIPI_CSI0_GPIO0_00 0
> > +#define SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL
> SC_P_MIPI_CSI0_GPIO0_00 1
> > +#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08
> SC_P_MIPI_CSI0_GPIO0_00 4
> > +#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0
> SC_P_QSPI0A_DATA0 0
> > +#define SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09
> SC_P_QSPI0A_DATA0 4
> > +#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1
> SC_P_QSPI0A_DATA1 0
> > +#define SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10
> SC_P_QSPI0A_DATA1 4
> > +#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2
> SC_P_QSPI0A_DATA2 0
> > +#define SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11
> SC_P_QSPI0A_DATA2 4
> > +#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3
> SC_P_QSPI0A_DATA3 0
> > +#define SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12
> SC_P_QSPI0A_DATA3 4
> > +#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS
> SC_P_QSPI0A_DQS 0
> > +#define SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13
> SC_P_QSPI0A_DQS 4
> > +#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B
> SC_P_QSPI0A_SS0_B 0
> > +#define SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14
> SC_P_QSPI0A_SS0_B 4
> > +#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B
> SC_P_QSPI0A_SS1_B 0
> > +#define SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15
> SC_P_QSPI0A_SS1_B 4
> > +#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK
> SC_P_QSPI0A_SCLK 0
> > +#define SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16
> SC_P_QSPI0A_SCLK 4
> > +#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK
> SC_P_QSPI0B_SCLK 0
> > +#define SC_P_QSPI0B_SCLK_LSIO_QSPI1A_SCLK
> SC_P_QSPI0B_SCLK 1
> > +#define SC_P_QSPI0B_SCLK_LSIO_KPP0_COL0
> SC_P_QSPI0B_SCLK 2
> > +#define SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17
> SC_P_QSPI0B_SCLK 4
> > +#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0
> SC_P_QSPI0B_DATA0 0
> > +#define SC_P_QSPI0B_DATA0_LSIO_QSPI1A_DATA0
> SC_P_QSPI0B_DATA0 1
> > +#define SC_P_QSPI0B_DATA0_LSIO_KPP0_COL1
> SC_P_QSPI0B_DATA0 2
> > +#define SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18
> SC_P_QSPI0B_DATA0 4
> > +#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1
> SC_P_QSPI0B_DATA1 0
> > +#define SC_P_QSPI0B_DATA1_LSIO_QSPI1A_DATA1
> SC_P_QSPI0B_DATA1 1
> > +#define SC_P_QSPI0B_DATA1_LSIO_KPP0_COL2
> SC_P_QSPI0B_DATA1 2
> > +#define SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19
> SC_P_QSPI0B_DATA1 4
> > +#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2
> SC_P_QSPI0B_DATA2 0
> > +#define SC_P_QSPI0B_DATA2_LSIO_QSPI1A_DATA2
> SC_P_QSPI0B_DATA2 1
> > +#define SC_P_QSPI0B_DATA2_LSIO_KPP0_COL3
> SC_P_QSPI0B_DATA2 2
> > +#define SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20
> SC_P_QSPI0B_DATA2 4
> > +#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3
> SC_P_QSPI0B_DATA3 0
> > +#define SC_P_QSPI0B_DATA3_LSIO_QSPI1A_DATA3
> SC_P_QSPI0B_DATA3 1
> > +#define SC_P_QSPI0B_DATA3_LSIO_KPP0_ROW0
> SC_P_QSPI0B_DATA3 2
> > +#define SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21
> SC_P_QSPI0B_DATA3 4
> > +#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS
> SC_P_QSPI0B_DQS 0
> > +#define SC_P_QSPI0B_DQS_LSIO_QSPI1A_DQS
> SC_P_QSPI0B_DQS 1
> > +#define SC_P_QSPI0B_DQS_LSIO_KPP0_ROW1
> SC_P_QSPI0B_DQS 2
> > +#define SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22
> SC_P_QSPI0B_DQS 4
> > +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B
> SC_P_QSPI0B_SS0_B 0
> > +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B
> SC_P_QSPI0B_SS0_B 1
> > +#define SC_P_QSPI0B_SS0_B_LSIO_KPP0_ROW2
> SC_P_QSPI0B_SS0_B 2
> > +#define SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23
> SC_P_QSPI0B_SS0_B 4
> > +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B
> SC_P_QSPI0B_SS1_B 0
> > +#define SC_P_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B
> SC_P_QSPI0B_SS1_B 1
> > +#define SC_P_QSPI0B_SS1_B_LSIO_KPP0_ROW3
> SC_P_QSPI0B_SS1_B 2
> > +#define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24
> SC_P_QSPI0B_SS1_B 4
> > +
> > +#endif /* _SC_PADS_H */
> > --
> > 2.7.4
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply [flat|nested] 36+ messages in thread
* RE: [PATCH 4/6] pinctrl: fsl: add scu based pinctrl support
2018-05-02 12:29 ` Linus Walleij
@ 2018-05-02 18:42 ` A.s. Dong
-1 siblings, 0 replies; 36+ messages in thread
From: A.s. Dong @ 2018-05-02 18:42 UTC (permalink / raw)
To: Linus Walleij
Cc: Dong Aisheng, Fabio Estevam, Stefan Agner,
open list:GPIO SUBSYSTEM, dl-linux-imx, Sascha Hauer,
Fabio Estevam, Shawn Guo, Linux ARM
Hi Linus,
> -----Original Message-----
> From: Linus Walleij [mailto:linus.walleij@linaro.org]
> Sent: Wednesday, May 2, 2018 8:29 PM
> To: A.s. Dong <aisheng.dong@nxp.com>
> Cc: open list:GPIO SUBSYSTEM <linux-gpio@vger.kernel.org>; Linux ARM
> <linux-arm-kernel@lists.infradead.org>; Shawn Guo
> <shawnguo@kernel.org>; Stefan Agner <stefan@agner.ch>; Dong Aisheng
> <dongas86@gmail.com>; dl-linux-imx <linux-imx@nxp.com>; Sascha Hauer
> <kernel@pengutronix.de>; Fabio Estevam <fabio.estevam@nxp.com>;
> Fabio Estevam <festevam@gmail.com>
> Subject: Re: [PATCH 4/6] pinctrl: fsl: add scu based pinctrl support
>
> On Wed, May 2, 2018 at 2:27 PM, Linus Walleij <linus.walleij@linaro.org>
> wrote:
> > On Fri, Apr 27, 2018 at 9:01 PM, Dong Aisheng <aisheng.dong@nxp.com>
> wrote:
> >
> >> Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller
> >> that is responsible for controlling the pad setting of the IPs that
> >> are present. Communication between the host processor running an OS
> >> and the system controller happens through a SCU protocol.
> >> This patch adds SCU protocol based pinctrl drivers.
> >>
> >> Cc: Linus Walleij <linus.walleij@linaro.org>
> >> Cc: Shawn Guo <shawnguo@kernel.org>
> >> Cc: Fabio Estevam <festevam@gmail.com>
> >> Cc: Stefan Agner <stefan@agner.ch>
> >> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> >> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> >
> > Patch applied.
>
> Bah on second thought holding this back since I see thyere are some
> discussions about the bindings in the next patch.
>
Yes :-)
> Anyway, it's nice if the other maintainers would like to get involved.
>
> Dong: you only need to resend patches 4.5.6 next time.
Got it.
Thanks a lot.
Regards
Dong Aisheng
>
> Yours,
> Linus Walleij
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH 4/6] pinctrl: fsl: add scu based pinctrl support
@ 2018-05-02 18:42 ` A.s. Dong
0 siblings, 0 replies; 36+ messages in thread
From: A.s. Dong @ 2018-05-02 18:42 UTC (permalink / raw)
To: linux-arm-kernel
Hi Linus,
> -----Original Message-----
> From: Linus Walleij [mailto:linus.walleij at linaro.org]
> Sent: Wednesday, May 2, 2018 8:29 PM
> To: A.s. Dong <aisheng.dong@nxp.com>
> Cc: open list:GPIO SUBSYSTEM <linux-gpio@vger.kernel.org>; Linux ARM
> <linux-arm-kernel@lists.infradead.org>; Shawn Guo
> <shawnguo@kernel.org>; Stefan Agner <stefan@agner.ch>; Dong Aisheng
> <dongas86@gmail.com>; dl-linux-imx <linux-imx@nxp.com>; Sascha Hauer
> <kernel@pengutronix.de>; Fabio Estevam <fabio.estevam@nxp.com>;
> Fabio Estevam <festevam@gmail.com>
> Subject: Re: [PATCH 4/6] pinctrl: fsl: add scu based pinctrl support
>
> On Wed, May 2, 2018 at 2:27 PM, Linus Walleij <linus.walleij@linaro.org>
> wrote:
> > On Fri, Apr 27, 2018 at 9:01 PM, Dong Aisheng <aisheng.dong@nxp.com>
> wrote:
> >
> >> Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller
> >> that is responsible for controlling the pad setting of the IPs that
> >> are present. Communication between the host processor running an OS
> >> and the system controller happens through a SCU protocol.
> >> This patch adds SCU protocol based pinctrl drivers.
> >>
> >> Cc: Linus Walleij <linus.walleij@linaro.org>
> >> Cc: Shawn Guo <shawnguo@kernel.org>
> >> Cc: Fabio Estevam <festevam@gmail.com>
> >> Cc: Stefan Agner <stefan@agner.ch>
> >> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> >> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> >
> > Patch applied.
>
> Bah on second thought holding this back since I see thyere are some
> discussions about the bindings in the next patch.
>
Yes :-)
> Anyway, it's nice if the other maintainers would like to get involved.
>
> Dong: you only need to resend patches 4.5.6 next time.
Got it.
Thanks a lot.
Regards
Dong Aisheng
>
> Yours,
> Linus Walleij
^ permalink raw reply [flat|nested] 36+ messages in thread
end of thread, other threads:[~2018-05-02 18:42 UTC | newest]
Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-04-27 19:01 [PATCH 0/6] pinctrl: imx: add imx8qxp pinctrl support Dong Aisheng
2018-04-27 19:01 ` Dong Aisheng
2018-04-27 19:01 ` [PATCH 1/6] pinctrl: imx: fix unsigned check if nfuncs with less than or equal zero Dong Aisheng
2018-04-27 19:01 ` Dong Aisheng
2018-05-02 12:22 ` Linus Walleij
2018-05-02 12:22 ` Linus Walleij
2018-04-27 19:01 ` [PATCH 2/6] pinctrl: pinctrl-imx: improve the code comments of PIN_FUNC_ID Dong Aisheng
2018-04-27 19:01 ` Dong Aisheng
2018-05-02 12:23 ` Linus Walleij
2018-05-02 12:23 ` Linus Walleij
2018-04-27 19:01 ` [PATCH 3/6] pinctrl: imx: use seq_puts() instead of seq_printf() Dong Aisheng
2018-04-27 19:01 ` Dong Aisheng
2018-05-02 12:24 ` Linus Walleij
2018-05-02 12:24 ` Linus Walleij
2018-04-27 19:01 ` [PATCH 4/6] pinctrl: fsl: add scu based pinctrl support Dong Aisheng
2018-04-27 19:01 ` Dong Aisheng
2018-05-02 12:27 ` Linus Walleij
2018-05-02 12:27 ` Linus Walleij
2018-05-02 12:29 ` Linus Walleij
2018-05-02 12:29 ` Linus Walleij
2018-05-02 12:36 ` Sascha Hauer
2018-05-02 12:36 ` Sascha Hauer
2018-05-02 13:03 ` Linus Walleij
2018-05-02 13:03 ` Linus Walleij
2018-05-02 15:05 ` Sascha Hauer
2018-05-02 15:05 ` Sascha Hauer
2018-05-02 18:42 ` A.s. Dong
2018-05-02 18:42 ` A.s. Dong
2018-04-27 19:01 ` [PATCH 5/6] dt-bindings: pinctrl: add imx8qxp pinctrl binding doc Dong Aisheng
2018-04-27 19:01 ` Dong Aisheng
2018-05-01 15:58 ` Rob Herring
2018-05-01 15:58 ` Rob Herring
2018-05-02 18:07 ` A.s. Dong
2018-05-02 18:07 ` A.s. Dong
2018-04-27 19:01 ` [PATCH 6/6] pinctrl: imx: add imx8qxp driver Dong Aisheng
2018-04-27 19:01 ` Dong Aisheng
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