From mboxrd@z Thu Jan 1 00:00:00 1970 From: Manu Gautam Subject: [PATCH v5 1/7] clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clk Date: Thu, 3 May 2018 02:36:08 +0530 Message-ID: <1525295174-15995-2-git-send-email-mgautam@codeaurora.org> References: <1525295174-15995-1-git-send-email-mgautam@codeaurora.org> Return-path: In-Reply-To: <1525295174-15995-1-git-send-email-mgautam@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org To: Kishon Vijay Abraham I , robh@kernel.org, sboyd@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dianders@chromium.org, evgreen@chromium.org, Vivek Gautam , linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, Manu Gautam List-Id: linux-arm-msm@vger.kernel.org The USB and PCIE pipe clocks are sourced from external clocks inside the QMP USB/PCIE PHYs. Enabling or disabling of PIPE RCG clocks is dependent on PHY initialization sequence hence update halt_check to BRANCH_HALT_SKIP for these clocks so that clock status bit is not polled when enabling or disabling the clocks. It allows to simplify PHY client driver code which is both user and source of the pipe_clk and avoid error logging related status check on clk_disable/enable. Signed-off-by: Manu Gautam --- drivers/clk/qcom/gcc-msm8996.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c index 3d64529..b73e7f1 100644 --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -1418,6 +1418,7 @@ enum { static struct clk_branch gcc_usb3_phy_pipe_clk = { .halt_reg = 0x50004, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x50004, .enable_mask = BIT(0), @@ -2472,6 +2473,7 @@ enum { static struct clk_branch gcc_pcie_0_pipe_clk = { .halt_reg = 0x6b018, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x6b018, .enable_mask = BIT(0), @@ -2547,6 +2549,7 @@ enum { static struct clk_branch gcc_pcie_1_pipe_clk = { .halt_reg = 0x6d018, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x6d018, .enable_mask = BIT(0), @@ -2622,6 +2625,7 @@ enum { static struct clk_branch gcc_pcie_2_pipe_clk = { .halt_reg = 0x6e018, + .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x6e018, .enable_mask = BIT(0), -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v5,1/7] clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clk From: Manu Gautam Message-Id: <1525295174-15995-2-git-send-email-mgautam@codeaurora.org> Date: Thu, 3 May 2018 02:36:08 +0530 To: Kishon Vijay Abraham I , robh@kernel.org, sboyd@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dianders@chromium.org, evgreen@chromium.org, Vivek Gautam , linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, Manu Gautam List-ID: VGhlIFVTQiBhbmQgUENJRSBwaXBlIGNsb2NrcyBhcmUgc291cmNlZCBmcm9tIGV4dGVybmFsIGNs b2NrcwppbnNpZGUgdGhlIFFNUCBVU0IvUENJRSBQSFlzLiBFbmFibGluZyBvciBkaXNhYmxpbmcg b2YgUElQRSBSQ0cKY2xvY2tzIGlzIGRlcGVuZGVudCBvbiBQSFkgaW5pdGlhbGl6YXRpb24gc2Vx dWVuY2UgaGVuY2UKdXBkYXRlIGhhbHRfY2hlY2sgdG8gQlJBTkNIX0hBTFRfU0tJUCBmb3IgdGhl c2UgY2xvY2tzIHNvCnRoYXQgY2xvY2sgc3RhdHVzIGJpdCBpcyBub3QgcG9sbGVkIHdoZW4gZW5h Ymxpbmcgb3IgZGlzYWJsaW5nCnRoZSBjbG9ja3MuIEl0IGFsbG93cyB0byBzaW1wbGlmeSBQSFkg Y2xpZW50IGRyaXZlciBjb2RlIHdoaWNoCmlzIGJvdGggdXNlciBhbmQgc291cmNlIG9mIHRoZSBw aXBlX2NsayBhbmQgYXZvaWQgZXJyb3IgbG9nZ2luZwpyZWxhdGVkIHN0YXR1cyBjaGVjayBvbiBj bGtfZGlzYWJsZS9lbmFibGUuCgpTaWduZWQtb2ZmLWJ5OiBNYW51IEdhdXRhbSA8bWdhdXRhbUBj b2RlYXVyb3JhLm9yZz4KLS0tCiBkcml2ZXJzL2Nsay9xY29tL2djYy1tc204OTk2LmMgfCA0ICsr KysKIDEgZmlsZSBjaGFuZ2VkLCA0IGluc2VydGlvbnMoKykKCmRpZmYgLS1naXQgYS9kcml2ZXJz L2Nsay9xY29tL2djYy1tc204OTk2LmMgYi9kcml2ZXJzL2Nsay9xY29tL2djYy1tc204OTk2LmMK aW5kZXggM2Q2NDUyOS4uYjczZTdmMSAxMDA2NDQKLS0tIGEvZHJpdmVycy9jbGsvcWNvbS9nY2Mt bXNtODk5Ni5jCisrKyBiL2RyaXZlcnMvY2xrL3Fjb20vZ2NjLW1zbTg5OTYuYwpAQCAtMTQxOCw2 ICsxNDE4LDcgQEAgZW51bSB7CiAKIHN0YXRpYyBzdHJ1Y3QgY2xrX2JyYW5jaCBnY2NfdXNiM19w aHlfcGlwZV9jbGsgPSB7CiAJLmhhbHRfcmVnID0gMHg1MDAwNCwKKwkuaGFsdF9jaGVjayA9IEJS QU5DSF9IQUxUX1NLSVAsCiAJLmNsa3IgPSB7CiAJCS5lbmFibGVfcmVnID0gMHg1MDAwNCwKIAkJ LmVuYWJsZV9tYXNrID0gQklUKDApLApAQCAtMjQ3Miw2ICsyNDczLDcgQEAgZW51bSB7CiAKIHN0 YXRpYyBzdHJ1Y3QgY2xrX2JyYW5jaCBnY2NfcGNpZV8wX3BpcGVfY2xrID0gewogCS5oYWx0X3Jl ZyA9IDB4NmIwMTgsCisJLmhhbHRfY2hlY2sgPSBCUkFOQ0hfSEFMVF9TS0lQLAogCS5jbGtyID0g ewogCQkuZW5hYmxlX3JlZyA9IDB4NmIwMTgsCiAJCS5lbmFibGVfbWFzayA9IEJJVCgwKSwKQEAg LTI1NDcsNiArMjU0OSw3IEBAIGVudW0gewogCiBzdGF0aWMgc3RydWN0IGNsa19icmFuY2ggZ2Nj X3BjaWVfMV9waXBlX2NsayA9IHsKIAkuaGFsdF9yZWcgPSAweDZkMDE4LAorCS5oYWx0X2NoZWNr ID0gQlJBTkNIX0hBTFRfU0tJUCwKIAkuY2xrciA9IHsKIAkJLmVuYWJsZV9yZWcgPSAweDZkMDE4 LAogCQkuZW5hYmxlX21hc2sgPSBCSVQoMCksCkBAIC0yNjIyLDYgKzI2MjUsNyBAQCBlbnVtIHsK IAogc3RhdGljIHN0cnVjdCBjbGtfYnJhbmNoIGdjY19wY2llXzJfcGlwZV9jbGsgPSB7CiAJLmhh bHRfcmVnID0gMHg2ZTAxOCwKKwkuaGFsdF9jaGVjayA9IEJSQU5DSF9IQUxUX1NLSVAsCiAJLmNs a3IgPSB7CiAJCS5lbmFibGVfcmVnID0gMHg2ZTAxOCwKIAkJLmVuYWJsZV9tYXNrID0gQklUKDAp LAo=