From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: patches@groups.riscv.org,
KONRAD Frederic <frederic.konrad@adacore.com>,
Michael Clark <mjc@sifive.com>
Subject: [Qemu-devel] [PULL 2/3] riscv: htif: increase the priority of the htif subregion
Date: Wed, 9 May 2018 22:20:39 +1200 [thread overview]
Message-ID: <1525861240-4130-3-git-send-email-mjc@sifive.com> (raw)
In-Reply-To: <1525861240-4130-1-git-send-email-mjc@sifive.com>
From: KONRAD Frederic <frederic.konrad@adacore.com>
The htif device is supposed to be mapped over an other subregion. So increase
its priority to one to avoid any conflict.
Here is the output of info mtree:
Before:
(qemu) info mtree
address-space: memory
0000000000000000-ffffffffffffffff (prio 0, i/o): system
0000000000000000-000000000000000f (prio 0, i/o): riscv.htif.uart
0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom
0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint
0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram
address-space: I/O
0000000000000000-000000000000ffff (prio 0, i/o): io
address-space: cpu-memory-0
0000000000000000-ffffffffffffffff (prio 0, i/o): system
0000000000000000-000000000000000f (prio 0, i/o): riscv.htif.uart
0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom
0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint
0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram
After:
(qemu) info mtree
address-space: memory
0000000000000000-ffffffffffffffff (prio 0, i/o): system
0000000000000000-000000000000000f (prio 1, i/o): riscv.htif.uart
0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom
0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint
0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram
address-space: I/O
0000000000000000-000000000000ffff (prio 0, i/o): io
address-space: cpu-memory-0
0000000000000000-ffffffffffffffff (prio 0, i/o): system
0000000000000000-000000000000000f (prio 1, i/o): riscv.htif.uart
0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom
0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint
0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram
Reviewed-by: Michael Clark <mjc@sifive.com>
Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Message-Id: <1525360636-18229-3-git-send-email-frederic.konrad@adacore.com>
---
hw/riscv/riscv_htif.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/riscv_htif.c b/hw/riscv/riscv_htif.c
index be252ec8cce9..f73512941fb6 100644
--- a/hw/riscv/riscv_htif.c
+++ b/hw/riscv/riscv_htif.c
@@ -253,8 +253,9 @@ HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
htif_be_change, s, NULL, true);
if (address_symbol_set == 3) {
memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s,
- TYPE_HTIF_UART, size);
- memory_region_add_subregion(address_space, base, &s->mmio);
+ TYPE_HTIF_UART, size);
+ memory_region_add_subregion_overlap(address_space, base,
+ &s->mmio, 1);
}
return s;
--
2.7.0
next prev parent reply other threads:[~2018-05-09 10:22 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-09 10:20 [Qemu-devel] [PULL 0/3] RISC-V: QEMU 2.13 Minor Fixes Michael Clark
2018-05-09 10:20 ` [Qemu-devel] [PULL 1/3] riscv: spike: allow base == 0 Michael Clark
2018-05-09 10:20 ` Michael Clark [this message]
2018-05-09 10:20 ` [Qemu-devel] [PULL 3/3] riscv: requires libfdt Michael Clark
2018-05-11 10:09 ` [Qemu-devel] [PULL 0/3] RISC-V: QEMU 2.13 Minor Fixes Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2018-05-08 20:07 Michael Clark
2018-05-08 20:07 ` [Qemu-devel] [PULL 2/3] riscv: htif: increase the priority of the htif subregion Michael Clark
2018-05-07 23:14 [Qemu-devel] [PULL 0/3] RISC-V: QEMU 2.13 Minor Fixes Michael Clark
2018-05-07 23:14 ` [Qemu-devel] [PULL 2/3] riscv: htif: increase the priority of the htif subregion Michael Clark
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