* [PATCH] arm64: dts: r8a77995: Add all HSCIF nodes
@ 2018-05-16 13:04 Ulrich Hecht
2018-05-16 13:04 ` [PATCH] arm64: dts: r8a77995: Add SCIF-{0,1,3,4,5} device nodes Ulrich Hecht
2018-05-17 7:26 ` [PATCH] arm64: dts: r8a77995: Add all HSCIF nodes Simon Horman
0 siblings, 2 replies; 4+ messages in thread
From: Ulrich Hecht @ 2018-05-16 13:04 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: wsa, geert, linux-serial, Takeshi Kihara, Ulrich Hecht
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
This patch adds the device nodes all HSCIF serial ports
incl. clocks and power domain to the R8A77995 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
---
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 35 +++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 2f712ac..4b05dc2 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -240,6 +240,41 @@
resets = <&cpg 407>;
};
+ hscif0: serial@e6540000 {
+ compatible = "renesas,hscif-r8a77995",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe6540000 0 0x60>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 520>,
+ <&cpg CPG_CORE R8A77995_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x31>, <&dmac1 0x30>,
+ <&dmac2 0x31>, <&dmac2 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 520>;
+ status = "disabled";
+ };
+
+ hscif3: serial@e66a0000 {
+ compatible = "renesas,hscif-r8a77995",
+ "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0 0xe66a0000 0 0x60>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 517>,
+ <&cpg CPG_CORE R8A77995_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x37>, <&dmac0 0x36>;
+ dma-names = "tx", "rx";
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 517>;
+ status = "disabled";
+ };
+
i2c0: i2c@e6500000 {
#address-cells = <1>;
#size-cells = <0>;
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH] arm64: dts: r8a77995: Add SCIF-{0,1,3,4,5} device nodes
2018-05-16 13:04 [PATCH] arm64: dts: r8a77995: Add all HSCIF nodes Ulrich Hecht
@ 2018-05-16 13:04 ` Ulrich Hecht
2018-05-17 7:38 ` Simon Horman
2018-05-17 7:26 ` [PATCH] arm64: dts: r8a77995: Add all HSCIF nodes Simon Horman
1 sibling, 1 reply; 4+ messages in thread
From: Ulrich Hecht @ 2018-05-16 13:04 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: wsa, geert, linux-serial, Takeshi Kihara, Ulrich Hecht
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
This patch adds the device nodes for SCIF-{0,1,3,4,5} serial ports,
incl. clocks and power domain.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
---
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 70 +++++++++++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 4b05dc2..73d6589 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -628,6 +628,34 @@
status = "disabled";
};
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a77995",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 64>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>,
+ <&cpg CPG_CORE R8A77995_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 207>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a77995",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 64>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>,
+ <&cpg CPG_CORE R8A77995_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 206>;
+ status = "disabled";
+ };
+
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a77995",
"renesas,rcar-gen3-scif", "renesas,scif";
@@ -645,6 +673,48 @@
status = "disabled";
};
+ scif3: serial@e6c50000 {
+ compatible = "renesas,scif-r8a77995",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c50000 0 64>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>,
+ <&cpg CPG_CORE R8A77995_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 204>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6c40000 {
+ compatible = "renesas,scif-r8a77995",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6c40000 0 64>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>,
+ <&cpg CPG_CORE R8A77995_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 203>;
+ status = "disabled";
+ };
+
+ scif5: serial@e6f30000 {
+ compatible = "renesas,scif-r8a77995",
+ "renesas,rcar-gen3-scif", "renesas,scif";
+ reg = <0 0xe6f30000 0 64>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>,
+ <&cpg CPG_CORE R8A77995_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 202>;
+ status = "disabled";
+ };
+
vin4: video@e6ef4000 {
compatible = "renesas,vin-r8a77995";
reg = <0 0xe6ef4000 0 0x1000>;
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: dts: r8a77995: Add all HSCIF nodes
2018-05-16 13:04 [PATCH] arm64: dts: r8a77995: Add all HSCIF nodes Ulrich Hecht
2018-05-16 13:04 ` [PATCH] arm64: dts: r8a77995: Add SCIF-{0,1,3,4,5} device nodes Ulrich Hecht
@ 2018-05-17 7:26 ` Simon Horman
1 sibling, 0 replies; 4+ messages in thread
From: Simon Horman @ 2018-05-17 7:26 UTC (permalink / raw)
To: Ulrich Hecht; +Cc: linux-renesas-soc, wsa, geert, linux-serial, Takeshi Kihara
On Wed, May 16, 2018 at 03:04:50PM +0200, Ulrich Hecht wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> This patch adds the device nodes all HSCIF serial ports
> incl. clocks and power domain to the R8A77995 SoC.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> ---
> arch/arm64/boot/dts/renesas/r8a77995.dtsi | 35 +++++++++++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> index 2f712ac..4b05dc2 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> @@ -240,6 +240,41 @@
> resets = <&cpg 407>;
> };
>
> + hscif0: serial@e6540000 {
> + compatible = "renesas,hscif-r8a77995",
> + "renesas,rcar-gen3-hscif",
> + "renesas,hscif";
> + reg = <0 0xe6540000 0 0x60>;
> + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 520>,
> + <&cpg CPG_CORE R8A77995_CLK_S3D1>,
Section 56.1 of the User's Manual v1.00 indicates that
the clock is S3D1C (250MHz) rather than S3D1 (266.66... MHz).
Otherwise the patch looks fine to me.
> + <&scif_clk>;
> + clock-names = "fck", "brg_int", "scif_clk";
> + dmas = <&dmac1 0x31>, <&dmac1 0x30>,
> + <&dmac2 0x31>, <&dmac2 0x30>;
> + dma-names = "tx", "rx", "tx", "rx";
> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 520>;
> + status = "disabled";
> + };
> +
> + hscif3: serial@e66a0000 {
> + compatible = "renesas,hscif-r8a77995",
> + "renesas,rcar-gen3-hscif",
> + "renesas,hscif";
> + reg = <0 0xe66a0000 0 0x60>;
> + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 517>,
> + <&cpg CPG_CORE R8A77995_CLK_S3D1>,
> + <&scif_clk>;
> + clock-names = "fck", "brg_int", "scif_clk";
> + dmas = <&dmac0 0x37>, <&dmac0 0x36>;
> + dma-names = "tx", "rx";
> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 517>;
> + status = "disabled";
> + };
> +
> i2c0: i2c@e6500000 {
> #address-cells = <1>;
> #size-cells = <0>;
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] arm64: dts: r8a77995: Add SCIF-{0,1,3,4,5} device nodes
2018-05-16 13:04 ` [PATCH] arm64: dts: r8a77995: Add SCIF-{0,1,3,4,5} device nodes Ulrich Hecht
@ 2018-05-17 7:38 ` Simon Horman
0 siblings, 0 replies; 4+ messages in thread
From: Simon Horman @ 2018-05-17 7:38 UTC (permalink / raw)
To: Ulrich Hecht; +Cc: linux-renesas-soc, wsa, geert, linux-serial, Takeshi Kihara
On Wed, May 16, 2018 at 03:04:51PM +0200, Ulrich Hecht wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> This patch adds the device nodes for SCIF-{0,1,3,4,5} serial ports,
> incl. clocks and power domain.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> ---
> arch/arm64/boot/dts/renesas/r8a77995.dtsi | 70 +++++++++++++++++++++++++++++++
> 1 file changed, 70 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> index 4b05dc2..73d6589 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
> @@ -628,6 +628,34 @@
> status = "disabled";
> };
>
> + scif0: serial@e6e60000 {
> + compatible = "renesas,scif-r8a77995",
> + "renesas,rcar-gen3-scif", "renesas,scif";
> + reg = <0 0xe6e60000 0 64>;
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 207>,
> + <&cpg CPG_CORE R8A77995_CLK_S3D1>,
> + <&scif_clk>;
Section 55.1 of the User's Manual v1.00 describes SCIF as using
S3D1Cφ (250MHz) rather than S3D1φ (266.66... MHz) on D3.
Also, do you plan to follow-up with a patch to hook-up DMA for SCIF devices?
Otherwise the patch looks fine to me.
> + clock-names = "fck", "brg_int", "scif_clk";
> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 207>;
> + status = "disabled";
> + };
> +
> + scif1: serial@e6e68000 {
> + compatible = "renesas,scif-r8a77995",
> + "renesas,rcar-gen3-scif", "renesas,scif";
> + reg = <0 0xe6e68000 0 64>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 206>,
> + <&cpg CPG_CORE R8A77995_CLK_S3D1>,
> + <&scif_clk>;
> + clock-names = "fck", "brg_int", "scif_clk";
> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 206>;
> + status = "disabled";
> + };
> +
> scif2: serial@e6e88000 {
> compatible = "renesas,scif-r8a77995",
> "renesas,rcar-gen3-scif", "renesas,scif";
> @@ -645,6 +673,48 @@
> status = "disabled";
> };
>
> + scif3: serial@e6c50000 {
> + compatible = "renesas,scif-r8a77995",
> + "renesas,rcar-gen3-scif", "renesas,scif";
> + reg = <0 0xe6c50000 0 64>;
> + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 204>,
> + <&cpg CPG_CORE R8A77995_CLK_S3D1>,
> + <&scif_clk>;
> + clock-names = "fck", "brg_int", "scif_clk";
> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 204>;
> + status = "disabled";
> + };
> +
> + scif4: serial@e6c40000 {
> + compatible = "renesas,scif-r8a77995",
> + "renesas,rcar-gen3-scif", "renesas,scif";
> + reg = <0 0xe6c40000 0 64>;
> + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 203>,
> + <&cpg CPG_CORE R8A77995_CLK_S3D1>,
> + <&scif_clk>;
> + clock-names = "fck", "brg_int", "scif_clk";
> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 203>;
> + status = "disabled";
> + };
> +
> + scif5: serial@e6f30000 {
> + compatible = "renesas,scif-r8a77995",
> + "renesas,rcar-gen3-scif", "renesas,scif";
> + reg = <0 0xe6f30000 0 64>;
> + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 202>,
> + <&cpg CPG_CORE R8A77995_CLK_S3D1>,
> + <&scif_clk>;
> + clock-names = "fck", "brg_int", "scif_clk";
> + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
> + resets = <&cpg 202>;
> + status = "disabled";
> + };
> +
> vin4: video@e6ef4000 {
> compatible = "renesas,vin-r8a77995";
> reg = <0 0xe6ef4000 0 0x1000>;
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-05-17 7:39 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-05-16 13:04 [PATCH] arm64: dts: r8a77995: Add all HSCIF nodes Ulrich Hecht
2018-05-16 13:04 ` [PATCH] arm64: dts: r8a77995: Add SCIF-{0,1,3,4,5} device nodes Ulrich Hecht
2018-05-17 7:38 ` Simon Horman
2018-05-17 7:26 ` [PATCH] arm64: dts: r8a77995: Add all HSCIF nodes Simon Horman
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