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From: Michael Clark <mjc@sifive.com>
To: qemu-devel@nongnu.org
Cc: patches@groups.riscv.org, Kito Cheng <kito.cheng@gmail.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Michael Clark <mjc@sifive.com>
Subject: [Qemu-devel] [PATCH v1 28/30] RISC-V: linux-user support for RVE ABI
Date: Wed, 23 May 2018 12:15:15 +1200	[thread overview]
Message-ID: <1527034517-7851-29-git-send-email-mjc@sifive.com> (raw)
In-Reply-To: <1527034517-7851-1-git-send-email-mjc@sifive.com>

From: Kito Cheng <kito.cheng@gmail.com>

This change checks elf_flags for EF_RISCV_RVE and if
present uses the RVE linux syscall ABI which uses t0
for the syscall number instead of a7.

Warn and exit if a non-RVE ABI binary is run on a
cpu with the RVE extension as it is incompatible.

Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Co-authored-by: Kito Cheng <kito.cheng@gmail.com>
Co-authored-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
---
 linux-user/riscv/cpu_loop.c | 14 +++++++++++++-
 target/riscv/cpu.h          |  4 ++++
 target/riscv/cpu_user.h     |  3 ++-
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
index f137d39d7e82..5f6a941c6c19 100644
--- a/linux-user/riscv/cpu_loop.c
+++ b/linux-user/riscv/cpu_loop.c
@@ -20,6 +20,7 @@
 #include "qemu/osdep.h"
 #include "qemu.h"
 #include "cpu_loop-common.h"
+#include "elf.h"
 
 void cpu_loop(CPURISCVState *env)
 {
@@ -53,7 +54,8 @@ void cpu_loop(CPURISCVState *env)
                 ret = 0;
             } else {
                 ret = do_syscall(env,
-                                 env->gpr[xA7],
+                                 env->gpr[(env->elf_flags & EF_RISCV_RVE)
+                                    ? xT0 : xA7],
                                  env->gpr[xA0],
                                  env->gpr[xA1],
                                  env->gpr[xA2],
@@ -113,6 +115,16 @@ void cpu_loop(CPURISCVState *env)
 
 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
 {
+    CPUState *cpu = ENV_GET_CPU(env);
+    TaskState *ts = cpu->opaque;
+    struct image_info *info = ts->info;
+
     env->pc = regs->sepc;
     env->gpr[xSP] = regs->sp;
+    env->elf_flags = info->elf_flags;
+
+    if ((env->misa & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
+        fprintf(stderr, "Incompatible ELF: RVE cpu requires RVE ABI binary\n");
+        exit(EXIT_FAILURE);
+    }
 }
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 830a9d476dce..0823461ae9f2 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -123,6 +123,10 @@ struct CPURISCVState {
 
     uint32_t features;
 
+#ifdef CONFIG_USER_ONLY
+    uint32_t elf_flags;
+#endif
+
 #ifndef CONFIG_USER_ONLY
     target_ulong priv;
     target_ulong resetvec;
diff --git a/target/riscv/cpu_user.h b/target/riscv/cpu_user.h
index c2199610abff..52d380aa98c2 100644
--- a/target/riscv/cpu_user.h
+++ b/target/riscv/cpu_user.h
@@ -10,4 +10,5 @@
 #define xA4 14
 #define xA5 15
 #define xA6 16
-#define xA7 17  /* syscall number goes here */
+#define xA7 17  /* syscall number for RVI ABI */
+#define xT0 5   /* syscall number for RVE ABI */
-- 
2.7.0

  parent reply	other threads:[~2018-05-23  0:18 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-23  0:14 [Qemu-devel] [PATCH v1 00/30] QEMU 2.13 RISC-V updates Michael Clark
2018-05-23  0:14 ` [Qemu-devel] [PATCH v1 01/30] RISC-V: Update address bits to support sv39 and sv48 Michael Clark
2018-05-25 15:07   ` Richard Henderson
2018-05-23  0:14 ` [Qemu-devel] [PATCH v1 02/30] RISC-V: Improve page table walker spec compliance Michael Clark
2018-05-23 22:31   ` Michael Clark
2018-05-23  0:14 ` [Qemu-devel] [PATCH v1 03/30] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps Michael Clark
2018-05-29 23:32   ` Alistair Francis
2018-05-23  0:14 ` [Qemu-devel] [PATCH v1 04/30] RISC-V: Simplify riscv_cpu_local_irqs_pending Michael Clark
2018-05-25 15:15   ` Richard Henderson
2018-05-23  0:14 ` [Qemu-devel] [PATCH v1 05/30] RISC-V: Allow setting and clearing multiple irqs Michael Clark
2018-05-23 23:55   ` Alistair Francis
2018-05-25 15:19   ` Richard Henderson
2018-05-23  0:14 ` [Qemu-devel] [PATCH v1 06/30] RISC-V: Move non-ops from op_helper to cpu_helper Michael Clark
2018-05-23 12:23   ` Philippe Mathieu-Daudé
2018-05-25 15:20   ` Richard Henderson
2018-05-23  0:14 ` [Qemu-devel] [PATCH v1 07/30] RISC-V: Update CSR and interrupt definitions Michael Clark
2018-05-23  0:14 ` [Qemu-devel] [PATCH v1 08/30] RISC-V: Implement modular CSR helper interface Michael Clark
2018-05-23  0:14 ` [Qemu-devel] [PATCH v1 09/30] RISC-V: Implement atomic mip/sip CSR updates Michael Clark
2018-05-29 23:34   ` Alistair Francis
2018-05-23  0:14 ` [Qemu-devel] [PATCH v1 10/30] RISC-V: Implement existential predicates for CSRs Michael Clark
2018-05-23  0:14 ` [Qemu-devel] [PATCH v1 11/30] RISC-V: Split out mstatus_fs from tb_flags Michael Clark
2018-05-23 12:25   ` Philippe Mathieu-Daudé
2018-05-29 23:40   ` Alistair Francis
2018-05-23  0:14 ` [Qemu-devel] [PATCH v1 12/30] RISC-V: Mark mstatus.fs dirty Michael Clark
2018-05-29 23:38   ` Alistair Francis
2018-05-23  0:15 ` [Qemu-devel] [PATCH v1 13/30] RISC-V: Implement mstatus.TSR/TW/TVM Michael Clark
2018-05-23 12:26   ` Philippe Mathieu-Daudé
2018-05-23  0:15 ` [Qemu-devel] [PATCH v1 14/30] RISC-V: Add public API for the CSR dispatch table Michael Clark
2018-05-23  0:15 ` [Qemu-devel] [PATCH v1 15/30] RISC-V: Add hartid and \n to interrupt logging Michael Clark
2018-05-23 12:33   ` Philippe Mathieu-Daudé
2018-05-24 22:47     ` Alistair Francis
2018-05-23  0:15 ` [Qemu-devel] [PATCH v1 16/30] RISC-V: Use riscv prefix consistently on cpu helpers Michael Clark
2018-05-23 12:36   ` Philippe Mathieu-Daudé
2018-05-29 23:43   ` Alistair Francis
2018-05-23  0:15 ` [Qemu-devel] [PATCH v1 17/30] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC Michael Clark
2018-05-23 12:37   ` Philippe Mathieu-Daudé
2018-05-29 23:47   ` Alistair Francis
2018-05-23  0:15 ` [Qemu-devel] [PATCH v1 18/30] RISC-V: Add missing free for plic_hart_config Michael Clark
2018-05-23 12:40   ` Philippe Mathieu-Daudé
2018-05-24 22:43     ` Alistair Francis
2018-05-23  0:15 ` [Qemu-devel] [PATCH v1 19/30] RISC-V: Allow interrupt controllers to claim interrupts Michael Clark
2018-05-23  0:15 ` [Qemu-devel] [PATCH v1 20/30] RISC-V: Add misa to DisasContext Michael Clark
2018-05-23 12:42   ` Philippe Mathieu-Daudé
2018-05-23  0:15 ` [Qemu-devel] [PATCH v1 21/30] RISC-V: Add misa.MAFD checks to translate Michael Clark
2018-05-23  0:15 ` [Qemu-devel] [PATCH v1 22/30] RISC-V: Add misa runtime write support Michael Clark
2018-05-25 18:53   ` Richard Henderson
2018-05-23  0:15 ` [Qemu-devel] [PATCH v1 23/30] RISC-V: Fix CLINT timecmp low 32-bit writes Michael Clark
2018-05-25 22:40   ` Alistair Francis
2018-05-23  0:15 ` [Qemu-devel] [PATCH v1 24/30] RISC-V: Fix PLIC pending bitfield reads Michael Clark
2018-05-25 22:38   ` Alistair Francis
2018-05-23  0:15 ` [Qemu-devel] [PATCH v1 25/30] RISC-V: Enable second UART on sifive_e and sifive_u Michael Clark
2018-05-23  0:15 ` [Qemu-devel] [PATCH v1 26/30] RISC-V: Remove unnecessary disassembler constraints Michael Clark
2018-05-24 22:45   ` Alistair Francis
2018-05-23  0:15 ` [Qemu-devel] [PATCH v1 27/30] elf: Add RISC-V PSABI ELF header defines Michael Clark
2018-05-23  6:44   ` Laurent Vivier
2018-05-25  7:17     ` Michael Clark
2018-05-23  0:15 ` Michael Clark [this message]
2018-05-23  0:15 ` [Qemu-devel] [PATCH v1 29/30] RISC-V: Don't add NULL bootargs to device-tree Michael Clark
2018-05-23 12:45   ` Philippe Mathieu-Daudé
2018-05-23  0:15 ` [Qemu-devel] [PATCH v1 30/30] RISC-V: Support separate firmware and kernel payload Michael Clark
2018-05-23 12:49   ` Philippe Mathieu-Daudé

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