From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137]) by ash.osuosl.org (Postfix) with ESMTP id EDC701C01CA for ; Fri, 25 May 2018 16:55:02 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by fraxinus.osuosl.org (Postfix) with ESMTP id EB4B087567 for ; Fri, 25 May 2018 16:55:02 +0000 (UTC) Received: from fraxinus.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KzbwOrK4_i_m for ; Fri, 25 May 2018 16:55:02 +0000 (UTC) Received: from mail-wr0-f193.google.com (mail-wr0-f193.google.com [209.85.128.193]) by fraxinus.osuosl.org (Postfix) with ESMTPS id 22A008768B for ; Fri, 25 May 2018 16:55:02 +0000 (UTC) Received: by mail-wr0-f193.google.com with SMTP id w18-v6so10338004wrn.6 for ; Fri, 25 May 2018 09:55:02 -0700 (PDT) From: Sergio Paracuellos Subject: [PATCH 3/7] staging: mt7621-gpio: fix masks for gpio pin Date: Fri, 25 May 2018 18:54:49 +0200 Message-Id: <1527267293-1862-4-git-send-email-sergio.paracuellos@gmail.com> In-Reply-To: <1527267293-1862-1-git-send-email-sergio.paracuellos@gmail.com> References: <1527267293-1862-1-git-send-email-sergio.paracuellos@gmail.com> List-Id: Linux Driver Project Developer List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: driverdev-devel-bounces@linuxdriverproject.org Sender: "devel" To: gregkh@linuxfoundation.org Cc: neil@brown.name, driverdev-devel@linuxdriverproject.org BIT macro is being used to get mask for gpio's pin which is retrieved using 'hwirq' from struct irq_data. The problem here is that 'hwirq' can be as large as 95, and 1UL << 95 is unlikely to work well. Instead of using BIT macro use a new PIN_MASK macro which takes into account pin and WIDTH of the bank in order to make a proper mask for the gpio pin. Also 'd->hwirq' has been replaced by 'pin' in some places because there was a 'pin' variable in changed functions with the proper value. This improves readability. Signed-off-by: Sergio Paracuellos Reviewed-by: NeilBrown --- drivers/staging/mt7621-gpio/gpio-mt7621.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/staging/mt7621-gpio/gpio-mt7621.c b/drivers/staging/mt7621-gpio/gpio-mt7621.c index d41cc3e..79452eb 100644 --- a/drivers/staging/mt7621-gpio/gpio-mt7621.c +++ b/drivers/staging/mt7621-gpio/gpio-mt7621.c @@ -16,6 +16,7 @@ #define MTK_BANK_CNT 3 #define MTK_BANK_WIDTH 32 +#define PIN_MASK(nr) (1UL << ((nr % MTK_BANK_WIDTH))) enum mediatek_gpio_reg { GPIO_REG_CTRL = 0, @@ -239,8 +240,8 @@ mediatek_gpio_irq_unmask(struct irq_data *d) fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); spin_lock_irqsave(&rg->lock, flags); - mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(d->hwirq) & rg->rising)); - mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(d->hwirq) & rg->falling)); + mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (PIN_MASK(pin) & rg->rising)); + mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (PIN_MASK(pin) & rg->falling)); spin_unlock_irqrestore(&rg->lock, flags); } @@ -261,8 +262,8 @@ mediatek_gpio_irq_mask(struct irq_data *d) fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); spin_lock_irqsave(&rg->lock, flags); - mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(d->hwirq)); - mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(d->hwirq)); + mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~PIN_MASK(pin)); + mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~PIN_MASK(pin)); spin_unlock_irqrestore(&rg->lock, flags); } @@ -273,7 +274,7 @@ mediatek_gpio_irq_type(struct irq_data *d, unsigned int type) int pin = d->hwirq; int bank = pin / MTK_BANK_WIDTH; struct mtk_gc *rg = gpio_data->gc_map[bank]; - u32 mask = BIT(d->hwirq); + u32 mask = PIN_MASK(pin); if (!rg) return -1; -- 2.7.4 _______________________________________________ devel mailing list devel@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel