From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932802AbeEaD3P (ORCPT ); Wed, 30 May 2018 23:29:15 -0400 Received: from ZXSHCAS1.zhaoxin.com ([203.148.12.81]:39883 "EHLO ZXSHCAS1.zhaoxin.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S932637AbeEaD3N (ORCPT ); Wed, 30 May 2018 23:29:13 -0400 From: David Wang To: , , , , , , , , CC: , , , , , , David Wang Subject: [PATCH] x86/mce: add CMCI support for Centaur CPUs Date: Thu, 31 May 2018 11:28:58 +0800 Message-ID: <1527737338-4036-1-git-send-email-davidwang@zhaoxin.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.29.8.54] X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To zxbjmbx3.zhaoxin.com (10.29.252.165) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Newer Centaur support CMCI mechanism, which is compatible with INTEL CMCI. Signed-off-by: David Wang --- arch/x86/Kconfig | 12 ++++++++++++ arch/x86/kernel/cpu/mcheck/mce.c | 6 ++++++ 2 files changed, 18 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index dda87a3..1adff5f 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1130,6 +1130,18 @@ config X86_MCE_AMD Additional support for AMD specific MCE features such as the DRAM Error Threshold. +config X86_MCE_CENTAUR + def_bool y + prompt "CENTAUR MCE features" + depends on CPU_SUP_CENTAUR && X86_MCE_INTEL + help + Additional support for Centaur specific MCE features such as + MCE broadcasting and CMCI support. + New Centaur CPU support MCE broadcasting. + New Centaur CPU support CMCI which is fully compliant with Intel CMCI. + + If unsure, say N here. + config X86_ANCIENT_MCE bool "Support for old Pentium 5 / WinChip machine checks" depends on X86_32 && X86_MCE diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index cd76380..2ebafc7 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -1727,6 +1727,7 @@ static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) } } +#ifdef CONFIG_X86_MCE_CENTAUR static void mce_centaur_feature_init(struct cpuinfo_x86 *c) { struct mca_config *cfg = &mca_cfg; @@ -1740,7 +1741,12 @@ static void mce_centaur_feature_init(struct cpuinfo_x86 *c) if (cfg->monarch_timeout < 0) cfg->monarch_timeout = USEC_PER_SEC; } + mce_intel_feature_init(c); + mce_adjust_timer = cmci_intel_adjust_timer; } +#else +static inline void mce_centaur_feature_init(struct cpuinfo_x86 *c) { } +#endif static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) { -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: x86/mce: add CMCI support for Centaur CPUs From: davidwang Message-Id: <1527737338-4036-1-git-send-email-davidwang@zhaoxin.com> Date: Thu, 31 May 2018 11:28:58 +0800 To: bp@alien8.de, tony.luck@intel.com, mingo@redhat.com, tglx@linutronix.de, hpa@zytor.com, gregkh@linuxfoudation.org, x86@kernel.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org Cc: brucechang@via-alliance.com, cooperyan@zhaoxin.com, qiyuanwang@zhaoxin.com, benjaminpan@viatech.com, lukelin@viacpu.com, timguo@zhaoxin.com, David Wang List-ID: TmV3ZXIgQ2VudGF1ciBzdXBwb3J0IENNQ0kgbWVjaGFuaXNtLCB3aGljaCBpcyBjb21wYXRpYmxl IHdpdGggSU5URUwgQ01DSS4KClNpZ25lZC1vZmYtYnk6IERhdmlkIFdhbmcgPGRhdmlkd2FuZ0B6 aGFveGluLmNvbT4KLS0tCiBhcmNoL3g4Ni9LY29uZmlnICAgICAgICAgICAgICAgICB8IDEyICsr KysrKysrKysrKwogYXJjaC94ODYva2VybmVsL2NwdS9tY2hlY2svbWNlLmMgfCAgNiArKysrKysK IDIgZmlsZXMgY2hhbmdlZCwgMTggaW5zZXJ0aW9ucygrKQoKZGlmZiAtLWdpdCBhL2FyY2gveDg2 L0tjb25maWcgYi9hcmNoL3g4Ni9LY29uZmlnCmluZGV4IGRkYTg3YTMuLjFhZGZmNWYgMTAwNjQ0 Ci0tLSBhL2FyY2gveDg2L0tjb25maWcKKysrIGIvYXJjaC94ODYvS2NvbmZpZwpAQCAtMTEzMCw2 ICsxMTMwLDE4IEBAIGNvbmZpZyBYODZfTUNFX0FNRAogCSAgIEFkZGl0aW9uYWwgc3VwcG9ydCBm b3IgQU1EIHNwZWNpZmljIE1DRSBmZWF0dXJlcyBzdWNoIGFzCiAJICAgdGhlIERSQU0gRXJyb3Ig VGhyZXNob2xkLgogCitjb25maWcgWDg2X01DRV9DRU5UQVVSCisJZGVmX2Jvb2wgeQorCXByb21w dCAiQ0VOVEFVUiBNQ0UgZmVhdHVyZXMiCisJZGVwZW5kcyBvbiBDUFVfU1VQX0NFTlRBVVIgJiYg WDg2X01DRV9JTlRFTAorCWhlbHAKKwkgICBBZGRpdGlvbmFsIHN1cHBvcnQgZm9yIENlbnRhdXIg c3BlY2lmaWMgTUNFIGZlYXR1cmVzIHN1Y2ggYXMKKwkgICBNQ0UgYnJvYWRjYXN0aW5nIGFuZCBD TUNJIHN1cHBvcnQuCisJICAgTmV3IENlbnRhdXIgQ1BVIHN1cHBvcnQgTUNFIGJyb2FkY2FzdGlu Zy4KKwkgICBOZXcgQ2VudGF1ciBDUFUgc3VwcG9ydCBDTUNJIHdoaWNoIGlzIGZ1bGx5IGNvbXBs aWFudCB3aXRoIEludGVsIENNQ0kuCisKKwkgICBJZiB1bnN1cmUsIHNheSBOIGhlcmUuCisKIGNv bmZpZyBYODZfQU5DSUVOVF9NQ0UKIAlib29sICJTdXBwb3J0IGZvciBvbGQgUGVudGl1bSA1IC8g V2luQ2hpcCBtYWNoaW5lIGNoZWNrcyIKIAlkZXBlbmRzIG9uIFg4Nl8zMiAmJiBYODZfTUNFCmRp ZmYgLS1naXQgYS9hcmNoL3g4Ni9rZXJuZWwvY3B1L21jaGVjay9tY2UuYyBiL2FyY2gveDg2L2tl cm5lbC9jcHUvbWNoZWNrL21jZS5jCmluZGV4IGNkNzYzODAuLjJlYmFmYzcgMTAwNjQ0Ci0tLSBh L2FyY2gveDg2L2tlcm5lbC9jcHUvbWNoZWNrL21jZS5jCisrKyBiL2FyY2gveDg2L2tlcm5lbC9j cHUvbWNoZWNrL21jZS5jCkBAIC0xNzI3LDYgKzE3MjcsNyBAQCBzdGF0aWMgdm9pZCBfX21jaGVj a19jcHVfaW5pdF9lYXJseShzdHJ1Y3QgY3B1aW5mb194ODYgKmMpCiAJfQogfQogCisjaWZkZWYg Q09ORklHX1g4Nl9NQ0VfQ0VOVEFVUgogc3RhdGljIHZvaWQgbWNlX2NlbnRhdXJfZmVhdHVyZV9p bml0KHN0cnVjdCBjcHVpbmZvX3g4NiAqYykKIHsKIAlzdHJ1Y3QgbWNhX2NvbmZpZyAqY2ZnID0g Jm1jYV9jZmc7CkBAIC0xNzQwLDcgKzE3NDEsMTIgQEAgc3RhdGljIHZvaWQgbWNlX2NlbnRhdXJf ZmVhdHVyZV9pbml0KHN0cnVjdCBjcHVpbmZvX3g4NiAqYykKIAkJaWYgKGNmZy0+bW9uYXJjaF90 aW1lb3V0IDwgMCkKIAkJCWNmZy0+bW9uYXJjaF90aW1lb3V0ID0gVVNFQ19QRVJfU0VDOwogCX0K KwltY2VfaW50ZWxfZmVhdHVyZV9pbml0KGMpOworCW1jZV9hZGp1c3RfdGltZXIgPSBjbWNpX2lu dGVsX2FkanVzdF90aW1lcjsKIH0KKyNlbHNlCitzdGF0aWMgaW5saW5lIHZvaWQgbWNlX2NlbnRh dXJfZmVhdHVyZV9pbml0KHN0cnVjdCBjcHVpbmZvX3g4NiAqYykgeyB9CisjZW5kaWYKIAogc3Rh dGljIHZvaWQgX19tY2hlY2tfY3B1X2luaXRfdmVuZG9yKHN0cnVjdCBjcHVpbmZvX3g4NiAqYykK IHsK