From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753926AbeEaFvP (ORCPT ); Thu, 31 May 2018 01:51:15 -0400 Received: from mga11.intel.com ([192.55.52.93]:55268 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751037AbeEaFvL (ORCPT ); Thu, 31 May 2018 01:51:11 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,462,1520924400"; d="scan'208";a="233383241" From: "Hean-Loong, Ong" To: Rob Herring , Dinh Nguyen , Daniel Vetter , Laurent Pinchart Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, hean.loong.ong@intel.com, yves.vandervennet@intel.com, chin.liang.see@intel.com, Ong@vger.kernel.org Subject: [PATCH 2/3] ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite Date: Thu, 31 May 2018 13:50:50 +0800 Message-Id: <1527745851-3339-3-git-send-email-hean.loong.ong@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1527745851-3339-1-git-send-email-hean.loong.ong@intel.com> References: <1527745851-3339-1-git-send-email-hean.loong.ong@intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ong Hean Loong Intel FPGA Video and Image Processing Suite Frame Buffer II driver config for Arria 10 devkit and its variants Signed-off-by: Ong, Hean Loong --- arch/arm/configs/socfpga_defconfig | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig index 2620ce7..d7deee8 100644 --- a/arch/arm/configs/socfpga_defconfig +++ b/arch/arm/configs/socfpga_defconfig @@ -111,6 +111,11 @@ CONFIG_MFD_ALTERA_A10SR=y CONFIG_MFD_STMPE=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_DRM=m +CONFIG_DRM_IVIP=m +CONFIG_DRM_IVIP_OF=m +CONFIG_FB=y +CONFIG_FB_SIMPLE=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_DWC2=y -- 1.7.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Hean-Loong, Ong" Subject: [PATCH 2/3] ARM:socfpga-defconfig Intel FPGA Video and Image Processing Suite Date: Thu, 31 May 2018 13:50:50 +0800 Message-ID: <1527745851-3339-3-git-send-email-hean.loong.ong@intel.com> References: <1527745851-3339-1-git-send-email-hean.loong.ong@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1527745851-3339-1-git-send-email-hean.loong.ong@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Rob Herring , Dinh Nguyen , Daniel Vetter , Laurent Pinchart Cc: devicetree@vger.kernel.org, yves.vandervennet@intel.com, hean.loong.ong@intel.com, chin.liang.see@intel.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Ong@freedesktop.org, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org RnJvbTogT25nIEhlYW4gTG9vbmcgPGhlYW4ubG9vbmcub25nQGludGVsLmNvbT4KCkludGVsIEZQ R0EgVmlkZW8gYW5kIEltYWdlIFByb2Nlc3NpbmcgU3VpdGUgRnJhbWUgQnVmZmVyIElJCmRyaXZl ciBjb25maWcgZm9yIEFycmlhIDEwIGRldmtpdCBhbmQgaXRzIHZhcmlhbnRzCgpTaWduZWQtb2Zm LWJ5OiBPbmcsIEhlYW4gTG9vbmcgPGhlYW4ubG9vbmcub25nQGludGVsLmNvbT4KLS0tCiBhcmNo L2FybS9jb25maWdzL3NvY2ZwZ2FfZGVmY29uZmlnIHwgICAgNSArKysrKwogMSBmaWxlcyBjaGFu Z2VkLCA1IGluc2VydGlvbnMoKyksIDAgZGVsZXRpb25zKC0pCgpkaWZmIC0tZ2l0IGEvYXJjaC9h cm0vY29uZmlncy9zb2NmcGdhX2RlZmNvbmZpZyBiL2FyY2gvYXJtL2NvbmZpZ3Mvc29jZnBnYV9k ZWZjb25maWcKaW5kZXggMjYyMGNlNy4uZDdkZWVlOCAxMDA2NDQKLS0tIGEvYXJjaC9hcm0vY29u Zmlncy9zb2NmcGdhX2RlZmNvbmZpZworKysgYi9hcmNoL2FybS9jb25maWdzL3NvY2ZwZ2FfZGVm Y29uZmlnCkBAIC0xMTEsNiArMTExLDExIEBAIENPTkZJR19NRkRfQUxURVJBX0ExMFNSPXkKIENP TkZJR19NRkRfU1RNUEU9eQogQ09ORklHX1JFR1VMQVRPUj15CiBDT05GSUdfUkVHVUxBVE9SX0ZJ WEVEX1ZPTFRBR0U9eQorQ09ORklHX0RSTT1tCitDT05GSUdfRFJNX0lWSVA9bQorQ09ORklHX0RS TV9JVklQX09GPW0KK0NPTkZJR19GQj15CitDT05GSUdfRkJfU0lNUExFPXkKIENPTkZJR19VU0I9 eQogQ09ORklHX1VTQl9TVE9SQUdFPXkKIENPTkZJR19VU0JfRFdDMj15Ci0tIAoxLjcuMQoKX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVsIG1h aWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMu ZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg==