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From: Anoob Joseph <anoob.joseph@caviumnetworks.com>
To: Akhil Goyal <akhil.goyal@nxp.com>,
	Pablo de Lara <pablo.de.lara.guarch@intel.com>,
	Thomas Monjalon <thomas@monjalon.net>
Cc: Srisivasubramanian Srinivasan
	<Srisivasubramanian.Srinivasan@cavium.com>,
	Ankur Dwivedi <ankur.dwivedi@cavium.com>,
	Jerin Jacob <jerin.jacob@caviumnetworks.com>,
	Murthy NSSR <Nidadavolu.Murthy@cavium.com>,
	Narayana Prasad <narayanaprasad.athreya@caviumnetworks.com>,
	Nithin Dabilpuram <nithin.dabilpuram@cavium.com>,
	Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>,
	dev@dpdk.org
Subject: [PATCH 11/16] crypto/cpt: add the basic device callback functions
Date: Fri,  8 Jun 2018 22:15:20 +0530	[thread overview]
Message-ID: <1528476325-15585-12-git-send-email-anoob.joseph@caviumnetworks.com> (raw)
In-Reply-To: <1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com>

From: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>

This patch addresses the following:
1. Adds the basic device operation functions for the cpt vf.
2. The probe/remove functions are staic so no need to declare in
the header file.
3. Removing extra declaration for cpt_dev_periodic_alarm_stop in the
header file.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@cavium.com>
Signed-off-by: Murthy NSSR <Nidadavolu.Murthy@cavium.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@cavium.com>
Signed-off-by: Ragothaman Jayaraman <Ragothaman.Jayaraman@cavium.com>
Signed-off-by: Srisivasubramanian Srinivasan <Srisivasubramanian.Srinivasan@cavium.com>
---
 drivers/crypto/cpt/Makefile            |   1 +
 drivers/crypto/cpt/cpt_pmd_cryptodev.c |  13 +-
 drivers/crypto/cpt/cpt_pmd_ops.c       | 544 +++++++++++++++++++++++++++++++++
 drivers/crypto/cpt/cpt_pmd_ops.h       |  64 ++++
 4 files changed, 616 insertions(+), 6 deletions(-)
 create mode 100644 drivers/crypto/cpt/cpt_pmd_ops.c
 create mode 100644 drivers/crypto/cpt/cpt_pmd_ops.h

diff --git a/drivers/crypto/cpt/Makefile b/drivers/crypto/cpt/Makefile
index 40ec9e2..bf22c2b 100644
--- a/drivers/crypto/cpt/Makefile
+++ b/drivers/crypto/cpt/Makefile
@@ -25,6 +25,7 @@ CFLAGS += -O3
 
 # PMD code
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_pmd_cryptodev.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_pmd_ops.c
 
 # Base code
 SRCS-$(CONFIG_RTE_LIBRTE_PMD_CPT) += cpt_device.c
diff --git a/drivers/crypto/cpt/cpt_pmd_cryptodev.c b/drivers/crypto/cpt/cpt_pmd_cryptodev.c
index addddd8..3939b5e 100644
--- a/drivers/crypto/cpt/cpt_pmd_cryptodev.c
+++ b/drivers/crypto/cpt/cpt_pmd_cryptodev.c
@@ -13,6 +13,7 @@
 
 #include "base/cpt_device.h"
 #include "cpt_pmd_logs.h"
+#include "cpt_pmd_ops.h"
 
 #define CSP_INTR_POLL_INTERVAL_MS 50
 
@@ -38,7 +39,7 @@
 				 cpt_pmd_alarm_cb, arg);
 }
 
-static int
+int
 cpt_pmd_periodic_alarm_stop(void *arg)
 {
 	return rte_eal_alarm_cancel(cpt_pmd_alarm_cb, arg);
@@ -46,11 +47,11 @@
 
 static struct rte_cryptodev_ops cptvf_ops = {
 	/* Device related operations */
-	.dev_configure = NULL,
-	.dev_start = NULL,
-	.dev_stop = NULL,
-	.dev_close = NULL,
-	.dev_infos_get = NULL,
+	.dev_configure = cpt_pmd_dev_config,
+	.dev_start = cpt_pmd_dev_start,
+	.dev_stop = cpt_pmd_dev_stop,
+	.dev_close = cpt_pmd_dev_close,
+	.dev_infos_get = cptvf_dev_info_get,
 
 	.stats_get = NULL,
 	.stats_reset = NULL,
diff --git a/drivers/crypto/cpt/cpt_pmd_ops.c b/drivers/crypto/cpt/cpt_pmd_ops.c
new file mode 100644
index 0000000..2f066cb
--- /dev/null
+++ b/drivers/crypto/cpt/cpt_pmd_ops.c
@@ -0,0 +1,544 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#include <rte_cryptodev_pmd.h>
+#include <rte_crypto.h>
+#include <rte_bus_pci.h>
+
+#include "cpt_pmd_logs.h"
+#include "cpt_pmd_ops.h"
+#include "base/cpt.h"
+#include "base/cpt_device.h"
+
+struct cpt_sess_misc {
+	uint16_t cpt_op:4;
+	uint16_t zsk_flag:4;
+	uint16_t aes_gcm:1;
+	uint16_t aes_ctr:1;
+	uint16_t dir_dma_supp:1; /* Single frag DMA supported? */
+	uint16_t is_gmac:1;
+	uint16_t aad_length;
+	uint8_t mac_len;
+	uint8_t iv_length; /**< IV length in bytes */
+	uint8_t auth_iv_length; /**< Auth IV length in bytes */
+	uint8_t rsvd1;
+	uint16_t iv_offset; /**< IV offset in bytes */
+	uint16_t auth_iv_offset; /**< Auth IV offset in bytes */
+	uint32_t salt;
+	phys_addr_t ctx_dma_addr;
+};
+
+/* Helper macros */
+
+#define SRC_IOV_SIZE \
+	(sizeof(iov_ptr_t) + (sizeof(buf_ptr_t) * MAX_SG_CNT))
+#define DST_IOV_SIZE \
+	(sizeof(iov_ptr_t) + (sizeof(buf_ptr_t) * MAX_SG_CNT))
+
+#define SESS_PRIV(__sess) \
+	(void *)((uint8_t *)__sess + sizeof(struct cpt_sess_misc))
+
+#define BYTE_LEN 8
+
+/* #define CPT_ALWAYS_USE_SG_MODE */
+#define CPT_ALWAYS_USE_SEPARATE_BUF
+
+/* TODO: Add all other capabilities */
+static const struct rte_cryptodev_capabilities cpt_capabilities[] = {
+	{	/* SHA1 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
+				.block_size = 64,
+				.key_size = {
+					.min = 64,
+					.max = 64,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 20,
+					.increment = 1
+				},
+				.aad_size = { 0 }
+			}, }
+		}, }
+	},
+	{	/* SHA224 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
+				.block_size = 64,
+					.key_size = {
+					.min = 64,
+					.max = 64,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 28,
+					.increment = 1
+				},
+				.aad_size = { 0 }
+			}, }
+		}, }
+	},
+	{	/* SHA256 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
+				.block_size = 64,
+				.key_size = {
+					.min = 64,
+					.max = 64,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 32,
+					.increment = 1
+				},
+				.aad_size = { 0 }
+			}, }
+		}, }
+	},
+	{	/* SHA384 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
+				.block_size = 64,
+				.key_size = {
+					.min = 64,
+					.max = 64,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 48,
+					.increment = 1
+					},
+				.aad_size = { 0 }
+			}, }
+		}, }
+	},
+	{	/* SHA512 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
+				.block_size = 128,
+				.key_size = {
+					.min = 64,
+					.max = 64,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 64,
+					.increment = 1
+				},
+				.aad_size = { 0 }
+			}, }
+		}, }
+	},
+	{	/* MD5 HMAC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_MD5_HMAC,
+				.block_size = 64,
+				.key_size = {
+					.min = 8,
+					.max = 64,
+					.increment = 8
+				},
+				.digest_size = {
+					.min = 1,
+					.max = 16,
+					.increment = 1
+				},
+				.aad_size = { 0 }
+			}, }
+		}, }
+	},
+	{	/* AES GCM */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,
+			{.aead = {
+				.algo = RTE_CRYPTO_AEAD_AES_GCM,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 32,
+					.increment = 8
+				},
+				.digest_size = {
+					.min = 8,
+					.max = 16,
+					.increment = 4
+				},
+				.aad_size = {
+					.min = 0,
+					.max = 1024,
+					.increment = 1
+				},
+				.iv_size = {
+					.min = 12,
+					.max = 12,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* AES GMAC (AUTH) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_AES_GMAC,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 32,
+					.increment = 8
+				},
+				.digest_size = {
+					.min = 8,
+					.max = 16,
+					.increment = 4
+				},
+				.aad_size = {
+					.min = 1,
+					.max = 65535,
+					.increment = 1
+				}
+			}, }
+		}, }
+	},
+	{	/* SNOW 3G (UIA2) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 4,
+					.max = 4,
+					.increment = 0
+				},
+				.aad_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* AES CBC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_AES_CBC,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 32,
+					.increment = 8
+				},
+				.iv_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* SNOW 3G (UEA2) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* AES CTR */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_AES_CTR,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 32,
+					.increment = 8
+				},
+				.iv_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* NULL (AUTH) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_NULL,
+				.block_size = 1,
+				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.aad_size = { 0 }
+			}, },
+		}, },
+	},
+	{	/* NULL (CIPHER) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_NULL,
+				.block_size = 1,
+				.key_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 0,
+					.max = 0,
+					.increment = 0
+				}
+			}, },
+		}, }
+	},
+	{       /* KASUMI (F8) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_KASUMI_F8,
+				.block_size = 8,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 8,
+					.max = 8,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* ZUC (EIA3) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_ZUC_EIA3,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 4,
+					.max = 4,
+					.increment = 0
+				},
+				.aad_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* ZUC (EEA3) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_ZUC_EEA3,
+				.block_size = 16,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{       /* KASUMI (F9) */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+			{.auth = {
+				.algo = RTE_CRYPTO_AUTH_KASUMI_F9,
+				.block_size = 8,
+				.key_size = {
+					.min = 16,
+					.max = 16,
+					.increment = 0
+				},
+				.digest_size = {
+					.min = 4,
+					.max = 4,
+					.increment = 0
+				},
+				.aad_size = {
+					.min = 8,
+					.max = 8,
+					.increment = 0
+				}
+			}, }
+		}, }
+	},
+	{	/* 3DES CBC */
+		.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+		{.sym = {
+			.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+			{.cipher = {
+				.algo = RTE_CRYPTO_CIPHER_3DES_CBC,
+				.block_size = 8,
+				.key_size = {
+					.min = 24,
+					.max = 24,
+					.increment = 0
+				},
+				.iv_size = {
+					.min = 8,
+					.max = 16,
+					.increment = 8
+				}
+			}, }
+		}, }
+	},
+	RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
+};
+
+int cpt_pmd_dev_config(struct rte_cryptodev *dev __rte_unused,
+		   struct rte_cryptodev_config *config __rte_unused)
+{
+	PMD_INIT_FUNC_TRACE();
+	return 0;
+}
+
+int cpt_pmd_dev_start(struct rte_cryptodev *c_dev __rte_unused)
+{
+	struct cpt_vf *cptvf = c_dev->data->dev_private;
+
+	PMD_INIT_FUNC_TRACE();
+
+	return cptvf_start_device(cptvf);
+}
+
+void cpt_pmd_dev_stop(struct rte_cryptodev *c_dev __rte_unused)
+{
+	struct cpt_vf *cptvf = c_dev->data->dev_private;
+
+	PMD_INIT_FUNC_TRACE();
+
+	cptvf_stop_device(cptvf);
+}
+
+int cpt_pmd_dev_close(struct rte_cryptodev *c_dev)
+{
+	struct cpt_vf *cptvf = c_dev->data->dev_private;
+	int i, ret;
+
+	PMD_INIT_FUNC_TRACE();
+
+	for (i = 0; i < c_dev->data->nb_queue_pairs; i++) {
+		ret = cpt_pmd_que_pair_release(c_dev, i);
+		if (ret)
+			return ret;
+	}
+	cpt_pmd_periodic_alarm_stop(cptvf);
+	cptvf_deinit_device(cptvf);
+
+	return 0;
+}
+
+void
+cptvf_dev_info_get(struct rte_cryptodev *dev, struct rte_cryptodev_info *info)
+{
+	PMD_INIT_FUNC_TRACE();
+	if (info != NULL) {
+		info->max_nb_queue_pairs = CPT_NUM_QS_PER_VF;
+		info->feature_flags = dev->feature_flags;
+		info->capabilities = cpt_capabilities;
+		/* TODO: Hardcoding as of now */
+		info->sym.max_nb_sessions = 128;
+		info->driver_id = cryptodev_cpt_driver_id;
+	}
+}
+
+int
+cpt_pmd_que_pair_release(struct rte_cryptodev *dev, uint16_t que_pair_id)
+{
+	cpt_instance_t *instance = dev->data->queue_pairs[que_pair_id];
+	int ret;
+
+	PMD_INIT_FUNC_TRACE();
+
+	ret = cptvf_put_resource(instance);
+	if (ret != 0) {
+		PMD_DRV_LOG(ERR, "Error putting instance handle"
+			    " of device %s : ret = %d\n", dev->data->name, ret);
+		return ret;
+	}
+
+	dev->data->queue_pairs[que_pair_id] = NULL;
+
+	return 0;
+}
diff --git a/drivers/crypto/cpt/cpt_pmd_ops.h b/drivers/crypto/cpt/cpt_pmd_ops.h
new file mode 100644
index 0000000..015b4a2
--- /dev/null
+++ b/drivers/crypto/cpt/cpt_pmd_ops.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
+ */
+
+#ifndef __CPT_PMD_OPS_H_
+#define __CPT_PMD_OPS_H_
+
+#include "base/cpt.h"
+
+#define CAVIUM_VENDOR_ID       0x177d
+#define NITROXIII_DEV_ID       0x11
+
+#define CSP_OP_CIPHER_ENCRYPT	0x1
+#define CSP_OP_CIPHER_DECRYPT	0x2
+#define CSP_OP_CIPHER_MASK	0x3
+
+#define CSP_OP_AUTH_VERIFY	0x4
+#define CSP_OP_AUTH_GENERATE	0x8
+#define CSP_OP_AUTH_MASK	0xC
+
+#define CSP_OP_ENCODE	(CSP_OP_CIPHER_ENCRYPT | CSP_OP_AUTH_GENERATE)
+#define CSP_OP_DECODE	(CSP_OP_CIPHER_DECRYPT | CSP_OP_AUTH_VERIFY)
+
+#define MAX_CIPHER_KEY_LEN  32
+#define MAX_AUTH_KEY_LEN    32
+#define DEFAULT_BLOCK_SIZE      64
+
+#define CSP_DDMA_AUTH		(1 << 1)
+#define CSP_DDMA_ENC		(1 << 2)
+#define CSP_DDMA_SUPPORTED	(CSP_DDMA_AUTH | CSP_DDMA_ENC)
+
+/*
+ * Space needed in packet for direct-dma operation.
+ * UCODE result & padding - 16 bytes max
+ * Result -  16 bytes
+ * struct cb_info size
+ */
+#define CSP_DDMA_EXTRA_SPACE (32 + sizeof(struct cpt_cb_info))
+
+#define ZS_EA 0x1
+#define ZS_IA 0x2
+#define K_F8 0x4
+#define K_F9 0x8
+
+extern uint8_t cryptodev_cpt_driver_id;
+extern int cpt_pmd_periodic_alarm_stop(void *arg);
+extern struct rte_mempool *cpt_meta_pool;
+extern int cpt_op_mlen;
+extern int cpt_op_sb_mlen;
+
+int cpt_pmd_dev_config(struct rte_cryptodev *dev __rte_unused,
+		   struct rte_cryptodev_config *config __rte_unused);
+int cpt_pmd_dev_start(struct rte_cryptodev *dev);
+
+void cpt_pmd_dev_stop(struct rte_cryptodev *dev);
+
+int cpt_pmd_dev_close(struct rte_cryptodev *dev);
+
+void cptvf_dev_info_get(struct rte_cryptodev *dev,
+			  struct rte_cryptodev_info *inf);
+
+int cpt_pmd_que_pair_release(struct rte_cryptodev *dev, uint16_t que_pair_id);
+
+#endif
-- 
1.9.3

  parent reply	other threads:[~2018-06-08 16:49 UTC|newest]

Thread overview: 185+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-08 16:45 [PATCH 00/16] Adding Cavium's crypto device(CPT) driver Anoob Joseph
2018-06-08 16:45 ` [PATCH 01/16] config: add Cavium CPT PMD skeleton Anoob Joseph
2018-06-14  2:56   ` Jerin Jacob
2018-06-19 13:39     ` De Lara Guarch, Pablo
2018-06-08 16:45 ` [PATCH 02/16] crypto/cpt/base: add hardware definitions Cavium CPT Anoob Joseph
2018-06-14  3:02   ` Jerin Jacob
2018-06-08 16:45 ` [PATCH 03/16] crypto/cpt/base: add hardware initialization API for CPT Anoob Joseph
2018-06-14  3:13   ` Jerin Jacob
2018-06-19 13:56     ` De Lara Guarch, Pablo
2018-06-08 16:45 ` [PATCH 04/16] crypto/cpt/base: add hardware enq/deq " Anoob Joseph
2018-06-14  3:20   ` Jerin Jacob
2018-06-19 14:36   ` De Lara Guarch, Pablo
2018-06-19 15:08   ` De Lara Guarch, Pablo
2018-06-08 16:45 ` [PATCH 05/16] crypto/cpt/base: add sym crypto session init " Anoob Joseph
2018-06-08 16:45 ` [PATCH 06/16] crypto/cpt/base: add sym crypto request prepare " Anoob Joseph
2018-06-14  3:24   ` Jerin Jacob
2018-06-08 16:45 ` [PATCH 07/16] crypto/cpt/base: add request prepare API for ZUC and SNOW3G Anoob Joseph
2018-06-08 16:45 ` [PATCH 08/16] crypto/cpt/base: add request prepare API for Kasumi Anoob Joseph
2018-06-08 16:45 ` [PATCH 09/16] crypto/cpt/base: add prepare request API for HASH and HMAC Anoob Joseph
2018-06-08 16:45 ` [PATCH 10/16] crypto/cpt: add driver initializations Anoob Joseph
2018-06-19 15:25   ` De Lara Guarch, Pablo
2018-06-08 16:45 ` Anoob Joseph [this message]
2018-06-19 15:58   ` [PATCH 11/16] crypto/cpt: add the basic device callback functions De Lara Guarch, Pablo
2018-06-08 16:45 ` [PATCH 12/16] crypto/cpt: adds some more callback functions for CPT Anoob Joseph
2018-06-08 16:45 ` [PATCH 13/16] crypto/cpt: adds the session related function callbacks Anoob Joseph
2018-06-08 16:45 ` [PATCH 14/16] crypto/cpt: adds the enqueue and dequeue callbacks Anoob Joseph
2018-06-08 16:45 ` [PATCH 15/16] doc: add Cavium's CPT guide Anoob Joseph
2018-06-19 16:10   ` De Lara Guarch, Pablo
2018-06-08 16:45 ` [PATCH 16/16] crypto/cpt: build with meson Anoob Joseph
2018-06-18 14:54   ` De Lara Guarch, Pablo
2018-06-18 13:02 ` [PATCH 00/16] Adding Cavium's crypto device(CPT) driver Anoob Joseph
2018-06-18 14:29   ` De Lara Guarch, Pablo
2018-07-09 22:55     ` De Lara Guarch, Pablo
2018-07-10  3:41       ` Anoob Joseph
2018-07-10  8:11         ` De Lara Guarch, Pablo
2018-09-04  3:58 ` [PATCH v2 00/33] Adding Cavium's OcteonTX crypto PMD Anoob Joseph
2018-09-04  3:58   ` [PATCH v2 01/33] config: add Cavium OcteonTX crypto PMD skeleton Anoob Joseph
2018-09-14 12:11     ` Akhil Goyal
2018-09-17  4:22       ` Joseph, Anoob
2018-09-17 10:37         ` Akhil Goyal
2018-09-17 11:42           ` Joseph, Anoob
2018-09-17 12:20             ` Akhil Goyal
2018-09-17 14:13               ` Joseph, Anoob
2018-09-17 14:36                 ` Thomas Monjalon
2018-09-17 14:50                   ` Joseph, Anoob
2018-09-18 12:31                 ` Akhil Goyal
2018-09-18 12:40                   ` Joseph
2018-09-18 12:44                     ` Akhil Goyal
2018-09-04  3:58   ` [PATCH v2 02/33] common/cpt: add common logging support Anoob Joseph
2018-09-14 12:29     ` Akhil Goyal
2018-09-04  3:58   ` [PATCH v2 03/33] crypto/octeontx: add PCI probe and remove Anoob Joseph
2018-09-14 12:39     ` Akhil Goyal
2018-09-17  4:40       ` Joseph, Anoob
2018-09-17 10:34         ` Akhil Goyal
2018-09-17 10:38           ` Joseph, Anoob
2018-09-04  3:58   ` [PATCH v2 04/33] crypto/octeontx: add register addresses Anoob Joseph
2018-09-04  3:58   ` [PATCH v2 05/33] common/cpt: add common code for init routine Anoob Joseph
2018-09-17 10:45     ` Akhil Goyal
2018-09-17 11:46       ` Thomas Monjalon
2018-09-17 12:29         ` Joseph, Anoob
2018-09-17 12:32         ` Akhil Goyal
2018-09-17 12:51           ` Thomas Monjalon
2018-09-04  3:58   ` [PATCH v2 06/33] crypto/octeontx: add hardware " Anoob Joseph
2018-09-04  3:58   ` [PATCH v2 07/33] common/cpt: add hardware register defines Anoob Joseph
2018-09-17 11:18     ` Akhil Goyal
2018-09-17 14:15       ` Joseph, Anoob
2018-09-04  3:58   ` [PATCH v2 08/33] crypto/octeontx: add hardware register access for misc poll Anoob Joseph
2018-09-04  3:58   ` [PATCH v2 09/33] crypto/octeontx: adds symmetric capabilities Anoob Joseph
2018-09-17 12:01     ` Akhil Goyal
2018-09-17 12:35       ` Joseph, Anoob
2018-09-24 11:36         ` Joseph, Anoob
2018-09-28 11:14           ` Joseph, Anoob
2018-10-01 10:05           ` Thomas Monjalon
2018-10-08 15:59             ` Trahe, Fiona
2018-10-08 20:27               ` Thomas Monjalon
2018-10-10  5:39                 ` Joseph, Anoob
2018-10-17  5:40                   ` Joseph, Anoob
2018-10-19 21:09                     ` Trahe, Fiona
2018-10-22  3:49                       ` Joseph, Anoob
2018-10-22  6:51                         ` Thomas Monjalon
2018-10-23  8:48                           ` Joseph, Anoob
2018-10-23  9:03                             ` Thomas Monjalon
2018-09-04  3:58   ` [PATCH v2 10/33] common/cpt: add PMD ops helper functions Anoob Joseph
2018-09-17 12:47     ` Akhil Goyal
2018-09-17 14:17       ` Joseph, Anoob
2018-09-04  3:58   ` [PATCH v2 11/33] crypto/octeontx: add global resource init Anoob Joseph
2018-09-04  3:58   ` [PATCH v2 12/33] crypto/octeontx: add mailbox routines Anoob Joseph
2018-09-04  3:59   ` [PATCH v2 13/33] crypto/octeontx: add basic dev ops Anoob Joseph
2018-09-04  3:59   ` [PATCH v2 14/33] common/cpt: add common macros for queue pair ops Anoob Joseph
2018-09-04  3:59   ` [PATCH v2 15/33] crypto/octeontx: add queue pair functions Anoob Joseph
2018-09-04  3:59   ` [PATCH v2 16/33] common/cpt: add common code required for session management Anoob Joseph
2018-09-04  3:59   ` [PATCH v2 17/33] crypto/octeontx: add session management ops Anoob Joseph
2018-09-04  3:59   ` [PATCH v2 18/33] common/cpt: add common code for fill session data Anoob Joseph
2018-09-04  3:59   ` [PATCH v2 19/33] crypto/octeontx: add supported sessions Anoob Joseph
2018-09-04  3:59   ` [PATCH v2 20/33] common/cpt: add common defines for microcode Anoob Joseph
2018-09-04  3:59   ` [PATCH v2 21/33] common/cpt: add microcode interface for encryption Anoob Joseph
2018-09-04  3:59   ` [PATCH v2 22/33] common/cpt: add microcode interface for decryption Anoob Joseph
2018-09-04  3:59   ` [PATCH v2 23/33] common/cpt: add crypo op enqueue request manager framework Anoob Joseph
2018-09-04  3:59   ` [PATCH v2 24/33] common/cpt: add support for zuc and snow3g Anoob Joseph
2018-09-04  3:59   ` [PATCH v2 25/33] common/cpt: add support for kasumi Anoob Joseph
2018-09-04  3:59   ` [PATCH v2 26/33] common/cpt: add support for hash Anoob Joseph
2018-09-04  3:59   ` [PATCH v2 27/33] crypto/octeontx: add routines to prepare instructions Anoob Joseph
2018-09-04  3:59   ` [PATCH v2 28/33] common/cpt: add common code for enqueuing cpt instruction Anoob Joseph
2018-09-04  3:59   ` [PATCH v2 29/33] crypto/octeontx: add enqueue burst op Anoob Joseph
2018-09-04  3:59   ` [PATCH v2 30/33] common/cpt: add common code for cpt dequeue Anoob Joseph
2018-09-04  3:59   ` [PATCH v2 31/33] crypto/octeontx: add dequeue burst op Anoob Joseph
2018-09-04  3:59   ` [PATCH v2 32/33] test: adds validation test Anoob Joseph
2018-09-04  3:59   ` [PATCH v2 33/33] doc: adds doc file Anoob Joseph
2018-09-17 13:30     ` Akhil Goyal
2018-09-14  9:16   ` [PATCH v2 00/33] Adding Cavium's OcteonTX crypto PMD Joseph, Anoob
2018-09-14  9:42     ` Akhil Goyal
2018-10-05 12:58   ` [PATCH v3 00/32] Adding Cavium's OCTEONTX " Anoob Joseph
2018-10-05 12:58     ` [PATCH v3 01/32] common/cpt: add common logging support Anoob Joseph
2018-10-08 12:27       ` Thomas Monjalon
2018-10-08 13:07         ` Joseph, Anoob
2018-10-08 13:37           ` Thomas Monjalon
2018-10-08 14:39             ` Anoob Joseph
2018-10-05 12:58     ` [PATCH v3 02/32] config: add Cavium OCTEONTX crypto PMD skeleton Anoob Joseph
2018-10-08 12:28       ` Thomas Monjalon
2018-10-05 12:58     ` [PATCH v3 03/32] crypto/octeontx: add register addresses Anoob Joseph
2018-10-05 12:58     ` [PATCH v3 04/32] common/cpt: add common code for init routine Anoob Joseph
2018-10-05 12:58     ` [PATCH v3 05/32] crypto/octeontx: add hardware " Anoob Joseph
2018-10-05 12:58     ` [PATCH v3 06/32] common/cpt: add hardware register defines Anoob Joseph
2018-10-05 12:58     ` [PATCH v3 07/32] crypto/octeontx: add hardware register access for misc poll Anoob Joseph
2018-10-05 12:58     ` [PATCH v3 08/32] crypto/octeontx: adds symmetric capabilities Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 09/32] common/cpt: add PMD ops helper functions Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 10/32] crypto/octeontx: add global resource init Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 11/32] crypto/octeontx: add mailbox routines Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 12/32] crypto/octeontx: add basic dev ops Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 13/32] common/cpt: add common macros for queue pair ops Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 14/32] crypto/octeontx: add queue pair functions Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 15/32] common/cpt: add common code required for session management Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 16/32] crypto/octeontx: add session management ops Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 17/32] common/cpt: add common code for fill session data Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 18/32] crypto/octeontx: add supported sessions Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 19/32] common/cpt: add common defines for microcode Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 20/32] common/cpt: add microcode interface for encryption Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 21/32] common/cpt: add microcode interface for decryption Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 22/32] common/cpt: add crypo op enqueue request manager framework Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 23/32] common/cpt: add support for zuc and snow3g Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 24/32] common/cpt: add support for kasumi Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 25/32] common/cpt: add support for hash Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 26/32] crypto/octeontx: add routines to prepare instructions Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 27/32] common/cpt: add common code for enqueuing cpt instruction Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 28/32] crypto/octeontx: add enqueue burst op Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 29/32] common/cpt: add common code for cpt dequeue Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 30/32] crypto/octeontx: add dequeue burst op Anoob Joseph
2018-10-05 12:59     ` [PATCH v3 31/32] test: adds validation test Anoob Joseph
2018-10-08 12:33       ` Akhil Goyal
2018-10-08 12:56         ` Akhil Goyal
2018-10-05 12:59     ` [PATCH v3 32/32] doc: adds doc file Anoob Joseph
2018-10-08 12:31       ` Thomas Monjalon
2018-10-05 13:04     ` [PATCH v3 00/32] Adding Cavium's OCTEONTX crypto PMD Akhil Goyal
2018-10-05 13:13       ` Joseph, Anoob
2018-10-05 13:14         ` Akhil Goyal
2018-10-05 13:35           ` Joseph, Anoob
2018-10-08 12:33     ` Thomas Monjalon
2018-10-08 12:58       ` Joseph, Anoob
2018-10-08 13:06         ` Thomas Monjalon
2018-10-09  9:07     ` [PATCH v4 00/23] Adding Cavium's OCTEON TX " Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 01/23] crypto/octeontx: add PMD skeleton Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 02/23] crypto/octeontx: add hardware init routine Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 03/23] crypto/octeontx: add hardware register access for misc poll Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 04/23] crypto/octeontx: add symmetric capabilities Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 05/23] common/cpt: add PMD ops helper functions Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 06/23] crypto/octeontx: add global resource init Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 07/23] crypto/octeontx: add mailbox routines Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 08/23] crypto/octeontx: add basic dev ops Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 09/23] crypto/octeontx: add queue pair functions Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 10/23] crypto/octeontx: add session management ops Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 11/23] crypto/octeontx: add supported sessions Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 12/23] common/cpt: add common defines for microcode Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 13/23] common/cpt: add microcode interface for encryption Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 14/23] common/cpt: add microcode interface for decryption Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 15/23] common/cpt: add crypo op enqueue request manager framework Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 16/23] common/cpt: support zuc and snow3g Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 17/23] common/cpt: support kasumi Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 18/23] common/cpt: support hash Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 19/23] crypto/octeontx: add routines to prepare instructions Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 20/23] crypto/octeontx: add enqueue burst op Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 21/23] crypto/octeontx: add dequeue " Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 22/23] test/crypto: add OCTEON TX unit tests Anoob Joseph
2018-10-09  9:07       ` [PATCH v4 23/23] doc: add documentation for OCTEON TX crypto Anoob Joseph
2018-10-09  9:56       ` [PATCH v4 00/23] Adding Cavium's OCTEON TX crypto PMD Thomas Monjalon
2018-10-09 10:29         ` Akhil Goyal

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