All of lore.kernel.org
 help / color / mirror / Atom feed
From: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
To: mpe@ellerman.id.au
Cc: linuxppc-dev@lists.ozlabs.org,
	Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Subject: [PATCH 0/2] constraints for power9 l2/l3 bus events
Date: Sun, 10 Jun 2018 19:57:00 +0530	[thread overview]
Message-ID: <1528640822-4800-1-git-send-email-maddy@linux.vnet.ibm.com> (raw)

This patch series adds constraints for power9 l2/l3 bus event.
In previous generation processors, both bus events and direct
events of performance monitoring unit can be individually
programmabled and monitored in PMCs.

But in Power9, L2/L3 bus events are always available as a
"bank" of events. To obtain the counts for any of the
l2/l3 bus events in a given bank, the user will have to
program PMC4 with corresponding l2/l3 bus event for that
bank.

Patch enforce two contraints incase of L2/L3 bus events.

1)Any L2/L3 event when programmed is also expected to program corresponding
PMC4 event from that group.
2)PMC4 event should always been programmed first due to group constraint
logic limitation

For ex. consider these L3 bus events

PM_L3_PF_ON_CHIP_MEM (0x460A0),
PM_L3_PF_MISS_L3 (0x160A0),
PM_L3_CO_MEM (0x260A0),
PM_L3_PF_ON_CHIP_CACHE (0x360A0),

1) This is an INVALID group for L3 Bus event monitoring,
since it is missing PMC4 event.
	perf stat -e "{r160A0,r260A0,r360A0}" < >

And this is a VALID group for L3 Bus events:
	perf stat -e "{r460A0,r160A0,r260A0,r360A0}" < >

2) This is an INVALID group for L3 Bus event monitoring,
since it is missing PMC4 event.
	perf stat -e "{r260A0,r360A0}" < >

And this is a VALID group for L3 Bus events:
	perf stat -e "{r460A0,r260A0,r360A0}" < >

3) This is an INVALID group for L3 Bus event monitoring,
since it is missing PMC4 event.
	perf stat -e "{r360A0}" < >

And this is a VALID group for L3 Bus events:
	perf stat -e "{r460A0,r360A0}" < >

Patch 2 of this series removes the l2 bus events added
to hw cache event array.

Madhavan Srinivasan (2):
  powerpc/perf: Add constraints for power9 l2/l3 bus events
  powerpc/perf: Remove l2 bus events from HW cache event array

 arch/powerpc/include/asm/perf_event_server.h |  2 ++
 arch/powerpc/perf/core-book3s.c              | 20 +++++++++++++++-----
 arch/powerpc/perf/isa207-common.c            | 28 ++++++++++++++++++----------
 arch/powerpc/perf/isa207-common.h            |  5 +++++
 arch/powerpc/perf/power9-pmu.c               | 10 ++++------
 5 files changed, 44 insertions(+), 21 deletions(-)

-- 
2.7.4

             reply	other threads:[~2018-06-10 14:27 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-10 14:27 Madhavan Srinivasan [this message]
2018-06-10 14:27 ` [PATCH 1/2] powerpc/perf: Add constraints for power9 l2/l3 bus events Madhavan Srinivasan
2018-12-22  9:54   ` [1/2] " Michael Ellerman
2018-06-10 14:27 ` [PATCH 2/2] powerpc/perf: Remove l2 bus events from HW cache event array Madhavan Srinivasan

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1528640822-4800-1-git-send-email-maddy@linux.vnet.ibm.com \
    --to=maddy@linux.vnet.ibm.com \
    --cc=linuxppc-dev@lists.ozlabs.org \
    --cc=mpe@ellerman.id.au \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.