From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dong Aisheng Subject: [PATCH V2 2/4] dt-bindings: arm: fsl: add mu binding doc Date: Sun, 17 Jun 2018 20:49:47 +0800 Message-ID: <1529239789-26849-3-git-send-email-aisheng.dong@nxp.com> References: <1529239789-26849-1-git-send-email-aisheng.dong@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1529239789-26849-1-git-send-email-aisheng.dong@nxp.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: linux-arm-kernel@lists.infradead.org Cc: Dong Aisheng , Mark Rutland , dongas86@gmail.com, devicetree@vger.kernel.org, Rob Herring , linux-imx@nxp.com, kernel@pengutronix.de, fabio.estevam@nxp.com, shawnguo@kernel.org List-Id: devicetree@vger.kernel.org The Messaging Unit module enables two processors within the SoC to communicate and coordinate by passing messages (e.g. data, status and control) through the MU interface. Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng --- v1->v2: * typo fixes * remove status property * remove imx6&7 compatible string which may be added later for the generic mailbox binding Note: Because MU used by SCU is not implemented as a mailbox driver, Instead, they're provided in library calls to gain higher performance. Futhermore, SCU MU has only one channel. But the binding doc claims (Change to allow 0?) So we did not follow the mailbox binding. For the generic mailbox driver binding way, it may be added later. --- .../devicetree/bindings/arm/freescale/fsl,mu.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,mu.txt diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,mu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,mu.txt new file mode 100644 index 0000000..c37aa1d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,mu.txt @@ -0,0 +1,32 @@ +NXP i.MX Messaging Unit (MU) +-------------------------------------------------------------------- + +The Messaging Unit module enables two processors within the SoC to +communicate and coordinate by passing messages (e.g. data, status +and control) through the MU interface. The MU also provides the ability +for one processor to signal the other processor using interrupts. + +Because the MU manages the messaging between processors, the MU uses +different clocks (from each side of the different peripheral buses). +Therefore, the MU must synchronize the accesses from one side to the +other. The MU accomplishes synchronization using two sets of matching +registers (Processor A-facing, Processor B-facing). + +Messaging Unit Device Node: +============================= + +Required properties: +------------------- +- compatible : should be "fsl,-mu", the supported chips include + imx8qxp, imx8qm. +- reg : Should contain the registers location and length +- interrupts : Interrupt number. The interrupt specifier format depends + on the interrupt controller parent. + +Examples: +-------- +lsio_mu0: mu@5d1b0000 { + compatible = "fsl,imx8qxp-mu"; + reg = <0x0 0x5d1b0000 0x0 0x10000>; + interrupts = ; +}; -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: aisheng.dong@nxp.com (Dong Aisheng) Date: Sun, 17 Jun 2018 20:49:47 +0800 Subject: [PATCH V2 2/4] dt-bindings: arm: fsl: add mu binding doc In-Reply-To: <1529239789-26849-1-git-send-email-aisheng.dong@nxp.com> References: <1529239789-26849-1-git-send-email-aisheng.dong@nxp.com> Message-ID: <1529239789-26849-3-git-send-email-aisheng.dong@nxp.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org The Messaging Unit module enables two processors within the SoC to communicate and coordinate by passing messages (e.g. data, status and control) through the MU interface. Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Cc: Rob Herring Cc: Mark Rutland Cc: devicetree at vger.kernel.org Signed-off-by: Dong Aisheng --- v1->v2: * typo fixes * remove status property * remove imx6&7 compatible string which may be added later for the generic mailbox binding Note: Because MU used by SCU is not implemented as a mailbox driver, Instead, they're provided in library calls to gain higher performance. Futhermore, SCU MU has only one channel. But the binding doc claims (Change to allow 0?) So we did not follow the mailbox binding. For the generic mailbox driver binding way, it may be added later. --- .../devicetree/bindings/arm/freescale/fsl,mu.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,mu.txt diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,mu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,mu.txt new file mode 100644 index 0000000..c37aa1d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,mu.txt @@ -0,0 +1,32 @@ +NXP i.MX Messaging Unit (MU) +-------------------------------------------------------------------- + +The Messaging Unit module enables two processors within the SoC to +communicate and coordinate by passing messages (e.g. data, status +and control) through the MU interface. The MU also provides the ability +for one processor to signal the other processor using interrupts. + +Because the MU manages the messaging between processors, the MU uses +different clocks (from each side of the different peripheral buses). +Therefore, the MU must synchronize the accesses from one side to the +other. The MU accomplishes synchronization using two sets of matching +registers (Processor A-facing, Processor B-facing). + +Messaging Unit Device Node: +============================= + +Required properties: +------------------- +- compatible : should be "fsl,-mu", the supported chips include + imx8qxp, imx8qm. +- reg : Should contain the registers location and length +- interrupts : Interrupt number. The interrupt specifier format depends + on the interrupt controller parent. + +Examples: +-------- +lsio_mu0: mu at 5d1b0000 { + compatible = "fsl,imx8qxp-mu"; + reg = <0x0 0x5d1b0000 0x0 0x10000>; + interrupts = ; +}; -- 2.7.4