From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C689FC43142 for ; Tue, 26 Jun 2018 08:54:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7B21F20A8B for ; Tue, 26 Jun 2018 08:54:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7B21F20A8B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932724AbeFZIyG (ORCPT ); Tue, 26 Jun 2018 04:54:06 -0400 Received: from regular1.263xmail.com ([211.150.99.131]:47213 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932206AbeFZIyD (ORCPT ); Tue, 26 Jun 2018 04:54:03 -0400 Received: from hjc?rock-chips.com (unknown [192.168.167.76]) by regular1.263xmail.com (Postfix) with ESMTP id 557465E08; Tue, 26 Jun 2018 16:53:52 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 5D67E323; Tue, 26 Jun 2018 16:53:48 +0800 (CST) X-RL-SENDER: hjc@rock-chips.com X-FST-TO: dri-devel@lists.freedesktop.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: hjc@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: hjc@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith SMTP id 27298DG8PVC; Tue, 26 Jun 2018 16:53:50 +0800 (CST) From: Sandy Huang To: dri-devel@lists.freedesktop.org, Sandy Huang , =?UTF-8?q?Heiko=20St=C3=BCbner?= , David Airlie Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] drm/rockchip: vop: add px30 vop support Date: Tue, 26 Jun 2018 16:53:35 +0800 Message-Id: <1530003215-46593-3-git-send-email-hjc@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530003215-46593-1-git-send-email-hjc@rock-chips.com> References: <1530003215-46593-1-git-send-email-hjc@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org PX30 have vop big and vop lite, just like rk3036 and rk3126 the max input and output resolution is 1920x1080, the main difference between the two vop is: vop big: win0 support yuv and rgb format; win1 and win2 support rgb format; vop lit: win1 support rgb format; Signed-off-by: Sandy Huang --- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 126 ++++++++++++++++++++++++++++ drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 74 ++++++++++++++++ 2 files changed, 200 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 08023d3..5af60eb 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -177,6 +177,128 @@ static const struct vop_data rk3126_vop = { .win_size = ARRAY_SIZE(rk3126_vop_win_data), }; +static const int px30_vop_intrs[] = { + FS_INTR, + 0, 0, + LINE_FLAG_INTR, + 0, + BUS_ERROR_INTR, + 0, 0, + DSP_HOLD_VALID_INTR, +}; + +static const struct vop_intr px30_intr = { + .intrs = px30_vop_intrs, + .nintrs = ARRAY_SIZE(px30_vop_intrs), + .line_flag_num[0] = VOP_REG(PX30_LINE_FLAG, 0xfff, 12), + .status = VOP_REG_SYNC(PX30_INTR_STATUS, 0xf, 0), + .enable = VOP_REG_SYNC(PX30_INTR_EN, 0xf, 4), + .clear = VOP_REG_SYNC(PX30_INTR_CLEAR, 0xf, 8), +}; + +static const struct vop_common px30_common = { + .standby = VOP_REG_SYNC(PX30_SYS_CTRL2, 0x1, 1), + .out_mode = VOP_REG(PX30_DSP_CTRL2, 0xf, 16), + .dsp_blank = VOP_REG(PX30_DSP_CTRL2, 0x1, 14), + .cfg_done = VOP_REG_SYNC(PX30_REG_CFG_DONE, 0x1, 0), +}; + +static const struct vop_modeset px30_modeset = { + .htotal_pw = VOP_REG(PX30_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), + .hact_st_end = VOP_REG(PX30_DSP_HACT_ST_END, 0x0fff0fff, 0), + .vtotal_pw = VOP_REG(PX30_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), + .vact_st_end = VOP_REG(PX30_DSP_VACT_ST_END, 0x0fff0fff, 0), +}; + +static const struct vop_output px30_output = { + .rgb_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0xf, 1), + .hdmi_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0xf, 9), + .mipi_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0xf, 25), + .rgb_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 0), + .hdmi_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 8), + .mipi_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 24), +}; + +static const struct vop_scl_regs px30_win_scl = { + .scale_yrgb_x = VOP_REG(PX30_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), + .scale_yrgb_y = VOP_REG(PX30_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), + .scale_cbcr_x = VOP_REG(PX30_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), + .scale_cbcr_y = VOP_REG(PX30_WIN0_SCL_FACTOR_CBR, 0xffff, 16), +}; + +static const struct vop_win_phy px30_win0_data = { + .scl = &px30_win_scl, + .data_formats = formats_win_full, + .nformats = ARRAY_SIZE(formats_win_full), + .enable = VOP_REG(PX30_WIN0_CTRL0, 0x1, 0), + .format = VOP_REG(PX30_WIN0_CTRL0, 0x7, 1), + .rb_swap = VOP_REG(PX30_WIN0_CTRL0, 0x1, 12), + .act_info = VOP_REG(PX30_WIN0_ACT_INFO, 0xffffffff, 0), + .dsp_info = VOP_REG(PX30_WIN0_DSP_INFO, 0xffffffff, 0), + .dsp_st = VOP_REG(PX30_WIN0_DSP_ST, 0xffffffff, 0), + .yrgb_mst = VOP_REG(PX30_WIN0_YRGB_MST0, 0xffffffff, 0), + .uv_mst = VOP_REG(PX30_WIN0_CBR_MST0, 0xffffffff, 0), + .yrgb_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 0), + .uv_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 16), +}; + +static const struct vop_win_phy px30_win1_data = { + .data_formats = formats_win_lite, + .nformats = ARRAY_SIZE(formats_win_lite), + .enable = VOP_REG(PX30_WIN1_CTRL0, 0x1, 0), + .format = VOP_REG(PX30_WIN1_CTRL0, 0x7, 4), + .rb_swap = VOP_REG(PX30_WIN1_CTRL0, 0x1, 12), + .dsp_info = VOP_REG(PX30_WIN1_DSP_INFO, 0xffffffff, 0), + .dsp_st = VOP_REG(PX30_WIN1_DSP_ST, 0xffffffff, 0), + .yrgb_mst = VOP_REG(PX30_WIN1_MST, 0xffffffff, 0), + .yrgb_vir = VOP_REG(PX30_WIN1_VIR, 0x1fff, 0), +}; + +static const struct vop_win_phy px30_win2_data = { + .data_formats = formats_win_lite, + .nformats = ARRAY_SIZE(formats_win_lite), + .gate = VOP_REG(PX30_WIN2_CTRL0, 0x1, 0), + .enable = VOP_REG(PX30_WIN2_CTRL0, 0x1, 4), + .format = VOP_REG(PX30_WIN2_CTRL0, 0x3, 5), + .rb_swap = VOP_REG(PX30_WIN2_CTRL0, 0x1, 20), + .dsp_info = VOP_REG(PX30_WIN2_DSP_INFO0, 0x0fff0fff, 0), + .dsp_st = VOP_REG(PX30_WIN2_DSP_ST0, 0x1fff1fff, 0), + .yrgb_mst = VOP_REG(PX30_WIN2_MST0, 0xffffffff, 0), + .yrgb_vir = VOP_REG(PX30_WIN2_VIR0_1, 0x1fff, 0), +}; + +static const struct vop_win_data px30_vop_lit_win_data[] = { + { .base = 0x00, .phy = &px30_win1_data, + .type = DRM_PLANE_TYPE_PRIMARY }, +}; + +static const struct vop_win_data px30_vop_big_win_data[] = { + { .base = 0x00, .phy = &px30_win0_data, + .type = DRM_PLANE_TYPE_PRIMARY }, + { .base = 0x00, .phy = &px30_win1_data, + .type = DRM_PLANE_TYPE_OVERLAY }, + { .base = 0x00, .phy = &px30_win2_data, + .type = DRM_PLANE_TYPE_CURSOR }, +}; + +static const struct vop_data px30_vop_lit = { + .intr = &px30_intr, + .common = &px30_common, + .modeset = &px30_modeset, + .output = &px30_output, + .win = px30_vop_lit_win_data, + .win_size = ARRAY_SIZE(px30_vop_lit_win_data), +}; + +static const struct vop_data px30_vop_big = { + .intr = &px30_intr, + .common = &px30_common, + .modeset = &px30_modeset, + .output = &px30_output, + .win = px30_vop_big_win_data, + .win_size = ARRAY_SIZE(px30_vop_big_win_data), +}; + static const struct vop_scl_extension rk3288_win_full_scl_ext = { .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), @@ -541,6 +663,10 @@ static const struct of_device_id vop_driver_dt_match[] = { .data = &rk3036_vop }, { .compatible = "rockchip,rk3126-vop", .data = &rk3126_vop }, + { .compatible = "rockchip,px30-vop-lit", + .data = &rk3126_vop } + { .compatible = "rockchip,px30-vop-big", + .data = &rk3126_vop } { .compatible = "rockchip,rk3288-vop", .data = &rk3288_vop }, { .compatible = "rockchip,rk3368-vop", diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index f81b510..71527cb 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -884,4 +884,78 @@ #define RK3126_WIN1_DSP_ST 0x54 /* rk3126 register definition end */ +/* px30 register definition */ +#define PX30_REG_CFG_DONE 0x00000 +#define PX30_VERSION 0x00004 +#define PX30_DSP_BG 0x00008 +#define PX30_MCU_CTRL 0x0000c +#define PX30_SYS_CTRL0 0x00010 +#define PX30_SYS_CTRL1 0x00014 +#define PX30_SYS_CTRL2 0x00018 +#define PX30_DSP_CTRL0 0x00020 +#define PX30_DSP_CTRL2 0x00028 +#define PX30_VOP_STATUS 0x0002c +#define PX30_LINE_FLAG 0x00030 +#define PX30_INTR_EN 0x00034 +#define PX30_INTR_CLEAR 0x00038 +#define PX30_INTR_STATUS 0x0003c +#define PX30_WIN0_CTRL0 0x00050 +#define PX30_WIN0_CTRL1 0x00054 +#define PX30_WIN0_COLOR_KEY 0x00058 +#define PX30_WIN0_VIR 0x0005c +#define PX30_WIN0_YRGB_MST0 0x00060 +#define PX30_WIN0_CBR_MST0 0x00064 +#define PX30_WIN0_ACT_INFO 0x00068 +#define PX30_WIN0_DSP_INFO 0x0006c +#define PX30_WIN0_DSP_ST 0x00070 +#define PX30_WIN0_SCL_FACTOR_YRGB 0x00074 +#define PX30_WIN0_SCL_FACTOR_CBR 0x00078 +#define PX30_WIN0_SCL_OFFSET 0x0007c +#define PX30_WIN0_ALPHA_CTRL 0x00080 +#define PX30_WIN1_CTRL0 0x00090 +#define PX30_WIN1_CTRL1 0x00094 +#define PX30_WIN1_VIR 0x00098 +#define PX30_WIN1_MST 0x000a0 +#define PX30_WIN1_DSP_INFO 0x000a4 +#define PX30_WIN1_DSP_ST 0x000a8 +#define PX30_WIN1_COLOR_KEY 0x000ac +#define PX30_WIN1_ALPHA_CTRL 0x000bc +#define PX30_HWC_CTRL0 0x000e0 +#define PX30_HWC_CTRL1 0x000e4 +#define PX30_HWC_MST 0x000e8 +#define PX30_HWC_DSP_ST 0x000ec +#define PX30_HWC_ALPHA_CTRL 0x000f0 +#define PX30_DSP_HTOTAL_HS_END 0x00100 +#define PX30_DSP_HACT_ST_END 0x00104 +#define PX30_DSP_VTOTAL_VS_END 0x00108 +#define PX30_DSP_VACT_ST_END 0x0010c +#define PX30_DSP_VS_ST_END_F1 0x00110 +#define PX30_DSP_VACT_ST_END_F1 0x00114 +#define PX30_BCSH_CTRL 0x00160 +#define PX30_BCSH_COL_BAR 0x00164 +#define PX30_BCSH_BCS 0x00168 +#define PX30_BCSH_H 0x0016c +#define PX30_FRC_LOWER01_0 0x00170 +#define PX30_FRC_LOWER01_1 0x00174 +#define PX30_FRC_LOWER10_0 0x00178 +#define PX30_FRC_LOWER10_1 0x0017c +#define PX30_FRC_LOWER11_0 0x00180 +#define PX30_FRC_LOWER11_1 0x00184 +#define PX30_MCU_RW_BYPASS_PORT 0x0018c +#define PX30_WIN2_CTRL0 0x00190 +#define PX30_WIN2_CTRL1 0x00194 +#define PX30_WIN2_VIR0_1 0x00198 +#define PX30_WIN2_VIR2_3 0x0019c +#define PX30_WIN2_MST0 0x001a0 +#define PX30_WIN2_DSP_INFO0 0x001a4 +#define PX30_WIN2_DSP_ST0 0x001a8 +#define PX30_WIN2_COLOR_KEY 0x001ac +#define PX30_WIN2_ALPHA_CTRL 0x001bc +#define PX30_BLANKING_VALUE 0x001f4 +#define PX30_FLAG_REG_FRM_VALID 0x001f8 +#define PX30_FLAG_REG 0x001fc +#define PX30_HWC_LUT_ADDR 0x00600 +#define PX30_GAMMA_LUT_ADDR 0x00a00 +/* px30 register definition end */ + #endif /* _ROCKCHIP_VOP_REG_H */ -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sandy Huang Subject: [PATCH 2/2] drm/rockchip: vop: add px30 vop support Date: Tue, 26 Jun 2018 16:53:35 +0800 Message-ID: <1530003215-46593-3-git-send-email-hjc@rock-chips.com> References: <1530003215-46593-1-git-send-email-hjc@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1530003215-46593-1-git-send-email-hjc@rock-chips.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org, Sandy Huang , =?UTF-8?q?Heiko=20St=C3=BCbner?= , David Airlie Cc: linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: linux-rockchip.vger.kernel.org UFgzMCBoYXZlIHZvcCBiaWcgYW5kIHZvcCBsaXRlLCBqdXN0IGxpa2UgcmszMDM2IGFuZCByazMx MjYKdGhlIG1heCBpbnB1dCBhbmQgb3V0cHV0IHJlc29sdXRpb24gaXMgMTkyMHgxMDgwLCB0aGUg bWFpbgpkaWZmZXJlbmNlIGJldHdlZW4gdGhlIHR3byB2b3AgaXM6Cgp2b3AgYmlnOgogICAgd2lu MCBzdXBwb3J0IHl1diBhbmQgcmdiIGZvcm1hdDsKICAgIHdpbjEgYW5kIHdpbjIgc3VwcG9ydCBy Z2IgZm9ybWF0Owp2b3AgbGl0OgogICAgd2luMSBzdXBwb3J0IHJnYiBmb3JtYXQ7CgpTaWduZWQt b2ZmLWJ5OiBTYW5keSBIdWFuZyA8aGpjQHJvY2stY2hpcHMuY29tPgotLS0KIGRyaXZlcnMvZ3B1 L2RybS9yb2NrY2hpcC9yb2NrY2hpcF92b3BfcmVnLmMgfCAxMjYgKysrKysrKysrKysrKysrKysr KysrKysrKysrKwogZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX3ZvcF9yZWcuaCB8 ICA3NCArKysrKysrKysrKysrKysrCiAyIGZpbGVzIGNoYW5nZWQsIDIwMCBpbnNlcnRpb25zKCsp CgpkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX3ZvcF9yZWcu YyBiL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9yb2NrY2hpcF92b3BfcmVnLmMKaW5kZXggMDgw MjNkMy4uNWFmNjBlYiAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tj aGlwX3ZvcF9yZWcuYworKysgYi9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9ja2NoaXBfdm9w X3JlZy5jCkBAIC0xNzcsNiArMTc3LDEyOCBAQCBzdGF0aWMgY29uc3Qgc3RydWN0IHZvcF9kYXRh IHJrMzEyNl92b3AgPSB7CiAJLndpbl9zaXplID0gQVJSQVlfU0laRShyazMxMjZfdm9wX3dpbl9k YXRhKSwKIH07CiAKK3N0YXRpYyBjb25zdCBpbnQgcHgzMF92b3BfaW50cnNbXSA9IHsKKwlGU19J TlRSLAorCTAsIDAsCisJTElORV9GTEFHX0lOVFIsCisJMCwKKwlCVVNfRVJST1JfSU5UUiwKKwkw LCAwLAorCURTUF9IT0xEX1ZBTElEX0lOVFIsCit9OworCitzdGF0aWMgY29uc3Qgc3RydWN0IHZv cF9pbnRyIHB4MzBfaW50ciA9IHsKKwkuaW50cnMgPSBweDMwX3ZvcF9pbnRycywKKwkubmludHJz ID0gQVJSQVlfU0laRShweDMwX3ZvcF9pbnRycyksCisJLmxpbmVfZmxhZ19udW1bMF0gPSBWT1Bf UkVHKFBYMzBfTElORV9GTEFHLCAweGZmZiwgMTIpLAorCS5zdGF0dXMgPSBWT1BfUkVHX1NZTkMo UFgzMF9JTlRSX1NUQVRVUywgMHhmLCAwKSwKKwkuZW5hYmxlID0gVk9QX1JFR19TWU5DKFBYMzBf SU5UUl9FTiwgMHhmLCA0KSwKKwkuY2xlYXIgPSBWT1BfUkVHX1NZTkMoUFgzMF9JTlRSX0NMRUFS LCAweGYsIDgpLAorfTsKKworc3RhdGljIGNvbnN0IHN0cnVjdCB2b3BfY29tbW9uIHB4MzBfY29t bW9uID0geworCS5zdGFuZGJ5ID0gVk9QX1JFR19TWU5DKFBYMzBfU1lTX0NUUkwyLCAweDEsIDEp LAorCS5vdXRfbW9kZSA9IFZPUF9SRUcoUFgzMF9EU1BfQ1RSTDIsIDB4ZiwgMTYpLAorCS5kc3Bf YmxhbmsgPSBWT1BfUkVHKFBYMzBfRFNQX0NUUkwyLCAweDEsIDE0KSwKKwkuY2ZnX2RvbmUgPSBW T1BfUkVHX1NZTkMoUFgzMF9SRUdfQ0ZHX0RPTkUsIDB4MSwgMCksCit9OworCitzdGF0aWMgY29u c3Qgc3RydWN0IHZvcF9tb2Rlc2V0IHB4MzBfbW9kZXNldCA9IHsKKwkuaHRvdGFsX3B3ID0gVk9Q X1JFRyhQWDMwX0RTUF9IVE9UQUxfSFNfRU5ELCAweDBmZmYwZmZmLCAwKSwKKwkuaGFjdF9zdF9l bmQgPSBWT1BfUkVHKFBYMzBfRFNQX0hBQ1RfU1RfRU5ELCAweDBmZmYwZmZmLCAwKSwKKwkudnRv dGFsX3B3ID0gVk9QX1JFRyhQWDMwX0RTUF9WVE9UQUxfVlNfRU5ELCAweDBmZmYwZmZmLCAwKSwK KwkudmFjdF9zdF9lbmQgPSBWT1BfUkVHKFBYMzBfRFNQX1ZBQ1RfU1RfRU5ELCAweDBmZmYwZmZm LCAwKSwKK307CisKK3N0YXRpYyBjb25zdCBzdHJ1Y3Qgdm9wX291dHB1dCBweDMwX291dHB1dCA9 IHsKKwkucmdiX3Bpbl9wb2wgPSBWT1BfUkVHKFBYMzBfRFNQX0NUUkwwLCAweGYsIDEpLAorCS5o ZG1pX3Bpbl9wb2wgPSBWT1BfUkVHKFBYMzBfRFNQX0NUUkwwLCAweGYsIDkpLAorCS5taXBpX3Bp bl9wb2wgPSBWT1BfUkVHKFBYMzBfRFNQX0NUUkwwLCAweGYsIDI1KSwKKwkucmdiX2VuID0gVk9Q X1JFRyhQWDMwX0RTUF9DVFJMMCwgMHgxLCAwKSwKKwkuaGRtaV9lbiA9IFZPUF9SRUcoUFgzMF9E U1BfQ1RSTDAsIDB4MSwgOCksCisJLm1pcGlfZW4gPSBWT1BfUkVHKFBYMzBfRFNQX0NUUkwwLCAw eDEsIDI0KSwKK307CisKK3N0YXRpYyBjb25zdCBzdHJ1Y3Qgdm9wX3NjbF9yZWdzIHB4MzBfd2lu X3NjbCA9IHsKKwkuc2NhbGVfeXJnYl94ID0gVk9QX1JFRyhQWDMwX1dJTjBfU0NMX0ZBQ1RPUl9Z UkdCLCAweGZmZmYsIDB4MCksCisJLnNjYWxlX3lyZ2JfeSA9IFZPUF9SRUcoUFgzMF9XSU4wX1ND TF9GQUNUT1JfWVJHQiwgMHhmZmZmLCAxNiksCisJLnNjYWxlX2NiY3JfeCA9IFZPUF9SRUcoUFgz MF9XSU4wX1NDTF9GQUNUT1JfQ0JSLCAweGZmZmYsIDB4MCksCisJLnNjYWxlX2NiY3JfeSA9IFZP UF9SRUcoUFgzMF9XSU4wX1NDTF9GQUNUT1JfQ0JSLCAweGZmZmYsIDE2KSwKK307CisKK3N0YXRp YyBjb25zdCBzdHJ1Y3Qgdm9wX3dpbl9waHkgcHgzMF93aW4wX2RhdGEgPSB7CisJLnNjbCA9ICZw eDMwX3dpbl9zY2wsCisJLmRhdGFfZm9ybWF0cyA9IGZvcm1hdHNfd2luX2Z1bGwsCisJLm5mb3Jt YXRzID0gQVJSQVlfU0laRShmb3JtYXRzX3dpbl9mdWxsKSwKKwkuZW5hYmxlID0gVk9QX1JFRyhQ WDMwX1dJTjBfQ1RSTDAsIDB4MSwgMCksCisJLmZvcm1hdCA9IFZPUF9SRUcoUFgzMF9XSU4wX0NU UkwwLCAweDcsIDEpLAorCS5yYl9zd2FwID0gVk9QX1JFRyhQWDMwX1dJTjBfQ1RSTDAsIDB4MSwg MTIpLAorCS5hY3RfaW5mbyA9IFZPUF9SRUcoUFgzMF9XSU4wX0FDVF9JTkZPLCAweGZmZmZmZmZm LCAwKSwKKwkuZHNwX2luZm8gPSBWT1BfUkVHKFBYMzBfV0lOMF9EU1BfSU5GTywgMHhmZmZmZmZm ZiwgMCksCisJLmRzcF9zdCA9IFZPUF9SRUcoUFgzMF9XSU4wX0RTUF9TVCwgMHhmZmZmZmZmZiwg MCksCisJLnlyZ2JfbXN0ID0gVk9QX1JFRyhQWDMwX1dJTjBfWVJHQl9NU1QwLCAweGZmZmZmZmZm LCAwKSwKKwkudXZfbXN0ID0gVk9QX1JFRyhQWDMwX1dJTjBfQ0JSX01TVDAsIDB4ZmZmZmZmZmYs IDApLAorCS55cmdiX3ZpciA9IFZPUF9SRUcoUFgzMF9XSU4wX1ZJUiwgMHgxZmZmLCAwKSwKKwku dXZfdmlyID0gVk9QX1JFRyhQWDMwX1dJTjBfVklSLCAweDFmZmYsIDE2KSwKK307CisKK3N0YXRp YyBjb25zdCBzdHJ1Y3Qgdm9wX3dpbl9waHkgcHgzMF93aW4xX2RhdGEgPSB7CisJLmRhdGFfZm9y bWF0cyA9IGZvcm1hdHNfd2luX2xpdGUsCisJLm5mb3JtYXRzID0gQVJSQVlfU0laRShmb3JtYXRz X3dpbl9saXRlKSwKKwkuZW5hYmxlID0gVk9QX1JFRyhQWDMwX1dJTjFfQ1RSTDAsIDB4MSwgMCks CisJLmZvcm1hdCA9IFZPUF9SRUcoUFgzMF9XSU4xX0NUUkwwLCAweDcsIDQpLAorCS5yYl9zd2Fw ID0gVk9QX1JFRyhQWDMwX1dJTjFfQ1RSTDAsIDB4MSwgMTIpLAorCS5kc3BfaW5mbyA9IFZPUF9S RUcoUFgzMF9XSU4xX0RTUF9JTkZPLCAweGZmZmZmZmZmLCAwKSwKKwkuZHNwX3N0ID0gVk9QX1JF RyhQWDMwX1dJTjFfRFNQX1NULCAweGZmZmZmZmZmLCAwKSwKKwkueXJnYl9tc3QgPSBWT1BfUkVH KFBYMzBfV0lOMV9NU1QsIDB4ZmZmZmZmZmYsIDApLAorCS55cmdiX3ZpciA9IFZPUF9SRUcoUFgz MF9XSU4xX1ZJUiwgMHgxZmZmLCAwKSwKK307CisKK3N0YXRpYyBjb25zdCBzdHJ1Y3Qgdm9wX3dp bl9waHkgcHgzMF93aW4yX2RhdGEgPSB7CisJLmRhdGFfZm9ybWF0cyA9IGZvcm1hdHNfd2luX2xp dGUsCisJLm5mb3JtYXRzID0gQVJSQVlfU0laRShmb3JtYXRzX3dpbl9saXRlKSwKKwkuZ2F0ZSA9 IFZPUF9SRUcoUFgzMF9XSU4yX0NUUkwwLCAweDEsIDApLAorCS5lbmFibGUgPSBWT1BfUkVHKFBY MzBfV0lOMl9DVFJMMCwgMHgxLCA0KSwKKwkuZm9ybWF0ID0gVk9QX1JFRyhQWDMwX1dJTjJfQ1RS TDAsIDB4MywgNSksCisJLnJiX3N3YXAgPSBWT1BfUkVHKFBYMzBfV0lOMl9DVFJMMCwgMHgxLCAy MCksCisJLmRzcF9pbmZvID0gVk9QX1JFRyhQWDMwX1dJTjJfRFNQX0lORk8wLCAweDBmZmYwZmZm LCAwKSwKKwkuZHNwX3N0ID0gVk9QX1JFRyhQWDMwX1dJTjJfRFNQX1NUMCwgMHgxZmZmMWZmZiwg MCksCisJLnlyZ2JfbXN0ID0gVk9QX1JFRyhQWDMwX1dJTjJfTVNUMCwgMHhmZmZmZmZmZiwgMCks CisJLnlyZ2JfdmlyID0gVk9QX1JFRyhQWDMwX1dJTjJfVklSMF8xLCAweDFmZmYsIDApLAorfTsK Kworc3RhdGljIGNvbnN0IHN0cnVjdCB2b3Bfd2luX2RhdGEgcHgzMF92b3BfbGl0X3dpbl9kYXRh W10gPSB7CisJeyAuYmFzZSA9IDB4MDAsIC5waHkgPSAmcHgzMF93aW4xX2RhdGEsCisJICAudHlw ZSA9IERSTV9QTEFORV9UWVBFX1BSSU1BUlkgfSwKK307CisKK3N0YXRpYyBjb25zdCBzdHJ1Y3Qg dm9wX3dpbl9kYXRhIHB4MzBfdm9wX2JpZ193aW5fZGF0YVtdID0geworCXsgLmJhc2UgPSAweDAw LCAucGh5ID0gJnB4MzBfd2luMF9kYXRhLAorCSAgLnR5cGUgPSBEUk1fUExBTkVfVFlQRV9QUklN QVJZIH0sCisJeyAuYmFzZSA9IDB4MDAsIC5waHkgPSAmcHgzMF93aW4xX2RhdGEsCisJICAudHlw ZSA9IERSTV9QTEFORV9UWVBFX09WRVJMQVkgfSwKKwl7IC5iYXNlID0gMHgwMCwgLnBoeSA9ICZw eDMwX3dpbjJfZGF0YSwKKwkgIC50eXBlID0gRFJNX1BMQU5FX1RZUEVfQ1VSU09SIH0sCit9Owor CitzdGF0aWMgY29uc3Qgc3RydWN0IHZvcF9kYXRhIHB4MzBfdm9wX2xpdCA9IHsKKwkuaW50ciA9 ICZweDMwX2ludHIsCisJLmNvbW1vbiA9ICZweDMwX2NvbW1vbiwKKwkubW9kZXNldCA9ICZweDMw X21vZGVzZXQsCisJLm91dHB1dCA9ICZweDMwX291dHB1dCwKKwkud2luID0gcHgzMF92b3BfbGl0 X3dpbl9kYXRhLAorCS53aW5fc2l6ZSA9IEFSUkFZX1NJWkUocHgzMF92b3BfbGl0X3dpbl9kYXRh KSwKK307CisKK3N0YXRpYyBjb25zdCBzdHJ1Y3Qgdm9wX2RhdGEgcHgzMF92b3BfYmlnID0gewor CS5pbnRyID0gJnB4MzBfaW50ciwKKwkuY29tbW9uID0gJnB4MzBfY29tbW9uLAorCS5tb2Rlc2V0 ID0gJnB4MzBfbW9kZXNldCwKKwkub3V0cHV0ID0gJnB4MzBfb3V0cHV0LAorCS53aW4gPSBweDMw X3ZvcF9iaWdfd2luX2RhdGEsCisJLndpbl9zaXplID0gQVJSQVlfU0laRShweDMwX3ZvcF9iaWdf d2luX2RhdGEpLAorfTsKKwogc3RhdGljIGNvbnN0IHN0cnVjdCB2b3Bfc2NsX2V4dGVuc2lvbiBy azMyODhfd2luX2Z1bGxfc2NsX2V4dCA9IHsKIAkuY2Jjcl92c2RfbW9kZSA9IFZPUF9SRUcoUksz Mjg4X1dJTjBfQ1RSTDEsIDB4MSwgMzEpLAogCS5jYmNyX3ZzdV9tb2RlID0gVk9QX1JFRyhSSzMy ODhfV0lOMF9DVFJMMSwgMHgxLCAzMCksCkBAIC01NDEsNiArNjYzLDEwIEBAIHN0YXRpYyBjb25z dCBzdHJ1Y3Qgb2ZfZGV2aWNlX2lkIHZvcF9kcml2ZXJfZHRfbWF0Y2hbXSA9IHsKIAkgIC5kYXRh ID0gJnJrMzAzNl92b3AgfSwKIAl7IC5jb21wYXRpYmxlID0gInJvY2tjaGlwLHJrMzEyNi12b3Ai LAogCSAgLmRhdGEgPSAmcmszMTI2X3ZvcCB9LAorCXsgLmNvbXBhdGlibGUgPSAicm9ja2NoaXAs cHgzMC12b3AtbGl0IiwKKwkgIC5kYXRhID0gJnJrMzEyNl92b3AgfQorCXsgLmNvbXBhdGlibGUg PSAicm9ja2NoaXAscHgzMC12b3AtYmlnIiwKKwkgIC5kYXRhID0gJnJrMzEyNl92b3AgfQogCXsg LmNvbXBhdGlibGUgPSAicm9ja2NoaXAscmszMjg4LXZvcCIsCiAJICAuZGF0YSA9ICZyazMyODhf dm9wIH0sCiAJeyAuY29tcGF0aWJsZSA9ICJyb2NrY2hpcCxyazMzNjgtdm9wIiwKZGlmZiAtLWdp dCBhL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9yb2NrY2hpcF92b3BfcmVnLmggYi9kcml2ZXJz L2dwdS9kcm0vcm9ja2NoaXAvcm9ja2NoaXBfdm9wX3JlZy5oCmluZGV4IGY4MWI1MTAuLjcxNTI3 Y2IgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9yb2NrY2hpcF92b3BfcmVn LmgKKysrIGIvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX3ZvcF9yZWcuaApAQCAt ODg0LDQgKzg4NCw3OCBAQAogI2RlZmluZSBSSzMxMjZfV0lOMV9EU1BfU1QJCTB4NTQKIC8qIHJr MzEyNiByZWdpc3RlciBkZWZpbml0aW9uIGVuZCAqLwogCisvKiBweDMwIHJlZ2lzdGVyIGRlZmlu aXRpb24gKi8KKyNkZWZpbmUgUFgzMF9SRUdfQ0ZHX0RPTkUJCQkweDAwMDAwCisjZGVmaW5lIFBY MzBfVkVSU0lPTgkJCQkweDAwMDA0CisjZGVmaW5lIFBYMzBfRFNQX0JHCQkJCTB4MDAwMDgKKyNk ZWZpbmUgUFgzMF9NQ1VfQ1RSTAkJCQkweDAwMDBjCisjZGVmaW5lIFBYMzBfU1lTX0NUUkwwCQkJ CTB4MDAwMTAKKyNkZWZpbmUgUFgzMF9TWVNfQ1RSTDEJCQkJMHgwMDAxNAorI2RlZmluZSBQWDMw X1NZU19DVFJMMgkJCQkweDAwMDE4CisjZGVmaW5lIFBYMzBfRFNQX0NUUkwwCQkJCTB4MDAwMjAK KyNkZWZpbmUgUFgzMF9EU1BfQ1RSTDIJCQkJMHgwMDAyOAorI2RlZmluZSBQWDMwX1ZPUF9TVEFU VVMJCQkJMHgwMDAyYworI2RlZmluZSBQWDMwX0xJTkVfRkxBRwkJCQkweDAwMDMwCisjZGVmaW5l IFBYMzBfSU5UUl9FTgkJCQkweDAwMDM0CisjZGVmaW5lIFBYMzBfSU5UUl9DTEVBUgkJCQkweDAw MDM4CisjZGVmaW5lIFBYMzBfSU5UUl9TVEFUVVMJCQkweDAwMDNjCisjZGVmaW5lIFBYMzBfV0lO MF9DVFJMMAkJCQkweDAwMDUwCisjZGVmaW5lIFBYMzBfV0lOMF9DVFJMMQkJCQkweDAwMDU0Cisj ZGVmaW5lIFBYMzBfV0lOMF9DT0xPUl9LRVkJCQkweDAwMDU4CisjZGVmaW5lIFBYMzBfV0lOMF9W SVIJCQkJMHgwMDA1YworI2RlZmluZSBQWDMwX1dJTjBfWVJHQl9NU1QwCQkJMHgwMDA2MAorI2Rl ZmluZSBQWDMwX1dJTjBfQ0JSX01TVDAJCQkweDAwMDY0CisjZGVmaW5lIFBYMzBfV0lOMF9BQ1Rf SU5GTwkJCTB4MDAwNjgKKyNkZWZpbmUgUFgzMF9XSU4wX0RTUF9JTkZPCQkJMHgwMDA2YworI2Rl ZmluZSBQWDMwX1dJTjBfRFNQX1NUCQkJMHgwMDA3MAorI2RlZmluZSBQWDMwX1dJTjBfU0NMX0ZB Q1RPUl9ZUkdCCQkweDAwMDc0CisjZGVmaW5lIFBYMzBfV0lOMF9TQ0xfRkFDVE9SX0NCUgkJMHgw MDA3OAorI2RlZmluZSBQWDMwX1dJTjBfU0NMX09GRlNFVAkJCTB4MDAwN2MKKyNkZWZpbmUgUFgz MF9XSU4wX0FMUEhBX0NUUkwJCQkweDAwMDgwCisjZGVmaW5lIFBYMzBfV0lOMV9DVFJMMAkJCQkw eDAwMDkwCisjZGVmaW5lIFBYMzBfV0lOMV9DVFJMMQkJCQkweDAwMDk0CisjZGVmaW5lIFBYMzBf V0lOMV9WSVIJCQkJMHgwMDA5OAorI2RlZmluZSBQWDMwX1dJTjFfTVNUCQkJCTB4MDAwYTAKKyNk ZWZpbmUgUFgzMF9XSU4xX0RTUF9JTkZPCQkJMHgwMDBhNAorI2RlZmluZSBQWDMwX1dJTjFfRFNQ X1NUCQkJMHgwMDBhOAorI2RlZmluZSBQWDMwX1dJTjFfQ09MT1JfS0VZCQkJMHgwMDBhYworI2Rl ZmluZSBQWDMwX1dJTjFfQUxQSEFfQ1RSTAkJCTB4MDAwYmMKKyNkZWZpbmUgUFgzMF9IV0NfQ1RS TDAJCQkJMHgwMDBlMAorI2RlZmluZSBQWDMwX0hXQ19DVFJMMQkJCQkweDAwMGU0CisjZGVmaW5l IFBYMzBfSFdDX01TVAkJCQkweDAwMGU4CisjZGVmaW5lIFBYMzBfSFdDX0RTUF9TVAkJCQkweDAw MGVjCisjZGVmaW5lIFBYMzBfSFdDX0FMUEhBX0NUUkwJCQkweDAwMGYwCisjZGVmaW5lIFBYMzBf RFNQX0hUT1RBTF9IU19FTkQJCQkweDAwMTAwCisjZGVmaW5lIFBYMzBfRFNQX0hBQ1RfU1RfRU5E CQkJMHgwMDEwNAorI2RlZmluZSBQWDMwX0RTUF9WVE9UQUxfVlNfRU5ECQkJMHgwMDEwOAorI2Rl ZmluZSBQWDMwX0RTUF9WQUNUX1NUX0VORAkJCTB4MDAxMGMKKyNkZWZpbmUgUFgzMF9EU1BfVlNf U1RfRU5EX0YxCQkJMHgwMDExMAorI2RlZmluZSBQWDMwX0RTUF9WQUNUX1NUX0VORF9GMQkJCTB4 MDAxMTQKKyNkZWZpbmUgUFgzMF9CQ1NIX0NUUkwJCQkJMHgwMDE2MAorI2RlZmluZSBQWDMwX0JD U0hfQ09MX0JBUgkJCTB4MDAxNjQKKyNkZWZpbmUgUFgzMF9CQ1NIX0JDUwkJCQkweDAwMTY4Cisj ZGVmaW5lIFBYMzBfQkNTSF9ICQkJCTB4MDAxNmMKKyNkZWZpbmUgUFgzMF9GUkNfTE9XRVIwMV8w CQkJMHgwMDE3MAorI2RlZmluZSBQWDMwX0ZSQ19MT1dFUjAxXzEJCQkweDAwMTc0CisjZGVmaW5l IFBYMzBfRlJDX0xPV0VSMTBfMAkJCTB4MDAxNzgKKyNkZWZpbmUgUFgzMF9GUkNfTE9XRVIxMF8x CQkJMHgwMDE3YworI2RlZmluZSBQWDMwX0ZSQ19MT1dFUjExXzAJCQkweDAwMTgwCisjZGVmaW5l IFBYMzBfRlJDX0xPV0VSMTFfMQkJCTB4MDAxODQKKyNkZWZpbmUgUFgzMF9NQ1VfUldfQllQQVNT X1BPUlQJCQkweDAwMThjCisjZGVmaW5lIFBYMzBfV0lOMl9DVFJMMAkJCQkweDAwMTkwCisjZGVm aW5lIFBYMzBfV0lOMl9DVFJMMQkJCQkweDAwMTk0CisjZGVmaW5lIFBYMzBfV0lOMl9WSVIwXzEJ CQkweDAwMTk4CisjZGVmaW5lIFBYMzBfV0lOMl9WSVIyXzMJCQkweDAwMTljCisjZGVmaW5lIFBY MzBfV0lOMl9NU1QwCQkJCTB4MDAxYTAKKyNkZWZpbmUgUFgzMF9XSU4yX0RTUF9JTkZPMAkJCTB4 MDAxYTQKKyNkZWZpbmUgUFgzMF9XSU4yX0RTUF9TVDAJCQkweDAwMWE4CisjZGVmaW5lIFBYMzBf V0lOMl9DT0xPUl9LRVkJCQkweDAwMWFjCisjZGVmaW5lIFBYMzBfV0lOMl9BTFBIQV9DVFJMCQkJ MHgwMDFiYworI2RlZmluZSBQWDMwX0JMQU5LSU5HX1ZBTFVFCQkJMHgwMDFmNAorI2RlZmluZSBQ WDMwX0ZMQUdfUkVHX0ZSTV9WQUxJRAkJCTB4MDAxZjgKKyNkZWZpbmUgUFgzMF9GTEFHX1JFRwkJ CQkweDAwMWZjCisjZGVmaW5lIFBYMzBfSFdDX0xVVF9BRERSCQkJMHgwMDYwMAorI2RlZmluZSBQ WDMwX0dBTU1BX0xVVF9BRERSCQkJMHgwMGEwMAorLyogcHgzMCByZWdpc3RlciBkZWZpbml0aW9u IGVuZCAqLworCiAjZW5kaWYgLyogX1JPQ0tDSElQX1ZPUF9SRUdfSCAqLwotLSAKMi43LjQKCgpf X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwg bWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0 cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 From: hjc@rock-chips.com (Sandy Huang) Date: Tue, 26 Jun 2018 16:53:35 +0800 Subject: [PATCH 2/2] drm/rockchip: vop: add px30 vop support In-Reply-To: <1530003215-46593-1-git-send-email-hjc@rock-chips.com> References: <1530003215-46593-1-git-send-email-hjc@rock-chips.com> Message-ID: <1530003215-46593-3-git-send-email-hjc@rock-chips.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org PX30 have vop big and vop lite, just like rk3036 and rk3126 the max input and output resolution is 1920x1080, the main difference between the two vop is: vop big: win0 support yuv and rgb format; win1 and win2 support rgb format; vop lit: win1 support rgb format; Signed-off-by: Sandy Huang --- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 126 ++++++++++++++++++++++++++++ drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 74 ++++++++++++++++ 2 files changed, 200 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 08023d3..5af60eb 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -177,6 +177,128 @@ static const struct vop_data rk3126_vop = { .win_size = ARRAY_SIZE(rk3126_vop_win_data), }; +static const int px30_vop_intrs[] = { + FS_INTR, + 0, 0, + LINE_FLAG_INTR, + 0, + BUS_ERROR_INTR, + 0, 0, + DSP_HOLD_VALID_INTR, +}; + +static const struct vop_intr px30_intr = { + .intrs = px30_vop_intrs, + .nintrs = ARRAY_SIZE(px30_vop_intrs), + .line_flag_num[0] = VOP_REG(PX30_LINE_FLAG, 0xfff, 12), + .status = VOP_REG_SYNC(PX30_INTR_STATUS, 0xf, 0), + .enable = VOP_REG_SYNC(PX30_INTR_EN, 0xf, 4), + .clear = VOP_REG_SYNC(PX30_INTR_CLEAR, 0xf, 8), +}; + +static const struct vop_common px30_common = { + .standby = VOP_REG_SYNC(PX30_SYS_CTRL2, 0x1, 1), + .out_mode = VOP_REG(PX30_DSP_CTRL2, 0xf, 16), + .dsp_blank = VOP_REG(PX30_DSP_CTRL2, 0x1, 14), + .cfg_done = VOP_REG_SYNC(PX30_REG_CFG_DONE, 0x1, 0), +}; + +static const struct vop_modeset px30_modeset = { + .htotal_pw = VOP_REG(PX30_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), + .hact_st_end = VOP_REG(PX30_DSP_HACT_ST_END, 0x0fff0fff, 0), + .vtotal_pw = VOP_REG(PX30_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), + .vact_st_end = VOP_REG(PX30_DSP_VACT_ST_END, 0x0fff0fff, 0), +}; + +static const struct vop_output px30_output = { + .rgb_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0xf, 1), + .hdmi_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0xf, 9), + .mipi_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0xf, 25), + .rgb_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 0), + .hdmi_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 8), + .mipi_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 24), +}; + +static const struct vop_scl_regs px30_win_scl = { + .scale_yrgb_x = VOP_REG(PX30_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), + .scale_yrgb_y = VOP_REG(PX30_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), + .scale_cbcr_x = VOP_REG(PX30_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), + .scale_cbcr_y = VOP_REG(PX30_WIN0_SCL_FACTOR_CBR, 0xffff, 16), +}; + +static const struct vop_win_phy px30_win0_data = { + .scl = &px30_win_scl, + .data_formats = formats_win_full, + .nformats = ARRAY_SIZE(formats_win_full), + .enable = VOP_REG(PX30_WIN0_CTRL0, 0x1, 0), + .format = VOP_REG(PX30_WIN0_CTRL0, 0x7, 1), + .rb_swap = VOP_REG(PX30_WIN0_CTRL0, 0x1, 12), + .act_info = VOP_REG(PX30_WIN0_ACT_INFO, 0xffffffff, 0), + .dsp_info = VOP_REG(PX30_WIN0_DSP_INFO, 0xffffffff, 0), + .dsp_st = VOP_REG(PX30_WIN0_DSP_ST, 0xffffffff, 0), + .yrgb_mst = VOP_REG(PX30_WIN0_YRGB_MST0, 0xffffffff, 0), + .uv_mst = VOP_REG(PX30_WIN0_CBR_MST0, 0xffffffff, 0), + .yrgb_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 0), + .uv_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 16), +}; + +static const struct vop_win_phy px30_win1_data = { + .data_formats = formats_win_lite, + .nformats = ARRAY_SIZE(formats_win_lite), + .enable = VOP_REG(PX30_WIN1_CTRL0, 0x1, 0), + .format = VOP_REG(PX30_WIN1_CTRL0, 0x7, 4), + .rb_swap = VOP_REG(PX30_WIN1_CTRL0, 0x1, 12), + .dsp_info = VOP_REG(PX30_WIN1_DSP_INFO, 0xffffffff, 0), + .dsp_st = VOP_REG(PX30_WIN1_DSP_ST, 0xffffffff, 0), + .yrgb_mst = VOP_REG(PX30_WIN1_MST, 0xffffffff, 0), + .yrgb_vir = VOP_REG(PX30_WIN1_VIR, 0x1fff, 0), +}; + +static const struct vop_win_phy px30_win2_data = { + .data_formats = formats_win_lite, + .nformats = ARRAY_SIZE(formats_win_lite), + .gate = VOP_REG(PX30_WIN2_CTRL0, 0x1, 0), + .enable = VOP_REG(PX30_WIN2_CTRL0, 0x1, 4), + .format = VOP_REG(PX30_WIN2_CTRL0, 0x3, 5), + .rb_swap = VOP_REG(PX30_WIN2_CTRL0, 0x1, 20), + .dsp_info = VOP_REG(PX30_WIN2_DSP_INFO0, 0x0fff0fff, 0), + .dsp_st = VOP_REG(PX30_WIN2_DSP_ST0, 0x1fff1fff, 0), + .yrgb_mst = VOP_REG(PX30_WIN2_MST0, 0xffffffff, 0), + .yrgb_vir = VOP_REG(PX30_WIN2_VIR0_1, 0x1fff, 0), +}; + +static const struct vop_win_data px30_vop_lit_win_data[] = { + { .base = 0x00, .phy = &px30_win1_data, + .type = DRM_PLANE_TYPE_PRIMARY }, +}; + +static const struct vop_win_data px30_vop_big_win_data[] = { + { .base = 0x00, .phy = &px30_win0_data, + .type = DRM_PLANE_TYPE_PRIMARY }, + { .base = 0x00, .phy = &px30_win1_data, + .type = DRM_PLANE_TYPE_OVERLAY }, + { .base = 0x00, .phy = &px30_win2_data, + .type = DRM_PLANE_TYPE_CURSOR }, +}; + +static const struct vop_data px30_vop_lit = { + .intr = &px30_intr, + .common = &px30_common, + .modeset = &px30_modeset, + .output = &px30_output, + .win = px30_vop_lit_win_data, + .win_size = ARRAY_SIZE(px30_vop_lit_win_data), +}; + +static const struct vop_data px30_vop_big = { + .intr = &px30_intr, + .common = &px30_common, + .modeset = &px30_modeset, + .output = &px30_output, + .win = px30_vop_big_win_data, + .win_size = ARRAY_SIZE(px30_vop_big_win_data), +}; + static const struct vop_scl_extension rk3288_win_full_scl_ext = { .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), @@ -541,6 +663,10 @@ static const struct of_device_id vop_driver_dt_match[] = { .data = &rk3036_vop }, { .compatible = "rockchip,rk3126-vop", .data = &rk3126_vop }, + { .compatible = "rockchip,px30-vop-lit", + .data = &rk3126_vop } + { .compatible = "rockchip,px30-vop-big", + .data = &rk3126_vop } { .compatible = "rockchip,rk3288-vop", .data = &rk3288_vop }, { .compatible = "rockchip,rk3368-vop", diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index f81b510..71527cb 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -884,4 +884,78 @@ #define RK3126_WIN1_DSP_ST 0x54 /* rk3126 register definition end */ +/* px30 register definition */ +#define PX30_REG_CFG_DONE 0x00000 +#define PX30_VERSION 0x00004 +#define PX30_DSP_BG 0x00008 +#define PX30_MCU_CTRL 0x0000c +#define PX30_SYS_CTRL0 0x00010 +#define PX30_SYS_CTRL1 0x00014 +#define PX30_SYS_CTRL2 0x00018 +#define PX30_DSP_CTRL0 0x00020 +#define PX30_DSP_CTRL2 0x00028 +#define PX30_VOP_STATUS 0x0002c +#define PX30_LINE_FLAG 0x00030 +#define PX30_INTR_EN 0x00034 +#define PX30_INTR_CLEAR 0x00038 +#define PX30_INTR_STATUS 0x0003c +#define PX30_WIN0_CTRL0 0x00050 +#define PX30_WIN0_CTRL1 0x00054 +#define PX30_WIN0_COLOR_KEY 0x00058 +#define PX30_WIN0_VIR 0x0005c +#define PX30_WIN0_YRGB_MST0 0x00060 +#define PX30_WIN0_CBR_MST0 0x00064 +#define PX30_WIN0_ACT_INFO 0x00068 +#define PX30_WIN0_DSP_INFO 0x0006c +#define PX30_WIN0_DSP_ST 0x00070 +#define PX30_WIN0_SCL_FACTOR_YRGB 0x00074 +#define PX30_WIN0_SCL_FACTOR_CBR 0x00078 +#define PX30_WIN0_SCL_OFFSET 0x0007c +#define PX30_WIN0_ALPHA_CTRL 0x00080 +#define PX30_WIN1_CTRL0 0x00090 +#define PX30_WIN1_CTRL1 0x00094 +#define PX30_WIN1_VIR 0x00098 +#define PX30_WIN1_MST 0x000a0 +#define PX30_WIN1_DSP_INFO 0x000a4 +#define PX30_WIN1_DSP_ST 0x000a8 +#define PX30_WIN1_COLOR_KEY 0x000ac +#define PX30_WIN1_ALPHA_CTRL 0x000bc +#define PX30_HWC_CTRL0 0x000e0 +#define PX30_HWC_CTRL1 0x000e4 +#define PX30_HWC_MST 0x000e8 +#define PX30_HWC_DSP_ST 0x000ec +#define PX30_HWC_ALPHA_CTRL 0x000f0 +#define PX30_DSP_HTOTAL_HS_END 0x00100 +#define PX30_DSP_HACT_ST_END 0x00104 +#define PX30_DSP_VTOTAL_VS_END 0x00108 +#define PX30_DSP_VACT_ST_END 0x0010c +#define PX30_DSP_VS_ST_END_F1 0x00110 +#define PX30_DSP_VACT_ST_END_F1 0x00114 +#define PX30_BCSH_CTRL 0x00160 +#define PX30_BCSH_COL_BAR 0x00164 +#define PX30_BCSH_BCS 0x00168 +#define PX30_BCSH_H 0x0016c +#define PX30_FRC_LOWER01_0 0x00170 +#define PX30_FRC_LOWER01_1 0x00174 +#define PX30_FRC_LOWER10_0 0x00178 +#define PX30_FRC_LOWER10_1 0x0017c +#define PX30_FRC_LOWER11_0 0x00180 +#define PX30_FRC_LOWER11_1 0x00184 +#define PX30_MCU_RW_BYPASS_PORT 0x0018c +#define PX30_WIN2_CTRL0 0x00190 +#define PX30_WIN2_CTRL1 0x00194 +#define PX30_WIN2_VIR0_1 0x00198 +#define PX30_WIN2_VIR2_3 0x0019c +#define PX30_WIN2_MST0 0x001a0 +#define PX30_WIN2_DSP_INFO0 0x001a4 +#define PX30_WIN2_DSP_ST0 0x001a8 +#define PX30_WIN2_COLOR_KEY 0x001ac +#define PX30_WIN2_ALPHA_CTRL 0x001bc +#define PX30_BLANKING_VALUE 0x001f4 +#define PX30_FLAG_REG_FRM_VALID 0x001f8 +#define PX30_FLAG_REG 0x001fc +#define PX30_HWC_LUT_ADDR 0x00600 +#define PX30_GAMMA_LUT_ADDR 0x00a00 +/* px30 register definition end */ + #endif /* _ROCKCHIP_VOP_REG_H */ -- 2.7.4