From mboxrd@z Thu Jan  1 00:00:00 1970
From: Madhav Chauhan <madhav.chauhan@intel.com>
Subject: [PATCH v4 13/20] drm/i915/icl: Define data/clock lanes
 dphy timing registers
Date: Thu,  5 Jul 2018 19:19:44 +0530
Message-ID: <1530798591-2077-14-git-send-email-madhav.chauhan@intel.com>
References: <1530798591-2077-1-git-send-email-madhav.chauhan@intel.com>
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