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From: Paulo Zanoni <paulo.r.zanoni@intel.com>
To: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 20/24] drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP
Date: Wed, 11 Jul 2018 14:28:25 -0700	[thread overview]
Message-ID: <1531344505.3878.1.camel@intel.com> (raw)
In-Reply-To: <83F5C7385F545743AD4FB2A62F75B07333A827D1@ORSMSX108.amr.corp.intel.com>

Em Qui, 2018-06-21 às 15:04 -0700, Srivatsa, Anusha escreveu:
> > -----Original Message-----
> > From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On
> > Behalf Of
> > Paulo Zanoni
> > Sent: Monday, May 21, 2018 5:26 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Zanoni, Paulo R <paulo.r.zanoni@intel.com>
> > Subject: [Intel-gfx] [PATCH 20/24] drm/i915/icl: implement the
> > tc/legacy HPD
> > {dis, }connect flow for DP
> > 
> > Implement the DFLEXDPPMS/DFLEXDPCSSS dance for DisplayPort. These
> > functions need to be called during HPD assert/deassert, but due to
> > how our driver
> > works it's much simpler if we always call them when
> > icl_digital_port_connected() is called, which means we won't call
> > them exactly
> > once per HPD event. This should also cover the connected boot case,
> > whatever
> > the BIOS does.
> > 
> > We're still missing the HDMI case, which should be implemented in
> > the next
> > patch.
> > 
> > Also notice that, today, the BSpec pages for the DFLEXDPPMS and
> > DFLEXDPCSSS
> > registers are wrong, so you should only trust the flows described
> > by the "Gen11
> > TypeC Programming" page in our spec.
> > 
> > Cc: Animesh Manna <animesh.manna@intel.com>
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h |  6
> > +++++  drivers/gpu/drm/i915/intel_dp.c |
> > 57 ++++++++++++++++++++++++++++++++++++++++-
> > 2 files changed, 62 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 24308d4435f5..42cbace4c61e 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -10027,4 +10027,10 @@ enum skl_power_gate {
> > 						 _ICL_PHY_MISC_B)
> > #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN	(1 << 23)
> > 
> > +#define PORT_TX_DFLEXDPPMS
> > 	_MMIO(0x163890)
> > +#define   DP_PHY_MODE_STATUS_COMPLETED(tc_port)		(1
> > <<
> > (tc_port))
> > +
> > +#define PORT_TX_DFLEXDPCSSS
> > 	_MMIO(0x163894)
> > +#define   DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)		(1
> > << (tc_port))
> > +
> > #endif /* _I915_REG_H_ */
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index f3d5b9eed625..f25f871e7c22 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -4762,6 +4762,56 @@ static void icl_update_tc_port_type(struct
> > drm_i915_private *dev_priv,
> > 			      type_str);
> > }
> > 
> > +static bool icl_tc_phy_mode_status_connect(struct drm_i915_private
> > *dev_priv,
> > +					   struct
> > intel_digital_port *dig_port) {
> > +	enum tc_port tc_port = intel_port_to_tc(dev_priv,
> > dig_port->base.port);
> > +	u32 val;
> > +
> > +	if (dig_port->tc_type != TC_PORT_LEGACY &&
> > +	    dig_port->tc_type != TC_PORT_TYPEC)
> > +		return true;
> 
> 		Shouldn’t this return false?

Types that don't need to run this sequence can be considered connected,
so we return true.


> 
> > +	val = I915_READ(PORT_TX_DFLEXDPPMS);
> > +	if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
> > +		DRM_ERROR("DP PHY for TC port %d not ready\n",
> > tc_port);
> > +		return false;
> > +	}
> > +
> > +	/*
> > +	 * This function may be called many times in a row without
> > an HPD event
> > +	 * in between, so try to avoid the write when we can.
> > +	 */
> > +	val = I915_READ(PORT_TX_DFLEXDPCSSS);
> > +	if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
> > +		val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
> > +		I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
> > +	}
> > +
> > +	return true;
> > +}
> > +
> > +static void icl_tc_phy_mode_status_disconnect(struct
> > drm_i915_private
> > *dev_priv,
> > +					      struct
> > intel_digital_port *dig_port) {
> > +	enum tc_port tc_port = intel_port_to_tc(dev_priv,
> > dig_port->base.port);
> > +	u32 val;
> > +
> > +	if (dig_port->tc_type != TC_PORT_LEGACY &&
> > +	    dig_port->tc_type != TC_PORT_TYPEC)
> > +		return;
> > +
> > +	/*
> > +	 * This function may be called many times in a row without
> > an HPD event
> > +	 * in between, so try to avoid the write when we can.
> > +	 */
> 
> So, in the sequences to enable, it does tell that enabling suitable
> aux power domains is optional. But in the disable sequence, disable
> AUX_PWR is mentioned as a non-optional step. 
> In which case it has to be before we set DFLEXDPCSSS register to 0.
> 
>  Is it being addressed in another patch?

It should be disabled here because we're not using the port anymore at
this point.

> 
> The rest of the patch looks good.
> 
> Anusha 
> 
> > +	val = I915_READ(PORT_TX_DFLEXDPCSSS);
> > +	if (val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)) {
> > +		val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
> > +		I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
> > +	}
> > +}
> > +
> > static bool icl_tc_port_connected(struct drm_i915_private
> > *dev_priv,
> > 				  struct intel_digital_port
> > *intel_dig_port)  { @@
> > -4782,12 +4832,17 @@ static bool icl_tc_port_connected(struct
> > drm_i915_private *dev_priv,
> > 	if (cpu_isr & tbt_bit)
> > 		is_tbt = true;
> > 
> > -	if (!is_legacy && !is_typec && !is_tbt)
> > +	if (!is_legacy && !is_typec && !is_tbt) {
> > +		icl_tc_phy_mode_status_disconnect(dev_priv,
> > intel_dig_port);
> > 		return false;
> > +	}
> > 
> > 	icl_update_tc_port_type(dev_priv, intel_dig_port, is_legacy,
> > is_typec,
> > 				is_tbt);
> > 
> > +	if (!icl_tc_phy_mode_status_connect(dev_priv,
> > intel_dig_port))
> > +		return false;
> > +
> > 	return true;
> > }
> > 
> > --
> > 2.14.3
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2018-07-11 21:28 UTC|newest]

Thread overview: 127+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-22  0:25 [PATCH 00/24] More ICL display patches Paulo Zanoni
2018-05-22  0:25 ` [PATCH 01/24] drm/i915/icl: Extend AUX F interrupts to ICL Paulo Zanoni
2018-05-23 19:02   ` Srivatsa, Anusha
2018-05-22  0:25 ` [PATCH 02/24] drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC Paulo Zanoni
2018-05-24  9:22   ` Mika Kuoppala
2018-05-24 22:51     ` Dhinakaran Pandiyan
2018-05-25 12:00       ` Mika Kuoppala
2018-05-25 19:43         ` [PATCH v2] " Dhinakaran Pandiyan
2018-05-25 19:56           ` Chris Wilson
2018-06-14  1:51             ` Dhinakaran Pandiyan
2018-06-14 10:32               ` Ville Syrjälä
2018-06-14 20:21                 ` Dhinakaran Pandiyan
2018-06-14 19:54             ` [PATCH v3] " Dhinakaran Pandiyan
2018-06-15 23:18               ` Paulo Zanoni
2018-05-22  0:25 ` [PATCH 03/24] drm/i915/icl: introduce tc_port Paulo Zanoni
2018-05-22  6:13   ` Kumar, Mahesh
2018-05-22  0:25 ` [PATCH 04/24] drm/i915/icl: Support for TC North Display interrupts Paulo Zanoni
2018-06-13 22:20   ` Lucas De Marchi
2018-06-15 23:47     ` Paulo Zanoni
2018-05-22  0:25 ` [PATCH 05/24] drm/i915/icp: Add Interrupt Support Paulo Zanoni
2018-05-24 23:53   ` Lucas De Marchi
2018-05-25  0:45     ` Dhinakaran Pandiyan
2018-05-25  0:43       ` Lucas De Marchi
2018-05-30  0:04         ` Lucas De Marchi
2018-06-13 22:23           ` Lucas De Marchi
2018-06-14  0:04             ` Paulo Zanoni
2018-06-14  2:21             ` Dhinakaran Pandiyan
2018-06-18 19:10               ` Anusha Srivatsa
2018-05-22  0:25 ` [PATCH 06/24] drm/i915/ICL: Add register definition for DFLEXDPMLE Paulo Zanoni
2018-05-25  0:26   ` Paulo Zanoni
2018-05-25 16:14     ` Lucas De Marchi
2018-05-25 16:58       ` Manasi Navare
2018-05-25 18:52   ` [PATCH v2 " Manasi Navare
2018-05-25 19:03   ` [PATCH v3 06/24] drm/i915/icl: " Manasi Navare
2018-05-22  0:25 ` [PATCH 07/24] drm/i915/icl: Add DDI HDMI level selection for ICL Paulo Zanoni
2018-05-25 16:26   ` Lucas De Marchi
2018-06-01 22:32     ` Paulo Zanoni
2018-06-11 23:51       ` Lucas De Marchi
2018-05-22  0:25 ` [PATCH 08/24] drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin Paulo Zanoni
2018-05-23 19:43   ` James Ausmus
2018-05-22  0:25 ` [PATCH 09/24] drm/i915/icl: Add Icelake PCH detection Paulo Zanoni
2018-05-25  0:29   ` Paulo Zanoni
2018-05-22  0:25 ` [PATCH 10/24] drm/i915/icl: add icelake_get_ddi_pll() Paulo Zanoni
2018-06-13 23:15   ` Lucas De Marchi
2018-06-13 23:51     ` Paulo Zanoni
2018-06-13 23:55       ` Lucas De Marchi
2018-05-22  0:25 ` [PATCH 11/24] drm/i915/icl: Get DDI clock for ICL based on PLLs Paulo Zanoni
2018-05-22 11:44   ` Mika Kahola
2018-05-23  5:48     ` Lucas De Marchi
2018-05-23 21:54     ` Paulo Zanoni
2018-05-23 21:15   ` Paulo Zanoni
2018-05-23 22:44   ` [PATCH v2 " Paulo Zanoni
2018-05-24 13:12     ` Mika Kahola
2018-05-22  0:25 ` [PATCH 12/24] drm/i915/icl: Calculate link clock using the new registers Paulo Zanoni
2018-05-25  0:33   ` Paulo Zanoni
2018-05-22  0:25 ` [PATCH 13/24] drm/i915/icl: unconditionally init DDI for every port Paulo Zanoni
2018-06-13 23:34   ` Lucas De Marchi
2018-06-13 23:47     ` Paulo Zanoni
2018-05-22  0:25 ` [PATCH 14/24] drm/i915/icl: start adding the TBT pll Paulo Zanoni
2018-06-14  0:37   ` Lucas De Marchi
2018-05-22  0:25 ` [PATCH 15/24] drm/i915/icl: compute the TBT PLL registers Paulo Zanoni
2018-06-08 20:19   ` Srivatsa, Anusha
2018-06-13 21:19     ` Paulo Zanoni
2018-06-18 19:57       ` Srivatsa, Anusha
2018-06-13 21:42   ` [PATCH v2 " Paulo Zanoni
2018-05-22  0:25 ` [PATCH 16/24] drm/i915/icl: Handle hotplug interrupts for DP over TBT Paulo Zanoni
2018-06-14  0:51   ` Lucas De Marchi
2018-05-22  0:25 ` [PATCH 17/24] drm/i915/icl: Add 10-bit support for hdmi Paulo Zanoni
2018-06-20 16:55   ` Ville Syrjälä
2018-05-22  0:25 ` [PATCH 18/24] drm/i915/icl: implement icl_digital_port_connected() Paulo Zanoni
2018-06-19 22:28   ` Lucas De Marchi
2018-06-20 21:01     ` Paulo Zanoni
2018-05-22  0:25 ` [PATCH 19/24] drm/i915/icl: store the port type for TC ports Paulo Zanoni
2018-06-14 19:59   ` Rodrigo Vivi
2018-06-21  0:37     ` Paulo Zanoni
2018-05-22  0:25 ` [PATCH 20/24] drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP Paulo Zanoni
2018-06-21 22:04   ` Srivatsa, Anusha
2018-07-11 21:28     ` Paulo Zanoni [this message]
2018-05-22  0:25 ` [PATCH 21/24] drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI Paulo Zanoni
2018-06-26 11:41   ` Mika Kahola
2018-05-22  0:25 ` [PATCH 22/24] drm/i915/icl: Update FIA supported lane count for hpd Paulo Zanoni
2018-06-21 22:45   ` Srivatsa, Anusha
2018-05-22  0:25 ` [PATCH 23/24] drm/i915/icl: program MG_DP_MODE Paulo Zanoni
2018-06-19 12:59   ` Maarten Lankhorst
2018-06-19 13:00     ` Maarten Lankhorst
2018-05-22  0:25 ` [PATCH 24/24] drm/i915/icl: toggle PHY clock gating around link training Paulo Zanoni
2018-06-19 13:22   ` Maarten Lankhorst
2018-05-22  0:38 ` ✗ Fi.CI.CHECKPATCH: warning for More ICL display patches Patchwork
2018-05-22  0:45 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-05-22  1:00 ` ✓ Fi.CI.BAT: success " Patchwork
2018-05-22  1:52 ` ✓ Fi.CI.IGT: " Patchwork
2018-05-23 22:59 ` ✗ Fi.CI.CHECKPATCH: warning for More ICL display patches (rev2) Patchwork
2018-05-23 23:06 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-05-23 23:19 ` ✓ Fi.CI.BAT: success " Patchwork
2018-05-24  0:54 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-05-24 23:42 ` [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping Paulo Zanoni
2018-05-24 23:42   ` [PATCH 26/24] drm/i915/icl: Add allowed DP rates for Icelake Paulo Zanoni
2018-05-25 18:32     ` James Ausmus
2018-06-01 23:43       ` Paulo Zanoni
2018-06-14 19:24         ` Rodrigo Vivi
2018-06-15  0:45           ` Manasi Navare
2018-06-15  5:20             ` Rodrigo Vivi
2018-06-14 19:23     ` Rodrigo Vivi
2018-06-19 20:39       ` Manasi Navare
2018-05-24 23:42   ` [PATCH 27/24] drm/i915/dp: Add support for HBR3 and TPS4 during link training Paulo Zanoni
2018-05-25 18:41     ` James Ausmus
2018-05-24 23:42   ` [PATCH 28/24] drm/i915/icl: implement DVFS for ICL Paulo Zanoni
2018-06-14 19:47     ` Rodrigo Vivi
2018-05-24 23:42   ` [PATCH 29/24] drm/i915/icl: DP_AUX_E is valid on ICL+ Paulo Zanoni
2018-05-25  0:12     ` Paulo Zanoni
2018-06-11 23:01       ` Paulo Zanoni
2018-05-24 23:42   ` [PATCH 30/24] drm/i915/icl: update VBT's child_device_config flags2 field Paulo Zanoni
2018-06-14 19:33     ` Rodrigo Vivi
2018-05-25  0:36   ` [PATCH 25/24] drm/i915/icl: fix gmbus gpio pin mapping Lucas De Marchi
2018-05-25 16:24     ` Ville Syrjälä
2018-05-25 16:26       ` Lucas De Marchi
2018-06-14 19:28     ` Rodrigo Vivi
2018-06-14 19:07   ` Rodrigo Vivi
2018-06-14 20:43     ` Paulo Zanoni
2018-05-24 23:59 ` ✗ Fi.CI.CHECKPATCH: warning for More ICL display patches (rev7) Patchwork
2018-05-25  0:06 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-05-25  0:14 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-05-25  0:49 ` ✗ Fi.CI.BAT: failure for More ICL display patches (rev8) Patchwork
2018-05-25 20:11 ` ✗ Fi.CI.BAT: failure for More ICL display patches (rev11) Patchwork
2018-06-01 23:22 ` [PATCH 00/24] More ICL display patches Paulo Zanoni
2018-06-13 21:49 ` ✗ Fi.CI.BAT: failure for More ICL display patches (rev12) Patchwork
2018-06-14 20:20 ` ✗ Fi.CI.BAT: failure for More ICL display patches (rev13) Patchwork

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