From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133]) by ash.osuosl.org (Postfix) with ESMTP id 2E9E71CF2A0 for ; Mon, 16 Jul 2018 15:53:32 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by hemlock.osuosl.org (Postfix) with ESMTP id 2C2CB88F42 for ; Mon, 16 Jul 2018 15:53:32 +0000 (UTC) Received: from hemlock.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 8eOBu4gospep for ; Mon, 16 Jul 2018 15:53:31 +0000 (UTC) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by hemlock.osuosl.org (Postfix) with ESMTPS id 30BC388E47 for ; Mon, 16 Jul 2018 15:53:31 +0000 (UTC) Received: by mail-wr1-f67.google.com with SMTP id a3-v6so23214077wrt.2 for ; Mon, 16 Jul 2018 08:53:31 -0700 (PDT) From: Sergio Paracuellos Subject: [PATCH v4 04/15] staging: mt7621-pci: use pcie_[read|write] in [write|read]_config Date: Mon, 16 Jul 2018 17:53:12 +0200 Message-Id: <1531756403-7197-5-git-send-email-sergio.paracuellos@gmail.com> In-Reply-To: <1531756403-7197-1-git-send-email-sergio.paracuellos@gmail.com> References: <1531756403-7197-1-git-send-email-sergio.paracuellos@gmail.com> List-Id: Linux Driver Project Developer List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: driverdev-devel-bounces@linuxdriverproject.org Sender: "devel" To: gregkh@linuxfoundation.org Cc: neil@brown.name, driverdev-devel@linuxdriverproject.org Instead of custom macros use pcie_read and pcie_write functions. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 67 ++++++++++++++++----------------- 1 file changed, 32 insertions(+), 35 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index ed15443..cb39479 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -229,41 +229,38 @@ struct pci_ops mt7621_pci_ops = { }; static void -read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val) +read_config(struct mt7621_pcie *pcie, + unsigned long bus, unsigned long dev, + unsigned long func, unsigned long reg, unsigned long *val) { - u32 address_reg, data_reg, address; - - address_reg = RALINK_PCI_CONFIG_ADDR; - data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG; - address = mt7621_pci_get_cfgaddr(bus, dev, func, reg); - MV_WRITE(address_reg, address); - MV_READ(data_reg, val); - return; + u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg); + + pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); + *val = pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG); } static void -write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val) +write_config(struct mt7621_pcie *pcie, + unsigned long bus, unsigned long dev, + unsigned long func, unsigned long reg, unsigned long val) { - u32 address_reg, data_reg, address; - - address_reg = RALINK_PCI_CONFIG_ADDR; - data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG; - address = mt7621_pci_get_cfgaddr(bus, dev, func, reg); - MV_WRITE(address_reg, address); - MV_WRITE(data_reg, val); - return; + u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg); + + pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); + pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG); } int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { + struct mt7621_pcie *pcie = dev->bus->sysdata; u16 cmd; u32 val; int irq; if (dev->bus->number == 0) { - write_config(0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE); - read_config(0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val); + write_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE); + read_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val); printk("BAR0 at slot %d = %x\n", slot, val); } @@ -472,13 +469,13 @@ static int mt7621_pci_probe(struct platform_device *pdev) bypass_pipe_rst(); set_phy_for_ssc(); - read_config(0, 0, 0, 0x70c, &val); + read_config(pcie, 0, 0, 0, 0x70c, &val); printk("Port 0 N_FTS = %x\n", (unsigned int)val); - read_config(0, 1, 0, 0x70c, &val); + read_config(pcie, 0, 1, 0, 0x70c, &val); printk("Port 1 N_FTS = %x\n", (unsigned int)val); - read_config(0, 2, 0, 0x70c, &val); + read_config(pcie, 0, 2, 0, 0x70c, &val); printk("Port 2 N_FTS = %x\n", (unsigned int)val); rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL); @@ -591,28 +588,28 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num switch (pcie_link_status) { case 7: - read_config(0, 2, 0, 0x4, &val); - write_config(0, 2, 0, 0x4, val|0x4); - read_config(0, 2, 0, 0x70c, &val); + read_config(pcie, 0, 2, 0, 0x4, &val); + write_config(pcie, 0, 2, 0, 0x4, val|0x4); + read_config(pcie, 0, 2, 0, 0x70c, &val); val &= ~(0xff)<<8; val |= 0x50<<8; - write_config(0, 2, 0, 0x70c, val); + write_config(pcie, 0, 2, 0, 0x70c, val); case 3: case 5: case 6: - read_config(0, 1, 0, 0x4, &val); - write_config(0, 1, 0, 0x4, val|0x4); - read_config(0, 1, 0, 0x70c, &val); + read_config(pcie, 0, 1, 0, 0x4, &val); + write_config(pcie, 0, 1, 0, 0x4, val|0x4); + read_config(pcie, 0, 1, 0, 0x70c, &val); val &= ~(0xff)<<8; val |= 0x50<<8; - write_config(0, 1, 0, 0x70c, val); + write_config(pcie, 0, 1, 0, 0x70c, val); default: - read_config(0, 0, 0, 0x4, &val); - write_config(0, 0, 0, 0x4, val|0x4); //bus master enable - read_config(0, 0, 0, 0x70c, &val); + read_config(pcie, 0, 0, 0, 0x4, &val); + write_config(pcie, 0, 0, 0, 0x4, val|0x4); //bus master enable + read_config(pcie, 0, 0, 0, 0x70c, &val); val &= ~(0xff)<<8; val |= 0x50<<8; - write_config(0, 0, 0, 0x70c, val); + write_config(pcie, 0, 0, 0, 0x70c, val); } bridge->busnr = 0; -- 2.7.4 _______________________________________________ devel mailing list devel@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel