From mboxrd@z Thu Jan 1 00:00:00 1970 From: tien.fong.chee at intel.com Date: Thu, 26 Jul 2018 15:54:15 +0800 Subject: [U-Boot] [PATCH 2/3] enable fpga loadfs In-Reply-To: <1532591656-20142-1-git-send-email-tien.fong.chee@intel.com> References: <1532591656-20142-1-git-send-email-tien.fong.chee@intel.com> Message-ID: <1532591656-20142-3-git-send-email-tien.fong.chee@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Tien Fong Chee Signed-off-by: Tien Fong Chee --- arch/arm/dts/socfpga_arria10.dtsi | 12 ++++++++++++ arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 6 ++++++ configs/socfpga_arria10_defconfig | 12 ++++++++++++ 3 files changed, 30 insertions(+), 0 deletions(-) diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi index b51febd..45aef6a 100644 --- a/arch/arm/dts/socfpga_arria10.dtsi +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -48,6 +48,12 @@ <0xffffc100 0x100>; }; + fs_loader0: fs-loader at 0 { + u-boot,dm-pre-reloc; + compatible = "u-boot,fs-loader"; + phandlepart = <&mmc 1>; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -532,12 +538,18 @@ }; fpga_mgr: fpga-mgr at ffd03000 { + u-boot,dm-pre-reloc; compatible = "altr,socfpga-a10-fpga-mgr"; reg = <0xffd03000 0x100 0xffcfe400 0x20>; clocks = <&l4_mp_clk>; resets = <&rst FPGAMGR_RESET>; reset-names = "fpgamgr"; + altr,bitstream_periph = + "ghrd_10as066n2.periph.rbf.mkimage"; + altr,bitstream_core = + "ghrd_10as066n2.core.rbf.mkimage"; + altr,bitstream_devpart = "0:1"; }; i2c0: i2c at ffc02200 { diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts index 9c6070d..4b9705b 100644 --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts @@ -18,6 +18,12 @@ /dts-v1/; #include "socfpga_arria10_socdk.dtsi" +/ { + chosen { + firmware-loader = &fs_loader0; + }; +}; + &mmc { u-boot,dm-pre-reloc; status = "okay"; diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index f24ea77..675f4da 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_TEXT_BASE=0x01000040 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_PART=y CONFIG_IDENT_STRING="socfpga_arria10" CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc" CONFIG_DISTRO_DEFAULTS=y @@ -18,6 +20,8 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb" +# CONFIG_OF_LIVE=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 @@ -39,12 +43,20 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPL_DOS_PARTITION=y +CONFIG_CMD_FAT=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_MMC=y CONFIG_FPGA_SOCFPGA=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y +CONFIG_FS_LOADER=y +CONFIG_SPL_DM_MMC=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_FPGA=y +CONFIG_FPGA_ALTERA=y +CONFIG_CMD_FPGA_LOADFS=y CONFIG_SYS_I2C_DW=y CONFIG_DM_MMC=y CONFIG_MMC_DW=y -- 1.7.7.4