From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38779) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fkB2t-00057z-FP for qemu-devel@nongnu.org; Mon, 30 Jul 2018 12:29:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fkB2p-0003Pl-1z for qemu-devel@nongnu.org; Mon, 30 Jul 2018 12:29:19 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:48059 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fkB2o-0003P1-PL for qemu-devel@nongnu.org; Mon, 30 Jul 2018 12:29:14 -0400 From: Aleksandar Markovic Date: Mon, 30 Jul 2018 18:12:32 +0200 Message-Id: <1532967169-22265-60-git-send-email-aleksandar.markovic@rt-rk.com> In-Reply-To: <1532967169-22265-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1532967169-22265-1-git-send-email-aleksandar.markovic@rt-rk.com> Subject: [Qemu-devel] [PATCH v5 59/76] gdbstub: Disable handling of nanoMIPS ISA bit in the MIPS gdbstub List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, riku.voipio@iki.fi, philippe.mathieu.daude@gmail.com, aurelien@aurel32.net, richard.henderson@linaro.org, amarkovic@wavecomp.com, smarkovic@wavecomp.com, pjovanovic@wavecomp.com, pburton@wavecomp.com From: James Hogan nanoMIPS has no ISA bit in the PC, so remove the handling of the low bit of the PC in the MIPS gdbstub for nanoMIPS. This prevents the PC being read as e.g. 0xbfc00001, and prevents writing to the PC clearing MIPS_HFLAG_M16. Signed-off-by: James Hogan Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/gdbstub.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index 18e0e6d..559b69f 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -60,7 +60,8 @@ int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) return gdb_get_regl(mem_buf, (int32_t)env->CP0_Cause); case 37: return gdb_get_regl(mem_buf, env->active_tc.PC | - !!(env->hflags & MIPS_HFLAG_M16)); + (!(env->insn_flags & ISA_NANOMIPS32) && + env->hflags & MIPS_HFLAG_M16)); case 72: return gdb_get_regl(mem_buf, 0); /* fp */ case 89: @@ -131,10 +132,12 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) break; case 37: env->active_tc.PC = tmp & ~(target_ulong)1; - if (tmp & 1) { - env->hflags |= MIPS_HFLAG_M16; - } else { - env->hflags &= ~(MIPS_HFLAG_M16); + if (!(env->insn_flags & ISA_NANOMIPS32)) { + if (tmp & 1) { + env->hflags |= MIPS_HFLAG_M16; + } else { + env->hflags &= ~(MIPS_HFLAG_M16); + } } break; case 72: /* fp, ignored */ -- 2.7.4