From mboxrd@z Thu Jan 1 00:00:00 1970 From: Aapo Vienamo Subject: [PATCH 15/40] mmc: tegra: Power on the calibration pad Date: Wed, 1 Aug 2018 19:32:05 +0300 Message-ID: <1533141150-10511-16-git-send-email-avienamo@nvidia.com> References: <1533141150-10511-1-git-send-email-avienamo@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <1533141150-10511-1-git-send-email-avienamo@nvidia.com> Sender: linux-kernel-owner@vger.kernel.org To: Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , Ulf Hansson , Adrian Hunter , Mikko Perttunen , Stefan Agner Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Aapo Vienamo List-Id: linux-tegra@vger.kernel.org Automatic pad drive strength calibration is performed on a separate pad identical to the ones used for driving the actual bus. Power on the calibration pad during the calibration procedure and power it off afterwards to save power. Signed-off-by: Aapo Vienamo Reviewed-by: Mikko Perttunen --- drivers/mmc/host/sdhci-tegra.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 53c035b9..9e22fec 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -54,6 +54,7 @@ #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 +#define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) @@ -240,11 +241,32 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) tegra_host->ddr_signaling = false; } +static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) +{ + u32 reg; + + /* + * Enable or disable the additional I/O pad used by the drive strength + * calibration process. + */ + reg = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); + if (enable) { + reg |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; + sdhci_writel(host, reg, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); + udelay(1); + } else { + reg &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; + sdhci_writel(host, reg, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); + } +} + static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) { u32 reg; int ret; + tegra_sdhci_configure_cal_pad(host, true); + reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); @@ -254,6 +276,8 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 1, 10000); + tegra_sdhci_configure_cal_pad(host, false); + if (ret) dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); } -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07B20C28CF6 for ; Wed, 1 Aug 2018 16:33:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BB6D8208B0 for ; Wed, 1 Aug 2018 16:33:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BB6D8208B0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390498AbeHASUB (ORCPT ); Wed, 1 Aug 2018 14:20:01 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:2581 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390465AbeHASUA (ORCPT ); Wed, 1 Aug 2018 14:20:00 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Wed, 01 Aug 2018 09:33:22 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 01 Aug 2018 09:33:28 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 01 Aug 2018 09:33:28 -0700 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 1 Aug 2018 16:33:27 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Wed, 1 Aug 2018 16:33:27 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 01 Aug 2018 09:33:27 -0700 From: Aapo Vienamo To: Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , Ulf Hansson , Adrian Hunter , Mikko Perttunen , Stefan Agner CC: , , , , Aapo Vienamo Subject: [PATCH 15/40] mmc: tegra: Power on the calibration pad Date: Wed, 1 Aug 2018 19:32:05 +0300 Message-ID: <1533141150-10511-16-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533141150-10511-1-git-send-email-avienamo@nvidia.com> References: <1533141150-10511-1-git-send-email-avienamo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Automatic pad drive strength calibration is performed on a separate pad identical to the ones used for driving the actual bus. Power on the calibration pad during the calibration procedure and power it off afterwards to save power. Signed-off-by: Aapo Vienamo Reviewed-by: Mikko Perttunen --- drivers/mmc/host/sdhci-tegra.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 53c035b9..9e22fec 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -54,6 +54,7 @@ #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7 +#define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31) #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) @@ -240,11 +241,32 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) tegra_host->ddr_signaling = false; } +static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable) +{ + u32 reg; + + /* + * Enable or disable the additional I/O pad used by the drive strength + * calibration process. + */ + reg = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); + if (enable) { + reg |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; + sdhci_writel(host, reg, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); + udelay(1); + } else { + reg &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD; + sdhci_writel(host, reg, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); + } +} + static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) { u32 reg; int ret; + tegra_sdhci_configure_cal_pad(host, true); + reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START; sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); @@ -254,6 +276,8 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE), 1, 10000); + tegra_sdhci_configure_cal_pad(host, false); + if (ret) dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); } -- 2.7.4