From: Huang Rui <ray.huang-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Huang Rui <ray.huang-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 5/6] drm/amdgpu: move psp macro into amdgpu_ucode into amdgpu_psp header
Date: Thu, 2 Aug 2018 19:08:14 +0800 [thread overview]
Message-ID: <1533208095-15055-5-git-send-email-ray.huang@amd.com> (raw)
In-Reply-To: <1533208095-15055-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
Demangle amdgpu.h.
Signed-off-by: Huang Rui <ray.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 29 +++++++++++++++++------------
2 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index afb7761..bf7633a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1356,7 +1356,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
-#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
/* Common functions */
int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 1292096..967712f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -63,13 +63,16 @@ struct psp_funcs
int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode,
struct psp_gfx_cmd_resp *cmd);
int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
- int (*ring_create)(struct psp_context *psp, enum psp_ring_type ring_type);
+ int (*ring_create)(struct psp_context *psp,
+ enum psp_ring_type ring_type);
int (*ring_stop)(struct psp_context *psp,
enum psp_ring_type ring_type);
int (*ring_destroy)(struct psp_context *psp,
enum psp_ring_type ring_type);
- int (*cmd_submit)(struct psp_context *psp, struct amdgpu_firmware_info *ucode,
- uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, int index);
+ int (*cmd_submit)(struct psp_context *psp,
+ struct amdgpu_firmware_info *ucode,
+ uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+ int index);
bool (*compare_sram_data)(struct psp_context *psp,
struct amdgpu_firmware_info *ucode,
enum AMDGPU_UCODE_ID ucode_type);
@@ -83,11 +86,11 @@ struct psp_context
struct psp_ring km_ring;
struct psp_gfx_cmd_resp *cmd;
- const struct psp_funcs *funcs;
+ const struct psp_funcs *funcs;
/* fence buffer */
- struct amdgpu_bo *fw_pri_bo;
- uint64_t fw_pri_mc_addr;
+ struct amdgpu_bo *fw_pri_bo;
+ uint64_t fw_pri_mc_addr;
void *fw_pri_buf;
/* sos firmware */
@@ -100,8 +103,8 @@ struct psp_context
uint8_t *sos_start_addr;
/* tmr buffer */
- struct amdgpu_bo *tmr_bo;
- uint64_t tmr_mc_addr;
+ struct amdgpu_bo *tmr_bo;
+ uint64_t tmr_mc_addr;
void *tmr_buf;
/* asd firmware and buffer */
@@ -110,13 +113,13 @@ struct psp_context
uint32_t asd_feature_version;
uint32_t asd_ucode_size;
uint8_t *asd_start_addr;
- struct amdgpu_bo *asd_shared_bo;
- uint64_t asd_shared_mc_addr;
+ struct amdgpu_bo *asd_shared_bo;
+ uint64_t asd_shared_mc_addr;
void *asd_shared_buf;
/* fence buffer */
- struct amdgpu_bo *fence_buf_bo;
- uint64_t fence_buf_mc_addr;
+ struct amdgpu_bo *fence_buf_bo;
+ uint64_t fence_buf_mc_addr;
void *fence_buf;
/* cmd buffer */
@@ -150,6 +153,8 @@ struct amdgpu_psp_funcs {
#define psp_mode1_reset(psp) \
((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
+#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
+
extern const struct amd_ip_funcs psp_ip_funcs;
extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
--
2.7.4
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next prev parent reply other threads:[~2018-08-02 11:08 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-02 11:08 [PATCH 1/6] drm/amdgpu: move gfx definitions into amdgpu_gfx header Huang Rui
[not found] ` <1533208095-15055-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
2018-08-02 11:08 ` [PATCH 2/6] drm/amdgpu: move ih definitions into amdgpu_ih header Huang Rui
2018-08-02 11:08 ` [PATCH 3/6] drm/amdgpu: move sdma definitions into amdgpu_sdma header Huang Rui
2018-08-02 11:08 ` [PATCH 4/6] drm/amdgpu: move firmware definitions into amdgpu_ucode header Huang Rui
2018-08-02 11:08 ` Huang Rui [this message]
[not found] ` <1533208095-15055-5-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
2018-08-02 11:24 ` [PATCH 5/6] drm/amdgpu: move psp macro into amdgpu_ucode into amdgpu_psp header Huang Rui
2018-08-02 11:08 ` [PATCH 6/6] drm/amdgpu: move gem definitions into amdgpu_gem header Huang Rui
2018-08-02 11:44 ` [PATCH 1/6] drm/amdgpu: move gfx definitions into amdgpu_gfx header Christian König
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