From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D388C43142 for ; Thu, 2 Aug 2018 11:38:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 36457214E0 for ; Thu, 2 Aug 2018 11:38:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 36457214E0 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732305AbeHBN27 (ORCPT ); Thu, 2 Aug 2018 09:28:59 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:15153 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1732168AbeHBN27 (ORCPT ); Thu, 2 Aug 2018 09:28:59 -0400 X-UUID: 54ae87890341443fa7db8fd32343c4a3-20180802 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 2005248011; Thu, 02 Aug 2018 19:38:07 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Thu, 2 Aug 2018 19:38:06 +0800 Received: from [172.21.84.99] (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Thu, 2 Aug 2018 19:38:06 +0800 Message-ID: <1533209886.11190.62.camel@mtksdccf07> Subject: Re: [PATCH v1 12/15] drm/mediatek: add layer number condition for RDMA to control plane From: Stu Hsieh To: CK Hu CC: Philipp Zabel , David Airlie , Matthias Brugger , , , , , Date: Thu, 2 Aug 2018 19:38:06 +0800 In-Reply-To: <1532487770.9280.17.camel@mtksdaap41> References: <1532420235-22268-1-git-send-email-stu.hsieh@mediatek.com> <1532420235-22268-13-git-send-email-stu.hsieh@mediatek.com> <1532487770.9280.17.camel@mtksdaap41> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, CK: On Wed, 2018-07-25 at 11:02 +0800, CK Hu wrote: > Hi, Stu: > > On Tue, 2018-07-24 at 16:17 +0800, Stu Hsieh wrote: > > This patch add layer number condition for RDMA to control plane > > > > When plane init in crtc create, > > it use the number of OVL layer to init plane. > > That's OVL can read 4 memory address. > > > > For mt2712 third ddp, it use RDMA to read memory. > > RDMA can read 1 memory address, so it just init one plane. > > > > For compatibility, this patch use two define OVL_LAYER_NR and > > RDMA_LAYER_NR to distingush two difference HW engine. > > > > Signed-off-by: Stu Hsieh > > --- > > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 +++++++++++++++++-------- > > drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 2 ++ > > 2 files changed, 19 insertions(+), 8 deletions(-) > > > > [...] > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h > > index 9d9410c67ae9..b44fefadf14a 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h > > @@ -18,7 +18,9 @@ > > #include "mtk_drm_ddp_comp.h" > > #include "mtk_drm_plane.h" > > > > +#define MAX_LAYER_NR 4 > > #define OVL_LAYER_NR 4 > > +#define RDMA_LAYER_NR 1 > > #define MTK_LUT_SIZE 512 > > #define MTK_MAX_BPC 10 > > #define MTK_MIN_BPC 3 > > If the layer number is not fixed in '4', I would like to get this value > from component because in some SoC, OVL may have 6 layer. So add an > interface to get the max layer number and OVL, RDMA driver would return > the number for this SoC. > > Regards, > CK > OK Regards, Stu > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stu Hsieh Subject: Re: [PATCH v1 12/15] drm/mediatek: add layer number condition for RDMA to control plane Date: Thu, 2 Aug 2018 19:38:06 +0800 Message-ID: <1533209886.11190.62.camel@mtksdccf07> References: <1532420235-22268-1-git-send-email-stu.hsieh@mediatek.com> <1532420235-22268-13-git-send-email-stu.hsieh@mediatek.com> <1532487770.9280.17.camel@mtksdaap41> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1532487770.9280.17.camel@mtksdaap41> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: CK Hu Cc: srv_heupstream@mediatek.com, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org List-Id: linux-mediatek@lists.infradead.org SGksIENLOgoKT24gV2VkLCAyMDE4LTA3LTI1IGF0IDExOjAyICswODAwLCBDSyBIdSB3cm90ZToK PiBIaSwgU3R1Ogo+IAo+IE9uIFR1ZSwgMjAxOC0wNy0yNCBhdCAxNjoxNyArMDgwMCwgU3R1IEhz aWVoIHdyb3RlOgo+ID4gVGhpcyBwYXRjaCBhZGQgbGF5ZXIgbnVtYmVyIGNvbmRpdGlvbiBmb3Ig UkRNQSB0byBjb250cm9sIHBsYW5lCj4gPiAKPiA+IFdoZW4gcGxhbmUgaW5pdCBpbiBjcnRjIGNy ZWF0ZSwKPiA+IGl0IHVzZSB0aGUgbnVtYmVyIG9mIE9WTCBsYXllciB0byBpbml0IHBsYW5lLgo+ ID4gVGhhdCdzIE9WTCBjYW4gcmVhZCA0IG1lbW9yeSBhZGRyZXNzLgo+ID4gCj4gPiBGb3IgbXQy NzEyIHRoaXJkIGRkcCwgaXQgdXNlIFJETUEgdG8gcmVhZCBtZW1vcnkuCj4gPiBSRE1BIGNhbiBy ZWFkIDEgbWVtb3J5IGFkZHJlc3MsIHNvIGl0IGp1c3QgaW5pdCBvbmUgcGxhbmUuCj4gPiAKPiA+ IEZvciBjb21wYXRpYmlsaXR5LCB0aGlzIHBhdGNoIHVzZSB0d28gZGVmaW5lIE9WTF9MQVlFUl9O UiBhbmQKPiA+IFJETUFfTEFZRVJfTlIgdG8gZGlzdGluZ3VzaCB0d28gZGlmZmVyZW5jZSBIVyBl bmdpbmUuCj4gPiAKPiA+IFNpZ25lZC1vZmYtYnk6IFN0dSBIc2llaCA8c3R1LmhzaWVoQG1lZGlh dGVrLmNvbT4KPiA+IC0tLQo+ID4gIGRyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9tdGtfZHJtX2Ny dGMuYyB8IDI1ICsrKysrKysrKysrKysrKysrLS0tLS0tLS0KPiA+ICBkcml2ZXJzL2dwdS9kcm0v bWVkaWF0ZWsvbXRrX2RybV9jcnRjLmggfCAgMiArKwo+ID4gIDIgZmlsZXMgY2hhbmdlZCwgMTkg aW5zZXJ0aW9ucygrKSwgOCBkZWxldGlvbnMoLSkKPiA+IAo+IAo+IFsuLi5dCj4gCj4gPiBkaWZm IC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fY3J0Yy5oIGIvZHJpdmVy cy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fY3J0Yy5oCj4gPiBpbmRleCA5ZDk0MTBjNjdhZTku LmI0NGZlZmFkZjE0YSAxMDA2NDQKPiA+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9t dGtfZHJtX2NydGMuaAo+ID4gKysrIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1f Y3J0Yy5oCj4gPiBAQCAtMTgsNyArMTgsOSBAQAo+ID4gICNpbmNsdWRlICJtdGtfZHJtX2RkcF9j b21wLmgiCj4gPiAgI2luY2x1ZGUgIm10a19kcm1fcGxhbmUuaCIKPiA+ICAKPiA+ICsjZGVmaW5l IE1BWF9MQVlFUl9OUgk0Cj4gPiAgI2RlZmluZSBPVkxfTEFZRVJfTlIJNAo+ID4gKyNkZWZpbmUg UkRNQV9MQVlFUl9OUgkxCj4gPiAgI2RlZmluZSBNVEtfTFVUX1NJWkUJNTEyCj4gPiAgI2RlZmlu ZSBNVEtfTUFYX0JQQwkxMAo+ID4gICNkZWZpbmUgTVRLX01JTl9CUEMJMwo+IAo+IElmIHRoZSBs YXllciBudW1iZXIgaXMgbm90IGZpeGVkIGluICc0JywgSSB3b3VsZCBsaWtlIHRvIGdldCB0aGlz IHZhbHVlCj4gZnJvbSBjb21wb25lbnQgYmVjYXVzZSBpbiBzb21lIFNvQywgT1ZMIG1heSBoYXZl IDYgbGF5ZXIuIFNvIGFkZCBhbgo+IGludGVyZmFjZSB0byBnZXQgdGhlIG1heCBsYXllciBudW1i ZXIgYW5kIE9WTCwgUkRNQSBkcml2ZXIgd291bGQgcmV0dXJuCj4gdGhlIG51bWJlciBmb3IgdGhp cyBTb0MuCj4gCj4gUmVnYXJkcywKPiBDSwo+IApPSwoKUmVnYXJkcywKU3R1Cgo+IAoKCl9fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWls aW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZy ZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: stu.hsieh@mediatek.com (Stu Hsieh) Date: Thu, 2 Aug 2018 19:38:06 +0800 Subject: [PATCH v1 12/15] drm/mediatek: add layer number condition for RDMA to control plane In-Reply-To: <1532487770.9280.17.camel@mtksdaap41> References: <1532420235-22268-1-git-send-email-stu.hsieh@mediatek.com> <1532420235-22268-13-git-send-email-stu.hsieh@mediatek.com> <1532487770.9280.17.camel@mtksdaap41> Message-ID: <1533209886.11190.62.camel@mtksdccf07> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, CK: On Wed, 2018-07-25 at 11:02 +0800, CK Hu wrote: > Hi, Stu: > > On Tue, 2018-07-24 at 16:17 +0800, Stu Hsieh wrote: > > This patch add layer number condition for RDMA to control plane > > > > When plane init in crtc create, > > it use the number of OVL layer to init plane. > > That's OVL can read 4 memory address. > > > > For mt2712 third ddp, it use RDMA to read memory. > > RDMA can read 1 memory address, so it just init one plane. > > > > For compatibility, this patch use two define OVL_LAYER_NR and > > RDMA_LAYER_NR to distingush two difference HW engine. > > > > Signed-off-by: Stu Hsieh > > --- > > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 25 +++++++++++++++++-------- > > drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 2 ++ > > 2 files changed, 19 insertions(+), 8 deletions(-) > > > > [...] > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h > > index 9d9410c67ae9..b44fefadf14a 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h > > @@ -18,7 +18,9 @@ > > #include "mtk_drm_ddp_comp.h" > > #include "mtk_drm_plane.h" > > > > +#define MAX_LAYER_NR 4 > > #define OVL_LAYER_NR 4 > > +#define RDMA_LAYER_NR 1 > > #define MTK_LUT_SIZE 512 > > #define MTK_MAX_BPC 10 > > #define MTK_MIN_BPC 3 > > If the layer number is not fixed in '4', I would like to get this value > from component because in some SoC, OVL may have 6 layer. So add an > interface to get the max layer number and OVL, RDMA driver would return > the number for this SoC. > > Regards, > CK > OK Regards, Stu >