From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92BC2C28CF6 for ; Fri, 3 Aug 2018 05:00:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1566B21707 for ; Fri, 3 Aug 2018 05:00:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1566B21707 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727436AbeHCGzO (ORCPT ); Fri, 3 Aug 2018 02:55:14 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:36653 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726627AbeHCGzO (ORCPT ); Fri, 3 Aug 2018 02:55:14 -0400 X-UUID: 50001a32507f4c979c5a5507cc6f5d09-20180803 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 725614619; Fri, 03 Aug 2018 13:00:40 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs03n2.mediatek.inc (172.21.101.182) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Fri, 3 Aug 2018 13:00:38 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Fri, 3 Aug 2018 13:00:38 +0800 Message-ID: <1533272438.31144.2.camel@mtksdaap41> Subject: Re: [PATCH v2 03/15] drm/mediatek: add connection from RDMA1 to DSI0 From: CK Hu To: Stu Hsieh CC: Philipp Zabel , David Airlie , Matthias Brugger , , , , , Date: Fri, 3 Aug 2018 13:00:38 +0800 In-Reply-To: <1533265868-28110-4-git-send-email-stu.hsieh@mediatek.com> References: <1533265868-28110-1-git-send-email-stu.hsieh@mediatek.com> <1533265868-28110-4-git-send-email-stu.hsieh@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Stu: On Fri, 2018-08-03 at 11:10 +0800, Stu Hsieh wrote: > This patch add connection from RDMA1 to DSI0 > > Signed-off-by: Stu Hsieh Reviewed-by: CK Hu > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 310d8482d5a0..31189fad8d4e 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -124,6 +124,7 @@ > #define DPI0_SEL_IN_RDMA2 0x3 > #define DPI1_SEL_IN_RDMA1 (0x1 << 8) > #define DPI1_SEL_IN_RDMA2 (0x3 << 8) > +#define DSI0_SEL_IN_RDMA1 0x1 > #define DSI1_SEL_IN_RDMA1 0x1 > #define DSI1_SEL_IN_RDMA2 0x4 > #define DSI2_SEL_IN_RDMA1 (0x1 << 16) > @@ -290,6 +291,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > *addr = DISP_REG_CONFIG_DPI_SEL_IN; > value = DPI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA1; > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > value = DSI1_SEL_IN_RDMA1; From mboxrd@z Thu Jan 1 00:00:00 1970 From: CK Hu Subject: Re: [PATCH v2 03/15] drm/mediatek: add connection from RDMA1 to DSI0 Date: Fri, 3 Aug 2018 13:00:38 +0800 Message-ID: <1533272438.31144.2.camel@mtksdaap41> References: <1533265868-28110-1-git-send-email-stu.hsieh@mediatek.com> <1533265868-28110-4-git-send-email-stu.hsieh@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1533265868-28110-4-git-send-email-stu.hsieh@mediatek.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Stu Hsieh Cc: srv_heupstream@mediatek.com, David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, Matthias Brugger , linux-arm-kernel@lists.infradead.org List-Id: linux-mediatek@lists.infradead.org SGksIFN0dToKCk9uIEZyaSwgMjAxOC0wOC0wMyBhdCAxMToxMCArMDgwMCwgU3R1IEhzaWVoIHdy b3RlOgo+IFRoaXMgcGF0Y2ggYWRkIGNvbm5lY3Rpb24gZnJvbSBSRE1BMSB0byBEU0kwCj4gCj4g U2lnbmVkLW9mZi1ieTogU3R1IEhzaWVoIDxzdHUuaHNpZWhAbWVkaWF0ZWsuY29tPgoKUmV2aWV3 ZWQtYnk6IENLIEh1IDxjay5odUBtZWRpYXRlay5jb20+Cgo+IC0tLQo+ICBkcml2ZXJzL2dwdS9k cm0vbWVkaWF0ZWsvbXRrX2RybV9kZHAuYyB8IDQgKysrKwo+ICAxIGZpbGUgY2hhbmdlZCwgNCBp bnNlcnRpb25zKCspCj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tZWRpYXRlay9t dGtfZHJtX2RkcC5jIGIvZHJpdmVycy9ncHUvZHJtL21lZGlhdGVrL210a19kcm1fZGRwLmMKPiBp bmRleCAzMTBkODQ4MmQ1YTAuLjMxMTg5ZmFkOGQ0ZSAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dw dS9kcm0vbWVkaWF0ZWsvbXRrX2RybV9kZHAuYwo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9tZWRp YXRlay9tdGtfZHJtX2RkcC5jCj4gQEAgLTEyNCw2ICsxMjQsNyBAQAo+ICAjZGVmaW5lIERQSTBf U0VMX0lOX1JETUEyCQkweDMKPiAgI2RlZmluZSBEUEkxX1NFTF9JTl9SRE1BMQkJKDB4MSA8PCA4 KQo+ICAjZGVmaW5lIERQSTFfU0VMX0lOX1JETUEyCQkoMHgzIDw8IDgpCj4gKyNkZWZpbmUgRFNJ MF9TRUxfSU5fUkRNQTEJCTB4MQo+ICAjZGVmaW5lIERTSTFfU0VMX0lOX1JETUExCQkweDEKPiAg I2RlZmluZSBEU0kxX1NFTF9JTl9SRE1BMgkJMHg0Cj4gICNkZWZpbmUgRFNJMl9TRUxfSU5fUkRN QTEJCSgweDEgPDwgMTYpCj4gQEAgLTI5MCw2ICsyOTEsOSBAQCBzdGF0aWMgdW5zaWduZWQgaW50 IG10a19kZHBfc2VsX2luKGVudW0gbXRrX2RkcF9jb21wX2lkIGN1ciwKPiAgCX0gZWxzZSBpZiAo Y3VyID09IEREUF9DT01QT05FTlRfUkRNQTEgJiYgbmV4dCA9PSBERFBfQ09NUE9ORU5UX0RQSTEp IHsKPiAgCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19EUElfU0VMX0lOOwo+ICAJCXZhbHVlID0g RFBJMV9TRUxfSU5fUkRNQTE7Cj4gKwl9IGVsc2UgaWYgKGN1ciA9PSBERFBfQ09NUE9ORU5UX1JE TUExICYmIG5leHQgPT0gRERQX0NPTVBPTkVOVF9EU0kwKSB7Cj4gKwkJKmFkZHIgPSBESVNQX1JF R19DT05GSUdfRFNJRV9TRUxfSU47Cj4gKwkJdmFsdWUgPSBEU0kwX1NFTF9JTl9SRE1BMTsKPiAg CX0gZWxzZSBpZiAoY3VyID09IEREUF9DT01QT05FTlRfUkRNQTEgJiYgbmV4dCA9PSBERFBfQ09N UE9ORU5UX0RTSTEpIHsKPiAgCQkqYWRkciA9IERJU1BfUkVHX0NPTkZJR19EU0lPX1NFTF9JTjsK PiAgCQl2YWx1ZSA9IERTSTFfU0VMX0lOX1JETUExOwoKCl9fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVs QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWls bWFuL2xpc3RpbmZvL2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: ck.hu@mediatek.com (CK Hu) Date: Fri, 3 Aug 2018 13:00:38 +0800 Subject: [PATCH v2 03/15] drm/mediatek: add connection from RDMA1 to DSI0 In-Reply-To: <1533265868-28110-4-git-send-email-stu.hsieh@mediatek.com> References: <1533265868-28110-1-git-send-email-stu.hsieh@mediatek.com> <1533265868-28110-4-git-send-email-stu.hsieh@mediatek.com> Message-ID: <1533272438.31144.2.camel@mtksdaap41> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, Stu: On Fri, 2018-08-03 at 11:10 +0800, Stu Hsieh wrote: > This patch add connection from RDMA1 to DSI0 > > Signed-off-by: Stu Hsieh Reviewed-by: CK Hu > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index 310d8482d5a0..31189fad8d4e 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -124,6 +124,7 @@ > #define DPI0_SEL_IN_RDMA2 0x3 > #define DPI1_SEL_IN_RDMA1 (0x1 << 8) > #define DPI1_SEL_IN_RDMA2 (0x3 << 8) > +#define DSI0_SEL_IN_RDMA1 0x1 > #define DSI1_SEL_IN_RDMA1 0x1 > #define DSI1_SEL_IN_RDMA2 0x4 > #define DSI2_SEL_IN_RDMA1 (0x1 << 16) > @@ -290,6 +291,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { > *addr = DISP_REG_CONFIG_DPI_SEL_IN; > value = DPI1_SEL_IN_RDMA1; > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; > + value = DSI0_SEL_IN_RDMA1; > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { > *addr = DISP_REG_CONFIG_DSIO_SEL_IN; > value = DSI1_SEL_IN_RDMA1;