From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55440) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fmj0H-0008Dw-3Y for qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:09:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fmj0E-0000lN-7G for qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:09:09 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46957 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fmj0D-0000kE-TY for qemu-devel@nongnu.org; Mon, 06 Aug 2018 13:09:06 -0400 From: Aleksandar Markovic Date: Mon, 6 Aug 2018 18:59:47 +0200 Message-Id: <1533574847-19294-21-git-send-email-aleksandar.markovic@rt-rk.com> In-Reply-To: <1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1533574847-19294-1-git-send-email-aleksandar.markovic@rt-rk.com> Subject: [Qemu-devel] [PATCH v7 20/80] target/mips: Add emulation of nanoMIPS 16-bit branch instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, laurent@vivier.eu, riku.voipio@iki.fi, philippe.mathieu.daude@gmail.com, aurelien@aurel32.net, richard.henderson@linaro.org, amarkovic@wavecomp.com, smarkovic@wavecomp.com, pjovanovic@wavecomp.com, pburton@wavecomp.com, arikalo@wavecomp.com, thuth@redhat.com, armbru@redhat.com From: Yongbok Kim Add emulation of nanoMIPS 16-bit branch instructions. Reviewed-by: Richard Henderson Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index 53c92f6..6a7c31e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16701,14 +16701,50 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) case NM_SWGP16: break; case NM_BC16: + gen_compute_branch(ctx, OPC_BEQ, 2, 0, 0, + (sextract32(ctx->opcode, 0, 1) << 10) | + (extract32(ctx->opcode, 1, 9) << 1), 0); break; case NM_BALC16: + gen_compute_branch(ctx, OPC_BGEZAL, 2, 0, 0, + (sextract32(ctx->opcode, 0, 1) << 10) | + (extract32(ctx->opcode, 1, 9) << 1), 0); break; case NM_BEQZC16: + gen_compute_branch(ctx, OPC_BEQ, 2, rt, 0, + (sextract32(ctx->opcode, 0, 1) << 7) | + (extract32(ctx->opcode, 1, 6) << 1), 0); break; case NM_BNEZC16: + gen_compute_branch(ctx, OPC_BNE, 2, rt, 0, + (sextract32(ctx->opcode, 0, 1) << 7) | + (extract32(ctx->opcode, 1, 6) << 1), 0); break; case NM_P16_BR: + switch (ctx->opcode & 0xf) { + case 0: + /* P16.JRC */ + switch (extract32(ctx->opcode, 4, 1)) { + case NM_JRC: + gen_compute_branch(ctx, OPC_JR, 2, + extract32(ctx->opcode, 5, 5), 0, 0, 0); + break; + case NM_JALRC16: + gen_compute_branch(ctx, OPC_JALR, 2, + extract32(ctx->opcode, 5, 5), 31, 0, 0); + break; + } + break; + default: + { + /* P16.BRI */ + uint32_t opc = extract32(ctx->opcode, 4, 3) < + extract32(ctx->opcode, 7, 3) ? OPC_BEQ : OPC_BNE; + gen_compute_branch(ctx, opc, 2, rs, rt, + extract32(ctx->opcode, 0, 4) << 1, 0); + } + break; + } break; case NM_P16_SR: break; -- 2.7.4