From mboxrd@z Thu Jan 1 00:00:00 1970 From: Aapo Vienamo Subject: [PATCH 0/8] Tegra SDHCI support HS400 on Tegra210 and Tegra186 Date: Tue, 7 Aug 2018 16:59:56 +0300 Message-ID: <1533650404-18125-1-git-send-email-avienamo@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: Sender: linux-kernel-owner@vger.kernel.org To: Ulf Hansson , Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , Adrian Hunter , Mikko Perttunen Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Aapo Vienamo List-Id: linux-tegra@vger.kernel.org Hi all, This series implements support for HS400 signaling on Tegra210 and Tegra186. This includes programming the DQS trimmer values, implementing enhanced strobe and HS400 delay line calibration. This series depends on the "Tegra SDHCI add support for HS200 and UHS signaling" series. Aapo Vienamo (8): dt-bindings: mmc: Add DQS trim value to Tegra SDHCI mmc: tegra: Parse and program DQS trim value mmc: tegra: Implement HS400 enhanced strobe mmc: tegra: Implement HS400 delay line calibration arm64: dts: tegra186: Add SDMMC4 DQS trim value arm64: dts: tegra210: Add SDMMC4 DQS trim value arm64: dts: tegra186: Enable HS400 arm64: dts: tegra210: Enable HS400 .../bindings/mmc/nvidia,tegra20-sdhci.txt | 3 + arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 + drivers/mmc/host/sdhci-tegra.c | 83 +++++++++++++++++++++- 4 files changed, 87 insertions(+), 3 deletions(-) -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D53CC46471 for ; Tue, 7 Aug 2018 14:00:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4655D20C0E for ; Tue, 7 Aug 2018 14:00:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4655D20C0E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389404AbeHGQOq (ORCPT ); Tue, 7 Aug 2018 12:14:46 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:8866 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389244AbeHGQOp (ORCPT ); Tue, 7 Aug 2018 12:14:45 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Tue, 07 Aug 2018 07:00:04 -0700 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 07 Aug 2018 07:00:13 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 07 Aug 2018 07:00:13 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 7 Aug 2018 14:00:17 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 7 Aug 2018 14:00:17 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Tue, 7 Aug 2018 14:00:17 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 07 Aug 2018 07:00:16 -0700 From: Aapo Vienamo To: Ulf Hansson , Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , "Adrian Hunter" , Mikko Perttunen CC: , , , , Aapo Vienamo Subject: [PATCH 0/8] Tegra SDHCI support HS400 on Tegra210 and Tegra186 Date: Tue, 7 Aug 2018 16:59:56 +0300 Message-ID: <1533650404-18125-1-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi all, This series implements support for HS400 signaling on Tegra210 and Tegra186. This includes programming the DQS trimmer values, implementing enhanced strobe and HS400 delay line calibration. This series depends on the "Tegra SDHCI add support for HS200 and UHS signaling" series. Aapo Vienamo (8): dt-bindings: mmc: Add DQS trim value to Tegra SDHCI mmc: tegra: Parse and program DQS trim value mmc: tegra: Implement HS400 enhanced strobe mmc: tegra: Implement HS400 delay line calibration arm64: dts: tegra186: Add SDMMC4 DQS trim value arm64: dts: tegra210: Add SDMMC4 DQS trim value arm64: dts: tegra186: Enable HS400 arm64: dts: tegra210: Enable HS400 .../bindings/mmc/nvidia,tegra20-sdhci.txt | 3 + arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 + drivers/mmc/host/sdhci-tegra.c | 83 +++++++++++++++++++++- 4 files changed, 87 insertions(+), 3 deletions(-) -- 2.7.4