From mboxrd@z Thu Jan 1 00:00:00 1970 From: Aapo Vienamo Subject: [PATCH 8/8] arm64: dts: tegra210: Enable HS400 Date: Tue, 7 Aug 2018 17:00:04 +0300 Message-ID: <1533650404-18125-9-git-send-email-avienamo@nvidia.com> References: <1533650404-18125-1-git-send-email-avienamo@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <1533650404-18125-1-git-send-email-avienamo@nvidia.com> Sender: linux-kernel-owner@vger.kernel.org To: Ulf Hansson , Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , Adrian Hunter , Mikko Perttunen Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Aapo Vienamo List-Id: linux-tegra@vger.kernel.org Enable HS400 signaling on Tegra210 SDMMC4 controller. Signed-off-by: Aapo Vienamo --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index f8e5f09..8fe47d6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1116,6 +1116,7 @@ <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; nvidia,dqs-trim = <40>; + mmc-hs400-1_8v; status = "disabled"; }; -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27C0CC46470 for ; Tue, 7 Aug 2018 14:00:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E10AF217B7 for ; Tue, 7 Aug 2018 14:00:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E10AF217B7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389565AbeHGQPJ (ORCPT ); Tue, 7 Aug 2018 12:15:09 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:12405 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389201AbeHGQPJ (ORCPT ); Tue, 7 Aug 2018 12:15:09 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Tue, 07 Aug 2018 07:00:38 -0700 Received: from HQMAIL105.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 07 Aug 2018 07:00:40 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 07 Aug 2018 07:00:40 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 7 Aug 2018 14:00:40 +0000 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 7 Aug 2018 14:00:40 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Tue, 7 Aug 2018 14:00:39 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 07 Aug 2018 07:00:39 -0700 From: Aapo Vienamo To: Ulf Hansson , Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , "Adrian Hunter" , Mikko Perttunen CC: , , , , Aapo Vienamo Subject: [PATCH 8/8] arm64: dts: tegra210: Enable HS400 Date: Tue, 7 Aug 2018 17:00:04 +0300 Message-ID: <1533650404-18125-9-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533650404-18125-1-git-send-email-avienamo@nvidia.com> References: <1533650404-18125-1-git-send-email-avienamo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable HS400 signaling on Tegra210 SDMMC4 controller. Signed-off-by: Aapo Vienamo --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index f8e5f09..8fe47d6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1116,6 +1116,7 @@ <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; nvidia,dqs-trim = <40>; + mmc-hs400-1_8v; status = "disabled"; }; -- 2.7.4