From mboxrd@z Thu Jan 1 00:00:00 1970 From: Drocula Subject: [PATCH v2] bus/pci: check if 5-level paging is enabled when testing IOMMU address width Date: Mon, 13 Aug 2018 12:57:48 +0000 Message-ID: <1534165068-23161-1-git-send-email-quzeyao@gmail.com> References: <1533494497-16253-1-git-send-email-quzeyao@gmail.com> Cc: dev@dpdk.org, anatoly.burakov@intel.com, stephen@networkplumber.org, Drocula Return-path: Received: from mail-pf1-f194.google.com (mail-pf1-f194.google.com [209.85.210.194]) by dpdk.org (Postfix) with ESMTP id 2CFCB37A2 for ; Mon, 13 Aug 2018 14:58:07 +0200 (CEST) Received: by mail-pf1-f194.google.com with SMTP id y10-v6so7614426pfn.8 for ; Mon, 13 Aug 2018 05:58:07 -0700 (PDT) In-Reply-To: <1533494497-16253-1-git-send-email-quzeyao@gmail.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The kernel version 4.14 released with the support of 5-level paging. When PML5 enabled, user-space virtual addresses uses up to 56 bits. see kernel's Documentation/x86/x86_64/mm.txt. Signed-off-by: ZY Qiu --- drivers/bus/pci/linux/pci.c | 33 ++++++++++++++++++++++++++++++--- 1 file changed, 30 insertions(+), 3 deletions(-) diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c index 04648ac..acc19df 100644 --- a/drivers/bus/pci/linux/pci.c +++ b/drivers/bus/pci/linux/pci.c @@ -4,6 +4,7 @@ #include #include +#include #include #include @@ -552,16 +553,39 @@ } #if defined(RTE_ARCH_X86) +/* + * Try to detect whether the system uses 5-level page table. + */ +static bool +system_uses_PML5(void) +{ +#define X86_56_BIT_VA (0xfULL << 52) + void *page_4k; + page_4k = mmap((void *)X86_56_BIT_VA, 4096, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + + if (page_4k == MAP_FAILED) + return false; + munmap(page_4k, 4096); + + if ((unsigned long long)page_4k & X86_56_BIT_VA) + return true; + return false; +} + static bool pci_one_device_iommu_support_va(struct rte_pci_device *dev) { #define VTD_CAP_MGAW_SHIFT 16 #define VTD_CAP_MGAW_MASK (0x3fULL << VTD_CAP_MGAW_SHIFT) -#define X86_VA_WIDTH 47 /* From Documentation/x86/x86_64/mm.txt */ +/* From Documentation/x86/x86_64/mm.txt */ +#define X86_VA_WIDTH_PML4 47 +#define X86_VA_WIDTH_PML5 56 + struct rte_pci_addr *addr = &dev->addr; char filename[PATH_MAX]; FILE *fp; - uint64_t mgaw, vtd_cap_reg = 0; + uint64_t mgaw, vtd_cap_reg = 0, va_width = X86_VA_WIDTH_PML4; snprintf(filename, sizeof(filename), "%s/" PCI_PRI_FMT "/iommu/intel-iommu/cap", @@ -587,8 +611,11 @@ fclose(fp); + if (system_uses_PML5()) + va_width = X86_VA_WIDTH_PML5; + mgaw = ((vtd_cap_reg & VTD_CAP_MGAW_MASK) >> VTD_CAP_MGAW_SHIFT) + 1; - if (mgaw < X86_VA_WIDTH) + if (mgaw < va_width) return false; return true; -- 1.8.3.1