From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59403) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpH37-0005Ot-FF for qemu-devel@nongnu.org; Mon, 13 Aug 2018 13:54:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpH33-00073a-HV for qemu-devel@nongnu.org; Mon, 13 Aug 2018 13:54:37 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:55749 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpH33-000726-8q for qemu-devel@nongnu.org; Mon, 13 Aug 2018 13:54:33 -0400 From: Aleksandar Markovic Date: Mon, 13 Aug 2018 19:52:38 +0200 Message-Id: <1534182832-554-14-git-send-email-aleksandar.markovic@rt-rk.com> In-Reply-To: <1534182832-554-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1534182832-554-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v8 13/87] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, laurent@vivier.eu, riku.voipio@iki.fi, philippe.mathieu.daude@gmail.com, aurelien@aurel32.net, richard.henderson@linaro.org, amarkovic@wavecomp.com, smarkovic@wavecomp.com, pjovanovic@wavecomp.com, pburton@wavecomp.com From: Yongbok Kim MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only, and placing ELPA flag checks before switch statement were technically correct. However, after adding handling more registers, these checks should be moved to act only in cases of handling EntryLo0 and EntryLo1. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Aleksandar Markovic Reviewed-by: Richard Henderson Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 219de72..6740764 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4938,12 +4938,11 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg= , int reg, int sel) { const char *rn =3D "invalid"; =20 - CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); - switch (reg) { case 2: switch (sel) { case 0: + CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0))= ; rn =3D "EntryLo0"; break; @@ -4954,6 +4953,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, = int reg, int sel) case 3: switch (sel) { case 0: + CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1))= ; rn =3D "EntryLo1"; break; @@ -5006,12 +5006,11 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg= , int reg, int sel) const char *rn =3D "invalid"; uint64_t mask =3D ctx->PAMask >> 36; =20 - CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); - switch (reg) { case 2: switch (sel) { case 0: + CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); tcg_gen_andi_tl(arg, arg, mask); gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0))= ; rn =3D "EntryLo0"; @@ -5023,6 +5022,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, = int reg, int sel) case 3: switch (sel) { case 0: + CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); tcg_gen_andi_tl(arg, arg, mask); gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1))= ; rn =3D "EntryLo1"; --=20 2.7.4