From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mo4-p01-ob.smtp.rzone.de ([85.215.255.50]:14788 "EHLO mo4-p01-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732667AbeHNQkv (ORCPT ); Tue, 14 Aug 2018 12:40:51 -0400 From: Ulrich Hecht To: laurent.pinchart@ideasonboard.com Cc: linux-renesas-soc@vger.kernel.org, dri-devel@lists.freedesktop.org, jacopo+renesas@jmondi.org, kieran.bingham+renesas@ideasonboard.com, Ulrich Hecht Subject: [PROTO][PATCH 02/10] drm: rcar-du: Add r8a77995 device support Date: Tue, 14 Aug 2018 15:49:56 +0200 Message-Id: <1534254604-24204-3-git-send-email-uli+renesas@fpond.eu> In-Reply-To: <1534254604-24204-1-git-send-email-uli+renesas@fpond.eu> References: <1534254604-24204-1-git-send-email-uli+renesas@fpond.eu> Sender: linux-renesas-soc-owner@vger.kernel.org List-ID: Add support for the R-Car D3 (R8A77995) SoC to the R-Car DU driver. Based on patch by Koji Matsuoka . Signed-off-by: Ulrich Hecht --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 17 ++++++----------- drivers/gpu/drm/rcar-du/rcar_du_drv.c | 26 ++++++++++++++++++++++++++ drivers/gpu/drm/rcar-du/rcar_du_drv.h | 1 + drivers/gpu/drm/rcar-du/rcar_du_group.c | 3 ++- 4 files changed, 35 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index cd6803a..9153e7a 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -53,14 +53,6 @@ static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr) rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr); } -static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set) -{ - struct rcar_du_device *rcdu = rcrtc->group->dev; - - rcar_du_write(rcdu, rcrtc->mmio_offset + reg, - rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set); -} - static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr, u32 set) { @@ -527,7 +519,8 @@ static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc) * actively driven). */ interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE; - rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK | DSYSR_SCM_MASK, + rcar_du_crtc_clr_set(rcrtc, DSYSR, + DSYSR_TVM_MASK | DSYSR_SCM_MASK | DSYSR_ILTS, (interlaced ? DSYSR_SCM_INT_VIDEO : 0) | DSYSR_TVM_MASTER); @@ -596,7 +589,9 @@ static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc) * Select switch sync mode. This stops display operation and configures * the HSYNC and VSYNC signals as inputs. */ - rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH); + rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK | DSYSR_ILTS, + rcar_du_needs(rcrtc->group->dev, RCAR_DU_QUIRK_TVM_MASTER_ONLY) ? + DSYSR_TVM_MASTER : DSYSR_TVM_SWITCH); rcar_du_group_start_stop(rcrtc->group, false); } @@ -744,7 +739,7 @@ static int rcar_du_crtc_enable_vblank(struct drm_crtc *crtc) struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc); rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL); - rcar_du_crtc_set(rcrtc, DIER, DIER_VBE); + rcar_du_crtc_clr_set(rcrtc, DIER, DIER_TVE | DIER_FRE, DIER_VBE); rcrtc->vblank_enable = true; return 0; diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c index 56f9472..5c2f764 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c @@ -294,6 +294,31 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = { .num_lvds = 1, }; +static const struct rcar_du_device_info rcar_du_r8a77995_info = { + .gen = 3, + .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK + | RCAR_DU_FEATURE_EXT_CTRL_REGS + | RCAR_DU_FEATURE_VSP1_SOURCE, + .quirks = RCAR_DU_QUIRK_TVM_MASTER_ONLY, + .channels_mask = BIT(1) | BIT(0), + .routes = { + /* R8A77995 has two LVDS output and one RGB output. */ + [RCAR_DU_OUTPUT_DPAD0] = { + .possible_crtcs = BIT(0) | BIT(1), + .port = 0, + }, + [RCAR_DU_OUTPUT_LVDS0] = { + .possible_crtcs = BIT(0), + .port = 1, + }, + [RCAR_DU_OUTPUT_LVDS1] = { + .possible_crtcs = BIT(1), + .port = 2, + }, + }, + .num_lvds = 2, +}; + static const struct of_device_id rcar_du_of_table[] = { { .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info }, { .compatible = "renesas,du-r8a7745", .data = &rzg1_du_r8a7745_info }, @@ -307,6 +332,7 @@ static const struct of_device_id rcar_du_of_table[] = { { .compatible = "renesas,du-r8a7796", .data = &rcar_du_r8a7796_info }, { .compatible = "renesas,du-r8a77965", .data = &rcar_du_r8a77965_info }, { .compatible = "renesas,du-r8a77970", .data = &rcar_du_r8a77970_info }, + { .compatible = "renesas,du-r8a77995", .data = &rcar_du_r8a77995_info }, { } }; diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h index b3a25e8..6257405 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h @@ -32,6 +32,7 @@ struct rcar_du_device; #define RCAR_DU_FEATURE_VSP1_SOURCE (1 << 2) /* Has inputs from VSP1 */ #define RCAR_DU_QUIRK_ALIGN_128B (1 << 0) /* Align pitches to 128 bytes */ +#define RCAR_DU_QUIRK_TVM_MASTER_ONLY (1 << 1) /* Does not have TV switch/sync modes */ /* * struct rcar_du_output_routing - Output routing specification diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c index d539cb2..9a0a694 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c @@ -178,7 +178,8 @@ void rcar_du_group_put(struct rcar_du_group *rgrp) static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start) { rcar_du_group_write(rgrp, DSYSR, - (rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES | DSYSR_DEN)) | + (rcar_du_group_read(rgrp, DSYSR) & + ~(DSYSR_DRES | DSYSR_DEN | DSYSR_ILTS)) | (start ? DSYSR_DEN : DSYSR_DRES)); } -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ulrich Hecht Subject: [PROTO][PATCH 02/10] drm: rcar-du: Add r8a77995 device support Date: Tue, 14 Aug 2018 15:49:56 +0200 Message-ID: <1534254604-24204-3-git-send-email-uli+renesas@fpond.eu> References: <1534254604-24204-1-git-send-email-uli+renesas@fpond.eu> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mo6-p01-ob.smtp.rzone.de (mo6-p01-ob.smtp.rzone.de [IPv6:2a01:238:20a:202:5301::3]) by gabe.freedesktop.org (Postfix) with ESMTPS id E12FA6E144 for ; Tue, 14 Aug 2018 13:50:38 +0000 (UTC) In-Reply-To: <1534254604-24204-1-git-send-email-uli+renesas@fpond.eu> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: laurent.pinchart@ideasonboard.com Cc: linux-renesas-soc@vger.kernel.org, kieran.bingham+renesas@ideasonboard.com, jacopo+renesas@jmondi.org, Ulrich Hecht , dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org QWRkIHN1cHBvcnQgZm9yIHRoZSBSLUNhciBEMyAoUjhBNzc5OTUpIFNvQyB0byB0aGUgUi1DYXIg RFUgZHJpdmVyLgoKQmFzZWQgb24gcGF0Y2ggYnkgS29qaSBNYXRzdW9rYSA8a29qaS5tYXRzdW9r YS54bUByZW5lc2FzLmNvbT4uCgpTaWduZWQtb2ZmLWJ5OiBVbHJpY2ggSGVjaHQgPHVsaStyZW5l c2FzQGZwb25kLmV1PgotLS0KIGRyaXZlcnMvZ3B1L2RybS9yY2FyLWR1L3JjYXJfZHVfY3J0Yy5j ICB8IDE3ICsrKysrKy0tLS0tLS0tLS0tCiBkcml2ZXJzL2dwdS9kcm0vcmNhci1kdS9yY2FyX2R1 X2Rydi5jICAgfCAyNiArKysrKysrKysrKysrKysrKysrKysrKysrKwogZHJpdmVycy9ncHUvZHJt L3JjYXItZHUvcmNhcl9kdV9kcnYuaCAgIHwgIDEgKwogZHJpdmVycy9ncHUvZHJtL3JjYXItZHUv cmNhcl9kdV9ncm91cC5jIHwgIDMgKystCiA0IGZpbGVzIGNoYW5nZWQsIDM1IGluc2VydGlvbnMo KyksIDEyIGRlbGV0aW9ucygtKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9yY2FyLWR1 L3JjYXJfZHVfY3J0Yy5jIGIvZHJpdmVycy9ncHUvZHJtL3JjYXItZHUvcmNhcl9kdV9jcnRjLmMK aW5kZXggY2Q2ODAzYS4uOTE1M2U3YSAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL3JjYXIt ZHUvcmNhcl9kdV9jcnRjLmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL3JjYXItZHUvcmNhcl9kdV9j cnRjLmMKQEAgLTUzLDE0ICs1Myw2IEBAIHN0YXRpYyB2b2lkIHJjYXJfZHVfY3J0Y19jbHIoc3Ry dWN0IHJjYXJfZHVfY3J0YyAqcmNydGMsIHUzMiByZWcsIHUzMiBjbHIpCiAJCSAgICAgIHJjYXJf ZHVfcmVhZChyY2R1LCByY3J0Yy0+bW1pb19vZmZzZXQgKyByZWcpICYgfmNscik7CiB9CiAKLXN0 YXRpYyB2b2lkIHJjYXJfZHVfY3J0Y19zZXQoc3RydWN0IHJjYXJfZHVfY3J0YyAqcmNydGMsIHUz MiByZWcsIHUzMiBzZXQpCi17Ci0Jc3RydWN0IHJjYXJfZHVfZGV2aWNlICpyY2R1ID0gcmNydGMt Pmdyb3VwLT5kZXY7Ci0KLQlyY2FyX2R1X3dyaXRlKHJjZHUsIHJjcnRjLT5tbWlvX29mZnNldCAr IHJlZywKLQkJICAgICAgcmNhcl9kdV9yZWFkKHJjZHUsIHJjcnRjLT5tbWlvX29mZnNldCArIHJl ZykgfCBzZXQpOwotfQotCiBzdGF0aWMgdm9pZCByY2FyX2R1X2NydGNfY2xyX3NldChzdHJ1Y3Qg cmNhcl9kdV9jcnRjICpyY3J0YywgdTMyIHJlZywKIAkJCQkgdTMyIGNsciwgdTMyIHNldCkKIHsK QEAgLTUyNyw3ICs1MTksOCBAQCBzdGF0aWMgdm9pZCByY2FyX2R1X2NydGNfc3RhcnQoc3RydWN0 IHJjYXJfZHVfY3J0YyAqcmNydGMpCiAJICogYWN0aXZlbHkgZHJpdmVuKS4KIAkgKi8KIAlpbnRl cmxhY2VkID0gcmNydGMtPmNydGMubW9kZS5mbGFncyAmIERSTV9NT0RFX0ZMQUdfSU5URVJMQUNF OwotCXJjYXJfZHVfY3J0Y19jbHJfc2V0KHJjcnRjLCBEU1lTUiwgRFNZU1JfVFZNX01BU0sgfCBE U1lTUl9TQ01fTUFTSywKKwlyY2FyX2R1X2NydGNfY2xyX3NldChyY3J0YywgRFNZU1IsCisJCQkg ICAgIERTWVNSX1RWTV9NQVNLIHwgRFNZU1JfU0NNX01BU0sgfCBEU1lTUl9JTFRTLAogCQkJICAg ICAoaW50ZXJsYWNlZCA/IERTWVNSX1NDTV9JTlRfVklERU8gOiAwKSB8CiAJCQkgICAgIERTWVNS X1RWTV9NQVNURVIpOwogCkBAIC01OTYsNyArNTg5LDkgQEAgc3RhdGljIHZvaWQgcmNhcl9kdV9j cnRjX3N0b3Aoc3RydWN0IHJjYXJfZHVfY3J0YyAqcmNydGMpCiAJICogU2VsZWN0IHN3aXRjaCBz eW5jIG1vZGUuIFRoaXMgc3RvcHMgZGlzcGxheSBvcGVyYXRpb24gYW5kIGNvbmZpZ3VyZXMKIAkg KiB0aGUgSFNZTkMgYW5kIFZTWU5DIHNpZ25hbHMgYXMgaW5wdXRzLgogCSAqLwotCXJjYXJfZHVf Y3J0Y19jbHJfc2V0KHJjcnRjLCBEU1lTUiwgRFNZU1JfVFZNX01BU0ssIERTWVNSX1RWTV9TV0lU Q0gpOworCXJjYXJfZHVfY3J0Y19jbHJfc2V0KHJjcnRjLCBEU1lTUiwgRFNZU1JfVFZNX01BU0sg fCBEU1lTUl9JTFRTLAorCQlyY2FyX2R1X25lZWRzKHJjcnRjLT5ncm91cC0+ZGV2LCBSQ0FSX0RV X1FVSVJLX1RWTV9NQVNURVJfT05MWSkgPworCQlEU1lTUl9UVk1fTUFTVEVSIDogRFNZU1JfVFZN X1NXSVRDSCk7CiAKIAlyY2FyX2R1X2dyb3VwX3N0YXJ0X3N0b3AocmNydGMtPmdyb3VwLCBmYWxz ZSk7CiB9CkBAIC03NDQsNyArNzM5LDcgQEAgc3RhdGljIGludCByY2FyX2R1X2NydGNfZW5hYmxl X3ZibGFuayhzdHJ1Y3QgZHJtX2NydGMgKmNydGMpCiAJc3RydWN0IHJjYXJfZHVfY3J0YyAqcmNy dGMgPSB0b19yY2FyX2NydGMoY3J0Yyk7CiAKIAlyY2FyX2R1X2NydGNfd3JpdGUocmNydGMsIERT UkNSLCBEU1JDUl9WQkNMKTsKLQlyY2FyX2R1X2NydGNfc2V0KHJjcnRjLCBESUVSLCBESUVSX1ZC RSk7CisJcmNhcl9kdV9jcnRjX2Nscl9zZXQocmNydGMsIERJRVIsIERJRVJfVFZFIHwgRElFUl9G UkUsIERJRVJfVkJFKTsKIAlyY3J0Yy0+dmJsYW5rX2VuYWJsZSA9IHRydWU7CiAKIAlyZXR1cm4g MDsKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9yY2FyLWR1L3JjYXJfZHVfZHJ2LmMgYi9k cml2ZXJzL2dwdS9kcm0vcmNhci1kdS9yY2FyX2R1X2Rydi5jCmluZGV4IDU2Zjk0NzIuLjVjMmY3 NjQgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9yY2FyLWR1L3JjYXJfZHVfZHJ2LmMKKysr IGIvZHJpdmVycy9ncHUvZHJtL3JjYXItZHUvcmNhcl9kdV9kcnYuYwpAQCAtMjk0LDYgKzI5NCwz MSBAQCBzdGF0aWMgY29uc3Qgc3RydWN0IHJjYXJfZHVfZGV2aWNlX2luZm8gcmNhcl9kdV9yOGE3 Nzk3MF9pbmZvID0gewogCS5udW1fbHZkcyA9IDEsCiB9OwogCitzdGF0aWMgY29uc3Qgc3RydWN0 IHJjYXJfZHVfZGV2aWNlX2luZm8gcmNhcl9kdV9yOGE3Nzk5NV9pbmZvID0geworCS5nZW4gPSAz LAorCS5mZWF0dXJlcyA9IFJDQVJfRFVfRkVBVFVSRV9DUlRDX0lSUV9DTE9DSworCQkgIHwgUkNB Ul9EVV9GRUFUVVJFX0VYVF9DVFJMX1JFR1MKKwkJICB8IFJDQVJfRFVfRkVBVFVSRV9WU1AxX1NP VVJDRSwKKwkucXVpcmtzID0gUkNBUl9EVV9RVUlSS19UVk1fTUFTVEVSX09OTFksCisJLmNoYW5u ZWxzX21hc2sgPSBCSVQoMSkgfCBCSVQoMCksCisJLnJvdXRlcyA9IHsKKwkJLyogUjhBNzc5OTUg aGFzIHR3byBMVkRTIG91dHB1dCBhbmQgb25lIFJHQiBvdXRwdXQuICovCisJCVtSQ0FSX0RVX09V VFBVVF9EUEFEMF0gPSB7CisJCQkucG9zc2libGVfY3J0Y3MgPSBCSVQoMCkgfCBCSVQoMSksCisJ CQkucG9ydCA9IDAsCisJCX0sCisJCVtSQ0FSX0RVX09VVFBVVF9MVkRTMF0gPSB7CisJCQkucG9z c2libGVfY3J0Y3MgPSBCSVQoMCksCisJCQkucG9ydCA9IDEsCisJCX0sCisJCVtSQ0FSX0RVX09V VFBVVF9MVkRTMV0gPSB7CisJCQkucG9zc2libGVfY3J0Y3MgPSBCSVQoMSksCisJCQkucG9ydCA9 IDIsCisJCX0sCisJfSwKKwkubnVtX2x2ZHMgPSAyLAorfTsKKwogc3RhdGljIGNvbnN0IHN0cnVj dCBvZl9kZXZpY2VfaWQgcmNhcl9kdV9vZl90YWJsZVtdID0gewogCXsgLmNvbXBhdGlibGUgPSAi cmVuZXNhcyxkdS1yOGE3NzQzIiwgLmRhdGEgPSAmcnpnMV9kdV9yOGE3NzQzX2luZm8gfSwKIAl7 IC5jb21wYXRpYmxlID0gInJlbmVzYXMsZHUtcjhhNzc0NSIsIC5kYXRhID0gJnJ6ZzFfZHVfcjhh Nzc0NV9pbmZvIH0sCkBAIC0zMDcsNiArMzMyLDcgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCBvZl9k ZXZpY2VfaWQgcmNhcl9kdV9vZl90YWJsZVtdID0gewogCXsgLmNvbXBhdGlibGUgPSAicmVuZXNh cyxkdS1yOGE3Nzk2IiwgLmRhdGEgPSAmcmNhcl9kdV9yOGE3Nzk2X2luZm8gfSwKIAl7IC5jb21w YXRpYmxlID0gInJlbmVzYXMsZHUtcjhhNzc5NjUiLCAuZGF0YSA9ICZyY2FyX2R1X3I4YTc3OTY1 X2luZm8gfSwKIAl7IC5jb21wYXRpYmxlID0gInJlbmVzYXMsZHUtcjhhNzc5NzAiLCAuZGF0YSA9 ICZyY2FyX2R1X3I4YTc3OTcwX2luZm8gfSwKKwl7IC5jb21wYXRpYmxlID0gInJlbmVzYXMsZHUt cjhhNzc5OTUiLCAuZGF0YSA9ICZyY2FyX2R1X3I4YTc3OTk1X2luZm8gfSwKIAl7IH0KIH07CiAK ZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9yY2FyLWR1L3JjYXJfZHVfZHJ2LmggYi9kcml2 ZXJzL2dwdS9kcm0vcmNhci1kdS9yY2FyX2R1X2Rydi5oCmluZGV4IGIzYTI1ZTguLjYyNTc0MDUg MTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9yY2FyLWR1L3JjYXJfZHVfZHJ2LmgKKysrIGIv ZHJpdmVycy9ncHUvZHJtL3JjYXItZHUvcmNhcl9kdV9kcnYuaApAQCAtMzIsNiArMzIsNyBAQCBz dHJ1Y3QgcmNhcl9kdV9kZXZpY2U7CiAjZGVmaW5lIFJDQVJfRFVfRkVBVFVSRV9WU1AxX1NPVVJD RQkoMSA8PCAyKQkvKiBIYXMgaW5wdXRzIGZyb20gVlNQMSAqLwogCiAjZGVmaW5lIFJDQVJfRFVf UVVJUktfQUxJR05fMTI4QgkoMSA8PCAwKQkvKiBBbGlnbiBwaXRjaGVzIHRvIDEyOCBieXRlcyAq LworI2RlZmluZSBSQ0FSX0RVX1FVSVJLX1RWTV9NQVNURVJfT05MWQkoMSA8PCAxKQkvKiBEb2Vz IG5vdCBoYXZlIFRWIHN3aXRjaC9zeW5jIG1vZGVzICovCiAKIC8qCiAgKiBzdHJ1Y3QgcmNhcl9k dV9vdXRwdXRfcm91dGluZyAtIE91dHB1dCByb3V0aW5nIHNwZWNpZmljYXRpb24KZGlmZiAtLWdp dCBhL2RyaXZlcnMvZ3B1L2RybS9yY2FyLWR1L3JjYXJfZHVfZ3JvdXAuYyBiL2RyaXZlcnMvZ3B1 L2RybS9yY2FyLWR1L3JjYXJfZHVfZ3JvdXAuYwppbmRleCBkNTM5Y2IyLi45YTBhNjk0IDEwMDY0 NAotLS0gYS9kcml2ZXJzL2dwdS9kcm0vcmNhci1kdS9yY2FyX2R1X2dyb3VwLmMKKysrIGIvZHJp dmVycy9ncHUvZHJtL3JjYXItZHUvcmNhcl9kdV9ncm91cC5jCkBAIC0xNzgsNyArMTc4LDggQEAg dm9pZCByY2FyX2R1X2dyb3VwX3B1dChzdHJ1Y3QgcmNhcl9kdV9ncm91cCAqcmdycCkKIHN0YXRp YyB2b2lkIF9fcmNhcl9kdV9ncm91cF9zdGFydF9zdG9wKHN0cnVjdCByY2FyX2R1X2dyb3VwICpy Z3JwLCBib29sIHN0YXJ0KQogewogCXJjYXJfZHVfZ3JvdXBfd3JpdGUocmdycCwgRFNZU1IsCi0J CShyY2FyX2R1X2dyb3VwX3JlYWQocmdycCwgRFNZU1IpICYgfihEU1lTUl9EUkVTIHwgRFNZU1Jf REVOKSkgfAorCQkocmNhcl9kdV9ncm91cF9yZWFkKHJncnAsIERTWVNSKSAmCisJCSB+KERTWVNS X0RSRVMgfCBEU1lTUl9ERU4gfCBEU1lTUl9JTFRTKSkgfAogCQkoc3RhcnQgPyBEU1lTUl9ERU4g OiBEU1lTUl9EUkVTKSk7CiB9CiAKLS0gCjIuNy40CgpfX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBs aXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1h bi9saXN0aW5mby9kcmktZGV2ZWwK