From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from relay4-d.mail.gandi.net ([217.70.183.196]:53661 "EHLO relay4-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732016AbeHWSmf (ORCPT ); Thu, 23 Aug 2018 14:42:35 -0400 From: Jacopo Mondi To: Laurent Pinchart , David Airlie Cc: Jacopo Mondi , ulrich.hecht+renesas@gmail.com, kieran.bingham@ideasonboard.com, dri-devel@lists.freedesktop.org (open list:DRM DRIVERS FOR RENESAS), linux-renesas-soc@vger.kernel.org (open list:DRM DRIVERS FOR RENESAS) Subject: [PATCH 1/4] drm: rcar-du: Do not write ESCR for DPLL channels Date: Thu, 23 Aug 2018 17:12:11 +0200 Message-Id: <1535037134-373-2-git-send-email-jacopo+renesas@jmondi.org> In-Reply-To: <1535037134-373-1-git-send-email-jacopo+renesas@jmondi.org> References: <1535037134-373-1-git-send-email-jacopo+renesas@jmondi.org> Sender: linux-renesas-soc-owner@vger.kernel.org List-ID: According to revision 1.00 of R-Car Gen3 Soc manual, writing to ESCR register of DU channels equipped with a display PLL (DPLL) is invalid. Fix this by writing ESCR only for channels making use of the DU internal post-divider to generate the dotclockout signal, with R-Car H3 ES1.x being a notable exception. Signed-off-by: Jacopo Mondi --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index 1541152..7b1c05b 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -246,7 +246,6 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) struct rcar_du_device *rcdu = rcrtc->group->dev; unsigned long mode_clock = mode->clock * 1000; u32 dsmr; - u32 escr; if (rcdu->info->dpll_mask & (1 << rcrtc->index)) { unsigned long target = mode_clock; @@ -293,7 +292,11 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) rcar_du_group_write(rcrtc->group, DPLLCR, dpllcr); - escr = ESCR_DCLKSEL_DCLKIN | div; + /* Only H3 ES1.x has a post divider when a DPLL is present. */ + if (soc_device_match(rcar_du_r8a7795_es1)) + rcar_du_crtc_write(rcrtc, + rcrtc->index % 2 ? ESCR13 : ESCR02, + ESCR_DCLKSEL_DCLKIN | div); } else { struct du_clk_params params = { .diff = (unsigned long)-1 }; @@ -308,12 +311,10 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) params.rate); clk_set_rate(params.clk, params.rate); - escr = params.escr; + rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, + params.escr); } - dev_dbg(rcrtc->group->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr); - - rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr); rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0); /* Signal polarities */ -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jacopo Mondi Subject: [PATCH 1/4] drm: rcar-du: Do not write ESCR for DPLL channels Date: Thu, 23 Aug 2018 17:12:11 +0200 Message-ID: <1535037134-373-2-git-send-email-jacopo+renesas@jmondi.org> References: <1535037134-373-1-git-send-email-jacopo+renesas@jmondi.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9273089971 for ; Thu, 23 Aug 2018 15:12:30 +0000 (UTC) In-Reply-To: <1535037134-373-1-git-send-email-jacopo+renesas@jmondi.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Laurent Pinchart , David Airlie Cc: ulrich.hecht+renesas@gmail.com, "open list:DRM DRIVERS FOR RENESAS" , Jacopo Mondi , kieran.bingham@ideasonboard.com, "open list:DRM DRIVERS FOR RENESAS" List-Id: dri-devel@lists.freedesktop.org QWNjb3JkaW5nIHRvIHJldmlzaW9uIDEuMDAgb2YgUi1DYXIgR2VuMyBTb2MgbWFudWFsLCB3cml0 aW5nIHRvIEVTQ1IKcmVnaXN0ZXIgb2YgRFUgY2hhbm5lbHMgZXF1aXBwZWQgd2l0aCBhIGRpc3Bs YXkgUExMIChEUExMKSBpcyBpbnZhbGlkLgoKRml4IHRoaXMgYnkgd3JpdGluZyBFU0NSIG9ubHkg Zm9yIGNoYW5uZWxzIG1ha2luZyB1c2Ugb2YgdGhlIERVIGludGVybmFsCnBvc3QtZGl2aWRlciB0 byBnZW5lcmF0ZSB0aGUgZG90Y2xvY2tvdXQgc2lnbmFsLCB3aXRoIFItQ2FyIEgzIEVTMS54IGJl aW5nCmEgbm90YWJsZSBleGNlcHRpb24uCgpTaWduZWQtb2ZmLWJ5OiBKYWNvcG8gTW9uZGkgPGph Y29wbytyZW5lc2FzQGptb25kaS5vcmc+Ci0tLQogZHJpdmVycy9ncHUvZHJtL3JjYXItZHUvcmNh cl9kdV9jcnRjLmMgfCAxMyArKysrKysrLS0tLS0tCiAxIGZpbGUgY2hhbmdlZCwgNyBpbnNlcnRp b25zKCspLCA2IGRlbGV0aW9ucygtKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9yY2Fy LWR1L3JjYXJfZHVfY3J0Yy5jIGIvZHJpdmVycy9ncHUvZHJtL3JjYXItZHUvcmNhcl9kdV9jcnRj LmMKaW5kZXggMTU0MTE1Mi4uN2IxYzA1YiAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL3Jj YXItZHUvcmNhcl9kdV9jcnRjLmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL3JjYXItZHUvcmNhcl9k dV9jcnRjLmMKQEAgLTI0Niw3ICsyNDYsNiBAQCBzdGF0aWMgdm9pZCByY2FyX2R1X2NydGNfc2V0 X2Rpc3BsYXlfdGltaW5nKHN0cnVjdCByY2FyX2R1X2NydGMgKnJjcnRjKQogCXN0cnVjdCByY2Fy X2R1X2RldmljZSAqcmNkdSA9IHJjcnRjLT5ncm91cC0+ZGV2OwogCXVuc2lnbmVkIGxvbmcgbW9k ZV9jbG9jayA9IG1vZGUtPmNsb2NrICogMTAwMDsKIAl1MzIgZHNtcjsKLQl1MzIgZXNjcjsKIAog CWlmIChyY2R1LT5pbmZvLT5kcGxsX21hc2sgJiAoMSA8PCByY3J0Yy0+aW5kZXgpKSB7CiAJCXVu c2lnbmVkIGxvbmcgdGFyZ2V0ID0gbW9kZV9jbG9jazsKQEAgLTI5Myw3ICsyOTIsMTEgQEAgc3Rh dGljIHZvaWQgcmNhcl9kdV9jcnRjX3NldF9kaXNwbGF5X3RpbWluZyhzdHJ1Y3QgcmNhcl9kdV9j cnRjICpyY3J0YykKIAogCQlyY2FyX2R1X2dyb3VwX3dyaXRlKHJjcnRjLT5ncm91cCwgRFBMTENS LCBkcGxsY3IpOwogCi0JCWVzY3IgPSBFU0NSX0RDTEtTRUxfRENMS0lOIHwgZGl2OworCQkvKiBP bmx5IEgzIEVTMS54IGhhcyBhIHBvc3QgZGl2aWRlciB3aGVuIGEgRFBMTCBpcyBwcmVzZW50LiAq LworCQlpZiAoc29jX2RldmljZV9tYXRjaChyY2FyX2R1X3I4YTc3OTVfZXMxKSkKKwkJCXJjYXJf ZHVfY3J0Y193cml0ZShyY3J0YywKKwkJCQkJICAgcmNydGMtPmluZGV4ICUgMiA/IEVTQ1IxMyA6 IEVTQ1IwMiwKKwkJCQkJICAgRVNDUl9EQ0xLU0VMX0RDTEtJTiB8IGRpdik7CiAJfSBlbHNlIHsK IAkJc3RydWN0IGR1X2Nsa19wYXJhbXMgcGFyYW1zID0geyAuZGlmZiA9ICh1bnNpZ25lZCBsb25n KS0xIH07CiAKQEAgLTMwOCwxMiArMzExLDEwIEBAIHN0YXRpYyB2b2lkIHJjYXJfZHVfY3J0Y19z ZXRfZGlzcGxheV90aW1pbmcoc3RydWN0IHJjYXJfZHVfY3J0YyAqcmNydGMpCiAJCQlwYXJhbXMu cmF0ZSk7CiAKIAkJY2xrX3NldF9yYXRlKHBhcmFtcy5jbGssIHBhcmFtcy5yYXRlKTsKLQkJZXNj ciA9IHBhcmFtcy5lc2NyOworCQlyY2FyX2R1X2NydGNfd3JpdGUocmNydGMsIHJjcnRjLT5pbmRl eCAlIDIgPyBFU0NSMTMgOiBFU0NSMDIsCisJCQkJICAgcGFyYW1zLmVzY3IpOwogCX0KIAotCWRl dl9kYmcocmNydGMtPmdyb3VwLT5kZXYtPmRldiwgIiVzOiBFU0NSIDB4JTA4eFxuIiwgX19mdW5j X18sIGVzY3IpOwotCi0JcmNhcl9kdV9jcnRjX3dyaXRlKHJjcnRjLCByY3J0Yy0+aW5kZXggJSAy ID8gRVNDUjEzIDogRVNDUjAyLCBlc2NyKTsKIAlyY2FyX2R1X2NydGNfd3JpdGUocmNydGMsIHJj cnRjLT5pbmRleCAlIDIgPyBPVEFSMTMgOiBPVEFSMDIsIDApOwogCiAJLyogU2lnbmFsIHBvbGFy aXRpZXMgKi8KLS0gCjIuNy40CgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVz a3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9k cmktZGV2ZWwK