From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from relay4-d.mail.gandi.net ([217.70.183.196]:45903 "EHLO relay4-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732016AbeHWSmi (ORCPT ); Thu, 23 Aug 2018 14:42:38 -0400 From: Jacopo Mondi To: Laurent Pinchart , David Airlie Cc: Jacopo Mondi , ulrich.hecht+renesas@gmail.com, kieran.bingham@ideasonboard.com, dri-devel@lists.freedesktop.org (open list:DRM DRIVERS FOR RENESAS), linux-renesas-soc@vger.kernel.org (open list:DRM DRIVERS FOR RENESAS) Subject: [PATCH 3/4] drm: rcar-du: Fix handling of DORCR for group 1 Date: Thu, 23 Aug 2018 17:12:13 +0200 Message-Id: <1535037134-373-4-git-send-email-jacopo+renesas@jmondi.org> In-Reply-To: <1535037134-373-1-git-send-email-jacopo+renesas@jmondi.org> References: <1535037134-373-1-git-send-email-jacopo+renesas@jmondi.org> Sender: linux-renesas-soc-owner@vger.kernel.org List-ID: According to revision 1.00 of R-Car Gen3 Soc manual, only DU channels of group 0 (DU0 and DU1) supports output control routing through register DORCR0. For channels of group 1 (DU2 and DU3) which are only present on H3/M3-W/M3-N SoCs, no routing options are available between super-imposition processors and the output pin controller. The updated version of the SoC manual prescribes thus to hardcode DPRCR2 bits that controls output pin routing for those channels. Signed-off-by: Jacopo Mondi --- drivers/gpu/drm/rcar-du/rcar_du_group.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c index ef2c177..e79d424 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c @@ -127,10 +127,19 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp) rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | DEFR10_DEFE10); /* - * Use DS1PR and DS2PR to configure planes priorities and connects the - * superposition 0 to DU0 pins. DU1 pins will be configured dynamically. + * For group 0 (DU0/DU1) use DS1PR and DS2PR to configure planes + * priorities and connects the superposition 0 to DU0 pins. + * DU1 pins will be configured dynamically. + * + * For group 1 (DU2/DU3), if any, use DS2PR and DS3PT to configure + * planes priorities and hardcode other bits. */ - rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS); + if (rgrp->index == 0) + rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS); + else + rcar_du_group_write(rgrp, DORCR, DORCR_PG2T | DORCR_DK2S | + DORCR_PG2D_DS2 | DORCR_DPRS); + /* Apply planes to CRTCs association. */ mutex_lock(&rgrp->lock); @@ -247,6 +256,10 @@ int rcar_du_group_set_routing(struct rcar_du_group *rgrp) struct rcar_du_crtc *crtc0 = &rgrp->dev->crtcs[rgrp->index * 2]; u32 dorcr = rcar_du_group_read(rgrp, DORCR); + /* Only group 0 (DU0/DU1) has pin routing options. */ + if (rgrp->index > 0) + return 0; + dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK); /* -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jacopo Mondi Subject: [PATCH 3/4] drm: rcar-du: Fix handling of DORCR for group 1 Date: Thu, 23 Aug 2018 17:12:13 +0200 Message-ID: <1535037134-373-4-git-send-email-jacopo+renesas@jmondi.org> References: <1535037134-373-1-git-send-email-jacopo+renesas@jmondi.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) by gabe.freedesktop.org (Postfix) with ESMTPS id 36E2A89971 for ; Thu, 23 Aug 2018 15:12:33 +0000 (UTC) In-Reply-To: <1535037134-373-1-git-send-email-jacopo+renesas@jmondi.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Laurent Pinchart , David Airlie Cc: ulrich.hecht+renesas@gmail.com, "open list:DRM DRIVERS FOR RENESAS" , Jacopo Mondi , kieran.bingham@ideasonboard.com, "open list:DRM DRIVERS FOR RENESAS" List-Id: dri-devel@lists.freedesktop.org QWNjb3JkaW5nIHRvIHJldmlzaW9uIDEuMDAgb2YgUi1DYXIgR2VuMyBTb2MgbWFudWFsLCBvbmx5 IERVIGNoYW5uZWxzIG9mCmdyb3VwIDAgKERVMCBhbmQgRFUxKSBzdXBwb3J0cyBvdXRwdXQgY29u dHJvbCByb3V0aW5nIHRocm91Z2ggcmVnaXN0ZXIgRE9SQ1IwLgoKRm9yIGNoYW5uZWxzIG9mIGdy b3VwIDEgKERVMiBhbmQgRFUzKSB3aGljaCBhcmUgb25seSBwcmVzZW50IG9uIEgzL00zLVcvTTMt TgpTb0NzLCBubyByb3V0aW5nIG9wdGlvbnMgYXJlIGF2YWlsYWJsZSBiZXR3ZWVuIHN1cGVyLWlt cG9zaXRpb24gcHJvY2Vzc29ycwphbmQgdGhlIG91dHB1dCBwaW4gY29udHJvbGxlci4gVGhlIHVw ZGF0ZWQgdmVyc2lvbiBvZiB0aGUgU29DIG1hbnVhbApwcmVzY3JpYmVzIHRodXMgdG8gaGFyZGNv ZGUgRFBSQ1IyIGJpdHMgdGhhdCBjb250cm9scyBvdXRwdXQgcGluIHJvdXRpbmcgZm9yCnRob3Nl IGNoYW5uZWxzLgoKU2lnbmVkLW9mZi1ieTogSmFjb3BvIE1vbmRpIDxqYWNvcG8rcmVuZXNhc0Bq bW9uZGkub3JnPgotLS0KIGRyaXZlcnMvZ3B1L2RybS9yY2FyLWR1L3JjYXJfZHVfZ3JvdXAuYyB8 IDE5ICsrKysrKysrKysrKysrKystLS0KIDEgZmlsZSBjaGFuZ2VkLCAxNiBpbnNlcnRpb25zKCsp LCAzIGRlbGV0aW9ucygtKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9yY2FyLWR1L3Jj YXJfZHVfZ3JvdXAuYyBiL2RyaXZlcnMvZ3B1L2RybS9yY2FyLWR1L3JjYXJfZHVfZ3JvdXAuYwpp bmRleCBlZjJjMTc3Li5lNzlkNDI0IDEwMDY0NAotLS0gYS9kcml2ZXJzL2dwdS9kcm0vcmNhci1k dS9yY2FyX2R1X2dyb3VwLmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL3JjYXItZHUvcmNhcl9kdV9n cm91cC5jCkBAIC0xMjcsMTAgKzEyNywxOSBAQCBzdGF0aWMgdm9pZCByY2FyX2R1X2dyb3VwX3Nl dHVwKHN0cnVjdCByY2FyX2R1X2dyb3VwICpyZ3JwKQogCQlyY2FyX2R1X2dyb3VwX3dyaXRlKHJn cnAsIERFRlIxMCwgREVGUjEwX0NPREUgfCBERUZSMTBfREVGRTEwKTsKIAogCS8qCi0JICogVXNl IERTMVBSIGFuZCBEUzJQUiB0byBjb25maWd1cmUgcGxhbmVzIHByaW9yaXRpZXMgYW5kIGNvbm5l Y3RzIHRoZQotCSAqIHN1cGVycG9zaXRpb24gMCB0byBEVTAgcGlucy4gRFUxIHBpbnMgd2lsbCBi ZSBjb25maWd1cmVkIGR5bmFtaWNhbGx5LgorCSAqIEZvciBncm91cCAwIChEVTAvRFUxKSB1c2Ug RFMxUFIgYW5kIERTMlBSIHRvIGNvbmZpZ3VyZSBwbGFuZXMKKwkgKiBwcmlvcml0aWVzIGFuZCBj b25uZWN0cyB0aGUgc3VwZXJwb3NpdGlvbiAwIHRvIERVMCBwaW5zLgorCSAqIERVMSBwaW5zIHdp bGwgYmUgY29uZmlndXJlZCBkeW5hbWljYWxseS4KKwkgKgorCSAqIEZvciBncm91cCAxIChEVTIv RFUzKSwgaWYgYW55LCB1c2UgRFMyUFIgYW5kIERTM1BUIHRvIGNvbmZpZ3VyZQorCSAqIHBsYW5l cyBwcmlvcml0aWVzIGFuZCBoYXJkY29kZSBvdGhlciBiaXRzLgogCSAqLwotCXJjYXJfZHVfZ3Jv dXBfd3JpdGUocmdycCwgRE9SQ1IsIERPUkNSX1BHMURfRFMxIHwgRE9SQ1JfRFBSUyk7CisJaWYg KHJncnAtPmluZGV4ID09IDApCisJCXJjYXJfZHVfZ3JvdXBfd3JpdGUocmdycCwgRE9SQ1IsIERP UkNSX1BHMURfRFMxIHwgRE9SQ1JfRFBSUyk7CisJZWxzZQorCQlyY2FyX2R1X2dyb3VwX3dyaXRl KHJncnAsIERPUkNSLCBET1JDUl9QRzJUIHwgRE9SQ1JfREsyUyB8CisJCQkJICAgIERPUkNSX1BH MkRfRFMyIHwgRE9SQ1JfRFBSUyk7CisKIAogCS8qIEFwcGx5IHBsYW5lcyB0byBDUlRDcyBhc3Nv Y2lhdGlvbi4gKi8KIAltdXRleF9sb2NrKCZyZ3JwLT5sb2NrKTsKQEAgLTI0Nyw2ICsyNTYsMTAg QEAgaW50IHJjYXJfZHVfZ3JvdXBfc2V0X3JvdXRpbmcoc3RydWN0IHJjYXJfZHVfZ3JvdXAgKnJn cnApCiAJc3RydWN0IHJjYXJfZHVfY3J0YyAqY3J0YzAgPSAmcmdycC0+ZGV2LT5jcnRjc1tyZ3Jw LT5pbmRleCAqIDJdOwogCXUzMiBkb3JjciA9IHJjYXJfZHVfZ3JvdXBfcmVhZChyZ3JwLCBET1JD Uik7CiAKKwkvKiBPbmx5IGdyb3VwIDAgKERVMC9EVTEpIGhhcyBwaW4gcm91dGluZyBvcHRpb25z LiAqLworCWlmIChyZ3JwLT5pbmRleCA+IDApCisJCXJldHVybiAwOworCiAJZG9yY3IgJj0gfihE T1JDUl9QRzJUIHwgRE9SQ1JfREsyUyB8IERPUkNSX1BHMkRfTUFTSyk7CiAKIAkvKgotLSAKMi43 LjQKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1k ZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczov L2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbAo=