From mboxrd@z Thu Jan 1 00:00:00 1970 From: Hanjie Lin Subject: [PATCH v2 1/2] dt-bindings: phy: add DT bindings for Amlogic Meson PCIe Phy controller Date: Fri, 24 Aug 2018 15:33:25 +0800 Message-ID: <1535096006-152091-2-git-send-email-hanjie.lin@amlogic.com> References: <1535096006-152091-1-git-send-email-hanjie.lin@amlogic.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1535096006-152091-1-git-send-email-hanjie.lin@amlogic.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Kishon Vijay Abraham I Cc: Rob Herring , Hanjie Lin , Jianxin Pan , devicetree@vger.kernel.org, linux-pci@vger.kernel.org, Yixun Lan , Yue Wang , Qiufang Dai , Liang Yang , Jian Hu , Kevin Hilman , Carlo Caione , linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org From: Yue Wang The Meson-PCIE-PHY controller supports the 5-Gbps data rate of the PCI Express Gen 2 specification and is backward compatible with the 2.5-Gbps Gen 1.1 specification with only inferred idle detection supported on Amlogic SoCs. Signed-off-by: Hanjie Lin Signed-off-by: Yue Wang --- .../bindings/phy/amlogic,meson-pcie-phy.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt b/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt new file mode 100644 index 0000000..e2f0a27 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt @@ -0,0 +1,21 @@ +* Amlogic Meson AXG PCIE PHY binding + +Required properties: +- compatible: Should be + - "amlogic,axg-pcie-phy" +- #phys-cells: must be 0 (see phy-bindings.txt in this directory) +- reg: The base address and length of the registers +- resets: phandle to the reset lines +- reset-names: must contain "phy" and "peripheral" + - "phy" PHY reset +Optional properties: +- phy-supply: see phy-bindings.txt in this directory + +Example: + pcie_phy: pcie-phy@ff644000 { + #phy-cells = <0>; + compatible = "amlogic,axg-pcie-phy"; + reg = <0x0 0xff644000 0x0 0x2000>; + resets = <&reset RESET_PCIE_PHY>; + reset-names = "phy"; + }; -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sh2.amlogic.com ([58.32.228.45]:27897 "EHLO mail-sh2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726818AbeHXLGQ (ORCPT ); Fri, 24 Aug 2018 07:06:16 -0400 From: Hanjie Lin To: Kishon Vijay Abraham I CC: Yue Wang , Hanjie Lin , , , , Kevin Hilman , Carlo Caione , Rob Herring , Yixun Lan , Liang Yang , Jianxin Pan , Qiufang Dai , Jian Hu , Subject: [PATCH v2 1/2] dt-bindings: phy: add DT bindings for Amlogic Meson PCIe Phy controller Date: Fri, 24 Aug 2018 15:33:25 +0800 Message-ID: <1535096006-152091-2-git-send-email-hanjie.lin@amlogic.com> In-Reply-To: <1535096006-152091-1-git-send-email-hanjie.lin@amlogic.com> References: <1535096006-152091-1-git-send-email-hanjie.lin@amlogic.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-pci-owner@vger.kernel.org List-ID: From: Yue Wang The Meson-PCIE-PHY controller supports the 5-Gbps data rate of the PCI Express Gen 2 specification and is backward compatible with the 2.5-Gbps Gen 1.1 specification with only inferred idle detection supported on Amlogic SoCs. Signed-off-by: Hanjie Lin Signed-off-by: Yue Wang --- .../bindings/phy/amlogic,meson-pcie-phy.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt b/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt new file mode 100644 index 0000000..e2f0a27 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt @@ -0,0 +1,21 @@ +* Amlogic Meson AXG PCIE PHY binding + +Required properties: +- compatible: Should be + - "amlogic,axg-pcie-phy" +- #phys-cells: must be 0 (see phy-bindings.txt in this directory) +- reg: The base address and length of the registers +- resets: phandle to the reset lines +- reset-names: must contain "phy" and "peripheral" + - "phy" PHY reset +Optional properties: +- phy-supply: see phy-bindings.txt in this directory + +Example: + pcie_phy: pcie-phy@ff644000 { + #phy-cells = <0>; + compatible = "amlogic,axg-pcie-phy"; + reg = <0x0 0xff644000 0x0 0x2000>; + resets = <&reset RESET_PCIE_PHY>; + reset-names = "phy"; + }; -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: hanjie.lin@amlogic.com (Hanjie Lin) Date: Fri, 24 Aug 2018 15:33:25 +0800 Subject: [PATCH v2 1/2] dt-bindings: phy: add DT bindings for Amlogic Meson PCIe Phy controller In-Reply-To: <1535096006-152091-1-git-send-email-hanjie.lin@amlogic.com> References: <1535096006-152091-1-git-send-email-hanjie.lin@amlogic.com> Message-ID: <1535096006-152091-2-git-send-email-hanjie.lin@amlogic.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: Yue Wang The Meson-PCIE-PHY controller supports the 5-Gbps data rate of the PCI Express Gen 2 specification and is backward compatible with the 2.5-Gbps Gen 1.1 specification with only inferred idle detection supported on Amlogic SoCs. Signed-off-by: Hanjie Lin Signed-off-by: Yue Wang --- .../bindings/phy/amlogic,meson-pcie-phy.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt b/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt new file mode 100644 index 0000000..e2f0a27 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt @@ -0,0 +1,21 @@ +* Amlogic Meson AXG PCIE PHY binding + +Required properties: +- compatible: Should be + - "amlogic,axg-pcie-phy" +- #phys-cells: must be 0 (see phy-bindings.txt in this directory) +- reg: The base address and length of the registers +- resets: phandle to the reset lines +- reset-names: must contain "phy" and "peripheral" + - "phy" PHY reset +Optional properties: +- phy-supply: see phy-bindings.txt in this directory + +Example: + pcie_phy: pcie-phy at ff644000 { + #phy-cells = <0>; + compatible = "amlogic,axg-pcie-phy"; + reg = <0x0 0xff644000 0x0 0x2000>; + resets = <&reset RESET_PCIE_PHY>; + reset-names = "phy"; + }; -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: hanjie.lin@amlogic.com (Hanjie Lin) Date: Fri, 24 Aug 2018 15:33:25 +0800 Subject: [PATCH v2 1/2] dt-bindings: phy: add DT bindings for Amlogic Meson PCIe Phy controller In-Reply-To: <1535096006-152091-1-git-send-email-hanjie.lin@amlogic.com> References: <1535096006-152091-1-git-send-email-hanjie.lin@amlogic.com> Message-ID: <1535096006-152091-2-git-send-email-hanjie.lin@amlogic.com> To: linus-amlogic@lists.infradead.org List-Id: linus-amlogic.lists.infradead.org From: Yue Wang The Meson-PCIE-PHY controller supports the 5-Gbps data rate of the PCI Express Gen 2 specification and is backward compatible with the 2.5-Gbps Gen 1.1 specification with only inferred idle detection supported on Amlogic SoCs. Signed-off-by: Hanjie Lin Signed-off-by: Yue Wang --- .../bindings/phy/amlogic,meson-pcie-phy.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt b/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt new file mode 100644 index 0000000..e2f0a27 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt @@ -0,0 +1,21 @@ +* Amlogic Meson AXG PCIE PHY binding + +Required properties: +- compatible: Should be + - "amlogic,axg-pcie-phy" +- #phys-cells: must be 0 (see phy-bindings.txt in this directory) +- reg: The base address and length of the registers +- resets: phandle to the reset lines +- reset-names: must contain "phy" and "peripheral" + - "phy" PHY reset +Optional properties: +- phy-supply: see phy-bindings.txt in this directory + +Example: + pcie_phy: pcie-phy at ff644000 { + #phy-cells = <0>; + compatible = "amlogic,axg-pcie-phy"; + reg = <0x0 0xff644000 0x0 0x2000>; + resets = <&reset RESET_PCIE_PHY>; + reset-names = "phy"; + }; -- 2.7.4