* [PATCH 0/4] Enable Y210, Y212, Y216 formats for ICL
@ 2018-08-27 6:47 Swati Sharma
2018-08-27 6:47 ` [PATCH 1/4] drm: Add Y210, Y212, Y216 format definitions and fourcc Swati Sharma
` (6 more replies)
0 siblings, 7 replies; 14+ messages in thread
From: Swati Sharma @ 2018-08-27 6:47 UTC (permalink / raw)
To: dri-devel; +Cc: daniel.vetter, intel-gfx
These patches enable packed format YUV422-Y210, Y212 and Y216
for 10, 12 and 16 bit respectively for ICL.
For user space component IGT:WIP
Vidya Srinivas (4):
drm: Add Y210, Y212, Y216 format definitions and fourcc
drm/i915: Add Y210, Y212, Y216 plane control definitions
drm/i915: Preparations for enabling Y210, Y212, Y216 formats
drm/i915: Enable Y210, Y212, Y216 format for primary and sprite planes
drivers/gpu/drm/drm_fourcc.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_display.c | 40 ++++++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_sprite.c | 25 ++++++++++++++++++++--
include/uapi/drm/drm_fourcc.h | 4 ++++
5 files changed, 71 insertions(+), 4 deletions(-)
--
1.9.1
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/4] drm: Add Y210, Y212, Y216 format definitions and fourcc
2018-08-27 6:47 [PATCH 0/4] Enable Y210, Y212, Y216 formats for ICL Swati Sharma
@ 2018-08-27 6:47 ` Swati Sharma
2018-08-27 7:17 ` Kumar, Mahesh
2018-08-28 10:21 ` Alexandru-Cosmin Gheorghe
2018-08-27 6:47 ` [PATCH 2/4] drm/i915: Add Y210, Y212, Y216 plane control definitions Swati Sharma
` (5 subsequent siblings)
6 siblings, 2 replies; 14+ messages in thread
From: Swati Sharma @ 2018-08-27 6:47 UTC (permalink / raw)
To: dri-devel; +Cc: daniel.vetter, intel-gfx
From: Vidya Srinivas <vidya.srinivas@intel.com>
The following pixel formats are packed format that follows 4:2:2
chroma sampling. For memory represenation each component is
allocated 16 bits each. Thus each pixel occupies a DWORD.
Y210: Valid data occupies MSB 10 bits.
LSB 6 bits are filled with zeroes.
Y212: Valid data occupies MSB 12 bits.
LSB 4 bits are filled with zeroes.
Y216: Valid data occupies 16 bits,
doesn't require any padding bits.
First 16 bits stores the Y value and the next 16 bits stores one
of the chroma samples alternatively. The first luma sample will
be accompanied by first U sample and second luma sample is
accompanied by the first V sample.
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
include/uapi/drm/drm_fourcc.h | 4 ++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 35c1e27..4bf04a5 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -173,6 +173,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },
+ { .format = DRM_FORMAT_Y210, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
+ { .format = DRM_FORMAT_Y212, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
+ { .format = DRM_FORMAT_Y216, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 2ed46e9..6a03e6d 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -149,6 +149,10 @@
#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Y0:Cb0:Y1:Cr1 10:10:10:10 little endian */
+#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Y0:Cb0:Y1:Cr1 12:12:12:12 little endian */
+#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */
+
/*
* 2 plane RGB + A
* index 0 = RGB plane, same format as the corresponding non _A8 format has
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/4] drm/i915: Add Y210, Y212, Y216 plane control definitions
2018-08-27 6:47 [PATCH 0/4] Enable Y210, Y212, Y216 formats for ICL Swati Sharma
2018-08-27 6:47 ` [PATCH 1/4] drm: Add Y210, Y212, Y216 format definitions and fourcc Swati Sharma
@ 2018-08-27 6:47 ` Swati Sharma
2018-08-27 7:21 ` Kumar, Mahesh
2018-08-27 6:47 ` [PATCH 3/4] drm/i915: Preparations for enabling Y210, Y212, Y216 formats Swati Sharma
` (4 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Swati Sharma @ 2018-08-27 6:47 UTC (permalink / raw)
To: dri-devel
Cc: vidya.srinivas, juhapekka.heikkila, daniel.vetter, intel-gfx,
mahesh1.kumar, Swati Sharma
From: Vidya Srinivas <vidya.srinivas@intel.com>
Added needed plane control flag definitions for Y210, Y212 and
Y216 formats.
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8534f88..926e42d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6504,6 +6504,9 @@ enum {
#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
+#define PLANE_CTL_FORMAT_Y210 (1 << 23)
+#define PLANE_CTL_FORMAT_Y212 (3 << 23)
+#define PLANE_CTL_FORMAT_Y216 (5 << 23)
#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
#define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
#define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
--
1.9.1
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/4] drm/i915: Preparations for enabling Y210, Y212, Y216 formats
2018-08-27 6:47 [PATCH 0/4] Enable Y210, Y212, Y216 formats for ICL Swati Sharma
2018-08-27 6:47 ` [PATCH 1/4] drm: Add Y210, Y212, Y216 format definitions and fourcc Swati Sharma
2018-08-27 6:47 ` [PATCH 2/4] drm/i915: Add Y210, Y212, Y216 plane control definitions Swati Sharma
@ 2018-08-27 6:47 ` Swati Sharma
2018-08-27 7:54 ` Kumar, Mahesh
2018-08-27 6:47 ` [PATCH 4/4] drm/i915: Enable Y210, Y212, Y216 format for primary and sprite planes Swati Sharma
` (3 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Swati Sharma @ 2018-08-27 6:47 UTC (permalink / raw)
To: dri-devel; +Cc: daniel.vetter, intel-gfx
From: Vidya Srinivas <vidya.srinivas@intel.com>
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++
drivers/gpu/drm/i915/intel_sprite.c | 3 +++
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 30fdfd1..91aa8cc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3511,6 +3511,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
case DRM_FORMAT_NV12:
return PLANE_CTL_FORMAT_NV12;
+ case DRM_FORMAT_Y210:
+ return PLANE_CTL_FORMAT_Y210;
+ case DRM_FORMAT_Y212:
+ return PLANE_CTL_FORMAT_Y212;
+ case DRM_FORMAT_Y216:
+ return PLANE_CTL_FORMAT_Y216;
default:
MISSING_CASE(pixel_format);
}
@@ -4959,6 +4965,9 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_Y210:
+ case DRM_FORMAT_Y212:
+ case DRM_FORMAT_Y216:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
@@ -13413,6 +13422,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_Y210:
+ case DRM_FORMAT_Y212:
+ case DRM_FORMAT_Y216:
case DRM_FORMAT_NV12:
if (modifier == I915_FORMAT_MOD_Yf_TILED)
return true;
@@ -14544,6 +14556,9 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_Y210:
+ case DRM_FORMAT_Y212:
+ case DRM_FORMAT_Y216:
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
DRM_DEBUG_KMS("unsupported pixel format: %s\n",
drm_get_format_name(mode_cmd->pixel_format, &format_name));
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index c286dda..417501f 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1419,6 +1419,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_Y210:
+ case DRM_FORMAT_Y212:
+ case DRM_FORMAT_Y216:
case DRM_FORMAT_NV12:
if (modifier == I915_FORMAT_MOD_Yf_TILED)
return true;
--
1.9.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/4] drm/i915: Enable Y210, Y212, Y216 format for primary and sprite planes
2018-08-27 6:47 [PATCH 0/4] Enable Y210, Y212, Y216 formats for ICL Swati Sharma
` (2 preceding siblings ...)
2018-08-27 6:47 ` [PATCH 3/4] drm/i915: Preparations for enabling Y210, Y212, Y216 formats Swati Sharma
@ 2018-08-27 6:47 ` Swati Sharma
2018-08-27 7:59 ` Kumar, Mahesh
2018-08-27 7:01 ` ✗ Fi.CI.CHECKPATCH: warning for Enable Y210, Y212, Y216 formats for ICL Patchwork
` (2 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Swati Sharma @ 2018-08-27 6:47 UTC (permalink / raw)
To: dri-devel; +Cc: daniel.vetter, intel-gfx
From: Vidya Srinivas <vidya.srinivas@intel.com>
In this patch, a list for icl specific pixel formats is created
in which Y210, Y212 and Y216 pixel formats are added along with
legacy pixel formats for primary and sprite plane.
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_sprite.c | 22 ++++++++++++++++++++--
2 files changed, 43 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 91aa8cc..30065e3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -104,6 +104,24 @@
DRM_FORMAT_NV12,
};
+static const uint32_t icl_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_Y210,
+ DRM_FORMAT_Y212,
+ DRM_FORMAT_Y216,
+};
+
static const uint64_t skl_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -13718,8 +13736,11 @@ bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) >= 9) {
primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
PLANE_PRIMARY);
-
- if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
+ intel_primary_formats = icl_primary_formats;
+ num_formats = ARRAY_SIZE(icl_primary_formats);
+ } else if (skl_plane_has_planar(dev_priv, pipe,
+ PLANE_PRIMARY)) {
intel_primary_formats = skl_pri_planar_formats;
num_formats = ARRAY_SIZE(skl_pri_planar_formats);
} else {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 417501f..2abdd85 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1281,6 +1281,21 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
DRM_FORMAT_NV12,
};
+static uint32_t icl_plane_formats[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_Y210,
+ DRM_FORMAT_Y212,
+ DRM_FORMAT_Y216,
+};
+
static const uint64_t skl_plane_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -1536,8 +1551,11 @@ struct intel_plane *
intel_plane->disable_plane = skl_disable_plane;
intel_plane->get_hw_state = skl_plane_get_hw_state;
- if (skl_plane_has_planar(dev_priv, pipe,
- PLANE_SPRITE0 + plane)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
+ plane_formats = icl_plane_formats;
+ num_plane_formats = ARRAY_SIZE(icl_plane_formats);
+ } else if (skl_plane_has_planar(dev_priv, pipe,
+ PLANE_SPRITE0 + plane)) {
plane_formats = skl_planar_formats;
num_plane_formats = ARRAY_SIZE(skl_planar_formats);
} else {
--
1.9.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Enable Y210, Y212, Y216 formats for ICL
2018-08-27 6:47 [PATCH 0/4] Enable Y210, Y212, Y216 formats for ICL Swati Sharma
` (3 preceding siblings ...)
2018-08-27 6:47 ` [PATCH 4/4] drm/i915: Enable Y210, Y212, Y216 format for primary and sprite planes Swati Sharma
@ 2018-08-27 7:01 ` Patchwork
2018-08-27 7:18 ` ✓ Fi.CI.BAT: success " Patchwork
2018-08-27 8:08 ` ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2018-08-27 7:01 UTC (permalink / raw)
To: Swati Sharma; +Cc: intel-gfx
== Series Details ==
Series: Enable Y210, Y212, Y216 formats for ICL
URL : https://patchwork.freedesktop.org/series/48729/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c9d04d7941bb drm: Add Y210, Y212, Y216 format definitions and fourcc
-:33: WARNING:LONG_LINE: line over 100 characters
#33: FILE: drivers/gpu/drm/drm_fourcc.c:176:
+ { .format = DRM_FORMAT_Y210, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
-:34: WARNING:LONG_LINE: line over 100 characters
#34: FILE: drivers/gpu/drm/drm_fourcc.c:177:
+ { .format = DRM_FORMAT_Y212, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
-:35: WARNING:LONG_LINE: line over 100 characters
#35: FILE: drivers/gpu/drm/drm_fourcc.c:178:
+ { .format = DRM_FORMAT_Y216, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
-:47: WARNING:LONG_LINE_COMMENT: line over 100 characters
#47: FILE: include/uapi/drm/drm_fourcc.h:152:
+#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Y0:Cb0:Y1:Cr1 10:10:10:10 little endian */
-:48: WARNING:LONG_LINE_COMMENT: line over 100 characters
#48: FILE: include/uapi/drm/drm_fourcc.h:153:
+#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Y0:Cb0:Y1:Cr1 12:12:12:12 little endian */
-:49: WARNING:LONG_LINE_COMMENT: line over 100 characters
#49: FILE: include/uapi/drm/drm_fourcc.h:154:
+#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */
total: 0 errors, 6 warnings, 0 checks, 19 lines checked
c5c4436ab3aa drm/i915: Add Y210, Y212, Y216 plane control definitions
b21269a9abdb drm/i915: Preparations for enabling Y210, Y212, Y216 formats
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 48 lines checked
ff10f4e6686c drm/i915: Enable Y210, Y212, Y216 format for primary and sprite planes
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/4] drm: Add Y210, Y212, Y216 format definitions and fourcc
2018-08-27 6:47 ` [PATCH 1/4] drm: Add Y210, Y212, Y216 format definitions and fourcc Swati Sharma
@ 2018-08-27 7:17 ` Kumar, Mahesh
2018-08-27 7:50 ` Kumar, Mahesh
2018-08-28 10:21 ` Alexandru-Cosmin Gheorghe
1 sibling, 1 reply; 14+ messages in thread
From: Kumar, Mahesh @ 2018-08-27 7:17 UTC (permalink / raw)
To: Swati Sharma, dri-devel; +Cc: daniel.vetter, intel-gfx
Hi,
On 8/27/2018 12:17 PM, Swati Sharma wrote:
> From: Vidya Srinivas <vidya.srinivas@intel.com>
>
> The following pixel formats are packed format that follows 4:2:2
> chroma sampling. For memory represenation each component is
> allocated 16 bits each. Thus each pixel occupies a DWORD.
>
> Y210: Valid data occupies MSB 10 bits.
> LSB 6 bits are filled with zeroes.
> Y212: Valid data occupies MSB 12 bits.
> LSB 4 bits are filled with zeroes.
> Y216: Valid data occupies 16 bits,
> doesn't require any padding bits.
>
> First 16 bits stores the Y value and the next 16 bits stores one
> of the chroma samples alternatively. The first luma sample will
> be accompanied by first U sample and second luma sample is
> accompanied by the first V sample.
>
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
> drivers/gpu/drm/drm_fourcc.c | 3 +++
> include/uapi/drm/drm_fourcc.h | 4 ++++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index 35c1e27..4bf04a5 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -173,6 +173,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },
> + { .format = DRM_FORMAT_Y210, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
> + { .format = DRM_FORMAT_Y212, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
> + { .format = DRM_FORMAT_Y216, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
> };
you should also set is_yuv to true.
-Mahesh
>
> unsigned int i;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 2ed46e9..6a03e6d 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -149,6 +149,10 @@
>
> #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
>
> +#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Y0:Cb0:Y1:Cr1 10:10:10:10 little endian */
> +#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Y0:Cb0:Y1:Cr1 12:12:12:12 little endian */
> +#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */
> +
> /*
> * 2 plane RGB + A
> * index 0 = RGB plane, same format as the corresponding non _A8 format has
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Fi.CI.BAT: success for Enable Y210, Y212, Y216 formats for ICL
2018-08-27 6:47 [PATCH 0/4] Enable Y210, Y212, Y216 formats for ICL Swati Sharma
` (4 preceding siblings ...)
2018-08-27 7:01 ` ✗ Fi.CI.CHECKPATCH: warning for Enable Y210, Y212, Y216 formats for ICL Patchwork
@ 2018-08-27 7:18 ` Patchwork
2018-08-27 8:08 ` ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2018-08-27 7:18 UTC (permalink / raw)
To: Swati Sharma; +Cc: intel-gfx
== Series Details ==
Series: Enable Y210, Y212, Y216 formats for ICL
URL : https://patchwork.freedesktop.org/series/48729/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4706 -> Patchwork_10019 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10019 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10019, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/48729/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10019:
=== IGT changes ===
==== Warnings ====
igt@drv_selftest@live_execlists:
fi-whl-u: SKIP -> PASS +1
{igt@kms_psr@primary_page_flip}:
fi-cnl-psr: DMESG-WARN -> DMESG-FAIL
== Known issues ==
Here are the changes found in Patchwork_10019 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_guc:
fi-skl-guc: NOTRUN -> DMESG-WARN (fdo#107175, fdo#107258)
==== Possible fixes ====
igt@drv_selftest@live_hangcheck:
fi-whl-u: DMESG-FAIL (fdo#106560) -> PASS
igt@gem_exec_suspend@basic-s3:
fi-blb-e6850: INCOMPLETE -> PASS
{igt@pm_rpm@module-reload}:
fi-cnl-psr: WARN (fdo#107602) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#107175 https://bugs.freedesktop.org/show_bug.cgi?id=107175
fdo#107258 https://bugs.freedesktop.org/show_bug.cgi?id=107258
fdo#107602 https://bugs.freedesktop.org/show_bug.cgi?id=107602
== Participating hosts (53 -> 49) ==
Additional (1): fi-skl-guc
Missing (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4706 -> Patchwork_10019
CI_DRM_4706: 6d5687919f3a3426243041b99111b576dd0576d0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4609: 0bc9763af77bbb37f2ed65cc39c398e88db7d8e3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10019: ff10f4e6686cf96d938487319a831907cc81227c @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ff10f4e6686c drm/i915: Enable Y210, Y212, Y216 format for primary and sprite planes
b21269a9abdb drm/i915: Preparations for enabling Y210, Y212, Y216 formats
c5c4436ab3aa drm/i915: Add Y210, Y212, Y216 plane control definitions
c9d04d7941bb drm: Add Y210, Y212, Y216 format definitions and fourcc
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10019/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/4] drm/i915: Add Y210, Y212, Y216 plane control definitions
2018-08-27 6:47 ` [PATCH 2/4] drm/i915: Add Y210, Y212, Y216 plane control definitions Swati Sharma
@ 2018-08-27 7:21 ` Kumar, Mahesh
0 siblings, 0 replies; 14+ messages in thread
From: Kumar, Mahesh @ 2018-08-27 7:21 UTC (permalink / raw)
To: Swati Sharma, dri-devel
Cc: daniel.vetter, intel-gfx, vidya.srinivas, juhapekka.heikkila
Hi,
Please include platform name in subject line:
<drm/i915/icl>
On 8/27/2018 12:17 PM, Swati Sharma wrote:
> From: Vidya Srinivas <vidya.srinivas@intel.com>
>
> Added needed plane control flag definitions for Y210, Y212 and
> Y216 formats.
may be, add more info in commit message
-Mahesh
>
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8534f88..926e42d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6504,6 +6504,9 @@ enum {
> #define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
> #define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
> #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
> +#define PLANE_CTL_FORMAT_Y210 (1 << 23)
> +#define PLANE_CTL_FORMAT_Y212 (3 << 23)
> +#define PLANE_CTL_FORMAT_Y216 (5 << 23)
> #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
> #define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21)
> #define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/4] drm: Add Y210, Y212, Y216 format definitions and fourcc
2018-08-27 7:17 ` Kumar, Mahesh
@ 2018-08-27 7:50 ` Kumar, Mahesh
0 siblings, 0 replies; 14+ messages in thread
From: Kumar, Mahesh @ 2018-08-27 7:50 UTC (permalink / raw)
To: Swati Sharma, dri-devel
Cc: daniel.vetter, intel-gfx, vidya.srinivas, juhapekka.heikkila
On 8/27/2018 12:47 PM, Kumar, Mahesh wrote:
> Hi,
>
>
> On 8/27/2018 12:17 PM, Swati Sharma wrote:
>> From: Vidya Srinivas <vidya.srinivas@intel.com>
>>
>> The following pixel formats are packed format that follows 4:2:2
>> chroma sampling. For memory represenation each component is
>> allocated 16 bits each. Thus each pixel occupies a DWORD.
>>
>> Y210: Valid data occupies MSB 10 bits.
>> LSB 6 bits are filled with zeroes.
>> Y212: Valid data occupies MSB 12 bits.
>> LSB 4 bits are filled with zeroes.
>> Y216: Valid data occupies 16 bits,
>> doesn't require any padding bits.
>>
>> First 16 bits stores the Y value and the next 16 bits stores one
>> of the chroma samples alternatively. The first luma sample will
>> be accompanied by first U sample and second luma sample is
>> accompanied by the first V sample.
>>
>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
>> ---
>> drivers/gpu/drm/drm_fourcc.c | 3 +++
>> include/uapi/drm/drm_fourcc.h | 4 ++++
>> 2 files changed, 7 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
>> index 35c1e27..4bf04a5 100644
>> --- a/drivers/gpu/drm/drm_fourcc.c
>> +++ b/drivers/gpu/drm/drm_fourcc.c
>> @@ -173,6 +173,9 @@ const struct drm_format_info
>> *__drm_format_info(u32 format)
>> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes
>> = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
>> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes
>> = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
>> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes
>> = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true,
>> .is_yuv = true },
>> + { .format = DRM_FORMAT_Y210, .depth = 0,
>> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
>> + { .format = DRM_FORMAT_Y212, .depth = 0,
>> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
>> + { .format = DRM_FORMAT_Y216, .depth = 0,
>> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
>> };
> you should also set is_yuv to true.
>
Apart from this there can be different order for YUV samples, Are you
going to add those as well?
> -Mahesh
>> unsigned int i;
>> diff --git a/include/uapi/drm/drm_fourcc.h
>> b/include/uapi/drm/drm_fourcc.h
>> index 2ed46e9..6a03e6d 100644
>> --- a/include/uapi/drm/drm_fourcc.h
>> +++ b/include/uapi/drm/drm_fourcc.h
>> @@ -149,6 +149,10 @@
>> #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /*
>> [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
>> +#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /*
>> [63:0] Y0:Cb0:Y1:Cr1 10:10:10:10 little endian */
>> +#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /*
>> [63:0] Y0:Cb0:Y1:Cr1 12:12:12:12 little endian */
>> +#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /*
>> [63:0] Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */
>> +
>> /*
>> * 2 plane RGB + A
>> * index 0 = RGB plane, same format as the corresponding non _A8
>> format has
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/4] drm/i915: Preparations for enabling Y210, Y212, Y216 formats
2018-08-27 6:47 ` [PATCH 3/4] drm/i915: Preparations for enabling Y210, Y212, Y216 formats Swati Sharma
@ 2018-08-27 7:54 ` Kumar, Mahesh
0 siblings, 0 replies; 14+ messages in thread
From: Kumar, Mahesh @ 2018-08-27 7:54 UTC (permalink / raw)
To: Swati Sharma, dri-devel; +Cc: daniel.vetter, intel-gfx
Hi,
On 8/27/2018 12:17 PM, Swati Sharma wrote:
> From: Vidya Srinivas <vidya.srinivas@intel.com>
>
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++
> drivers/gpu/drm/i915/intel_sprite.c | 3 +++
> 2 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 30fdfd1..91aa8cc 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3511,6 +3511,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
> return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
> case DRM_FORMAT_NV12:
> return PLANE_CTL_FORMAT_NV12;
> + case DRM_FORMAT_Y210:
> + return PLANE_CTL_FORMAT_Y210;
> + case DRM_FORMAT_Y212:
> + return PLANE_CTL_FORMAT_Y212;
> + case DRM_FORMAT_Y216:
> + return PLANE_CTL_FORMAT_Y216;
While programming YUV pixel format, you also need to program order of
samples in bits [17:16]
BTW 64 bits pixel format are not supported in all the planes, these are
supported only in HDR planes.
You should handle that as well.
-Mahesh
> default:
> MISSING_CASE(pixel_format);
> }
> @@ -4959,6 +4965,9 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_Y210:
> + case DRM_FORMAT_Y212:
> + case DRM_FORMAT_Y216:
> break;
> default:
> DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
> @@ -13413,6 +13422,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> + case DRM_FORMAT_Y210:
> + case DRM_FORMAT_Y212:
> + case DRM_FORMAT_Y216:
> case DRM_FORMAT_NV12:
> if (modifier == I915_FORMAT_MOD_Yf_TILED)
> return true;
> @@ -14544,6 +14556,9 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_VYUY:
> + case DRM_FORMAT_Y210:
> + case DRM_FORMAT_Y212:
> + case DRM_FORMAT_Y216:
> if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
> DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> drm_get_format_name(mode_cmd->pixel_format, &format_name));
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index c286dda..417501f 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1419,6 +1419,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> + case DRM_FORMAT_Y210:
> + case DRM_FORMAT_Y212:
> + case DRM_FORMAT_Y216:
> case DRM_FORMAT_NV12:
> if (modifier == I915_FORMAT_MOD_Yf_TILED)
> return true;
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 4/4] drm/i915: Enable Y210, Y212, Y216 format for primary and sprite planes
2018-08-27 6:47 ` [PATCH 4/4] drm/i915: Enable Y210, Y212, Y216 format for primary and sprite planes Swati Sharma
@ 2018-08-27 7:59 ` Kumar, Mahesh
0 siblings, 0 replies; 14+ messages in thread
From: Kumar, Mahesh @ 2018-08-27 7:59 UTC (permalink / raw)
To: Swati Sharma, dri-devel; +Cc: mahesh1.sh.kumar, daniel.vetter, intel-gfx
On 8/27/2018 12:17 PM, Swati Sharma wrote:
> From: Vidya Srinivas <vidya.srinivas@intel.com>
>
> In this patch, a list for icl specific pixel formats is created
> in which Y210, Y212 and Y216 pixel formats are added along with
> legacy pixel formats for primary and sprite plane.
>
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++--
> drivers/gpu/drm/i915/intel_sprite.c | 22 ++++++++++++++++++++--
> 2 files changed, 43 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 91aa8cc..30065e3 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -104,6 +104,24 @@
> DRM_FORMAT_NV12,
> };
>
> +static const uint32_t icl_primary_formats[] = {
> + DRM_FORMAT_C8,
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_ABGR8888,
> + DRM_FORMAT_XRGB2101010,
> + DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_VYUY,
> + DRM_FORMAT_Y210,
> + DRM_FORMAT_Y212,
> + DRM_FORMAT_Y216,
> +};
> +
> static const uint64_t skl_format_modifiers_noccs[] = {
> I915_FORMAT_MOD_Yf_TILED,
> I915_FORMAT_MOD_Y_TILED,
> @@ -13718,8 +13736,11 @@ bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
> if (INTEL_GEN(dev_priv) >= 9) {
> primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
> PLANE_PRIMARY);
> -
> - if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
> + if (INTEL_GEN(dev_priv) >= 11) {
> + intel_primary_formats = icl_primary_formats;
> + num_formats = ARRAY_SIZE(icl_primary_formats);
> + } else if (skl_plane_has_planar(dev_priv, pipe,
> + PLANE_PRIMARY)) {
> intel_primary_formats = skl_pri_planar_formats;
> num_formats = ARRAY_SIZE(skl_pri_planar_formats);
> } else {
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 417501f..2abdd85 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1281,6 +1281,21 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
> DRM_FORMAT_NV12,
> };
>
> +static uint32_t icl_plane_formats[] = {
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_ABGR8888,
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_VYUY,
> + DRM_FORMAT_Y210,
> + DRM_FORMAT_Y212,
> + DRM_FORMAT_Y216,
> +};
> +
> static const uint64_t skl_plane_format_modifiers_noccs[] = {
> I915_FORMAT_MOD_Yf_TILED,
> I915_FORMAT_MOD_Y_TILED,
> @@ -1536,8 +1551,11 @@ struct intel_plane *
> intel_plane->disable_plane = skl_disable_plane;
> intel_plane->get_hw_state = skl_plane_get_hw_state;
>
> - if (skl_plane_has_planar(dev_priv, pipe,
> - PLANE_SPRITE0 + plane)) {
> + if (INTEL_GEN(dev_priv) >= 11) {
> + plane_formats = icl_plane_formats;
> + num_plane_formats = ARRAY_SIZE(icl_plane_formats);
64 bits pixel formats are supported only with HDR planes.
-Mahesh
> + } else if (skl_plane_has_planar(dev_priv, pipe,
> + PLANE_SPRITE0 + plane)) {
> plane_formats = skl_planar_formats;
> num_plane_formats = ARRAY_SIZE(skl_planar_formats);
> } else {
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Fi.CI.IGT: success for Enable Y210, Y212, Y216 formats for ICL
2018-08-27 6:47 [PATCH 0/4] Enable Y210, Y212, Y216 formats for ICL Swati Sharma
` (5 preceding siblings ...)
2018-08-27 7:18 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-08-27 8:08 ` Patchwork
6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2018-08-27 8:08 UTC (permalink / raw)
To: Swati Sharma; +Cc: intel-gfx
== Series Details ==
Series: Enable Y210, Y212, Y216 formats for ICL
URL : https://patchwork.freedesktop.org/series/48729/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4706_full -> Patchwork_10019_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here are the changes found in Patchwork_10019_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_suspend@shrink:
shard-glk: PASS -> INCOMPLETE (fdo#106886, k.org#198133, fdo#103359)
igt@gem_exec_big:
shard-hsw: PASS -> INCOMPLETE (fdo#103540)
igt@kms_setmode@basic:
shard-kbl: PASS -> FAIL (fdo#99912)
==== Possible fixes ====
igt@gem_ctx_isolation@bcs0-s3:
shard-kbl: INCOMPLETE (fdo#103665) -> PASS
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-glk: FAIL (fdo#105363, fdo#102887) -> PASS
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4706 -> Patchwork_10019
CI_DRM_4706: 6d5687919f3a3426243041b99111b576dd0576d0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4609: 0bc9763af77bbb37f2ed65cc39c398e88db7d8e3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10019: ff10f4e6686cf96d938487319a831907cc81227c @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10019/shards.html
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/4] drm: Add Y210, Y212, Y216 format definitions and fourcc
2018-08-27 6:47 ` [PATCH 1/4] drm: Add Y210, Y212, Y216 format definitions and fourcc Swati Sharma
2018-08-27 7:17 ` Kumar, Mahesh
@ 2018-08-28 10:21 ` Alexandru-Cosmin Gheorghe
1 sibling, 0 replies; 14+ messages in thread
From: Alexandru-Cosmin Gheorghe @ 2018-08-28 10:21 UTC (permalink / raw)
To: Swati Sharma
Cc: vidya.srinivas, juhapekka.heikkila, daniel.vetter, intel-gfx,
mahesh1.kumar, dri-devel, nd
Hi Swati,
On Mon, Aug 27, 2018 at 12:17:45PM +0530, Swati Sharma wrote:
> From: Vidya Srinivas <vidya.srinivas@intel.com>
>
> The following pixel formats are packed format that follows 4:2:2
> chroma sampling. For memory represenation each component is
> allocated 16 bits each. Thus each pixel occupies a DWORD.
>
> Y210: Valid data occupies MSB 10 bits.
> LSB 6 bits are filled with zeroes.
> Y212: Valid data occupies MSB 12 bits.
> LSB 4 bits are filled with zeroes.
> Y216: Valid data occupies 16 bits,
> doesn't require any padding bits.
>
> First 16 bits stores the Y value and the next 16 bits stores one
> of the chroma samples alternatively. The first luma sample will
> be accompanied by first U sample and second luma sample is
> accompanied by the first V sample.
>
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
> drivers/gpu/drm/drm_fourcc.c | 3 +++
> include/uapi/drm/drm_fourcc.h | 4 ++++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index 35c1e27..4bf04a5 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -173,6 +173,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },
> + { .format = DRM_FORMAT_Y210, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
> + { .format = DRM_FORMAT_Y212, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
> + { .format = DRM_FORMAT_Y216, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1 },
> };
>
> unsigned int i;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 2ed46e9..6a03e6d 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -149,6 +149,10 @@
>
> #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
>
> +#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Y0:Cb0:Y1:Cr1 10:10:10:10 little endian */
> +#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Y0:Cb0:Y1:Cr1 12:12:12:12 little endian */
> +#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */
I don't think this comments reflect very well the actual layout of the
color planes, I think you need to describe the padding as well.
Just looking at the comments without reading the commit message you
could easily assume that the padding happens is in the [63:40] bits.
> +
> /*
> * 2 plane RGB + A
> * index 0 = RGB plane, same format as the corresponding non _A8 format has
> --
> 1.9.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Cheers,
Alex G
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^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2018-08-28 10:21 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-08-27 6:47 [PATCH 0/4] Enable Y210, Y212, Y216 formats for ICL Swati Sharma
2018-08-27 6:47 ` [PATCH 1/4] drm: Add Y210, Y212, Y216 format definitions and fourcc Swati Sharma
2018-08-27 7:17 ` Kumar, Mahesh
2018-08-27 7:50 ` Kumar, Mahesh
2018-08-28 10:21 ` Alexandru-Cosmin Gheorghe
2018-08-27 6:47 ` [PATCH 2/4] drm/i915: Add Y210, Y212, Y216 plane control definitions Swati Sharma
2018-08-27 7:21 ` Kumar, Mahesh
2018-08-27 6:47 ` [PATCH 3/4] drm/i915: Preparations for enabling Y210, Y212, Y216 formats Swati Sharma
2018-08-27 7:54 ` Kumar, Mahesh
2018-08-27 6:47 ` [PATCH 4/4] drm/i915: Enable Y210, Y212, Y216 format for primary and sprite planes Swati Sharma
2018-08-27 7:59 ` Kumar, Mahesh
2018-08-27 7:01 ` ✗ Fi.CI.CHECKPATCH: warning for Enable Y210, Y212, Y216 formats for ICL Patchwork
2018-08-27 7:18 ` ✓ Fi.CI.BAT: success " Patchwork
2018-08-27 8:08 ` ✓ Fi.CI.IGT: " Patchwork
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