From mboxrd@z Thu Jan 1 00:00:00 1970 From: Janine Hagemann Date: Tue, 28 Aug 2018 08:25:03 +0200 Subject: [U-Boot] [PATCH v4 5/7] rockchip: rk3288-phycore: set flash1 iodomain to 1.8V In-Reply-To: <1535437505-32297-1-git-send-email-j.hagemann@phytec.de> References: <1535437505-32297-1-git-send-email-j.hagemann@phytec.de> Message-ID: <1535437505-32297-6-git-send-email-j.hagemann@phytec.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de This pin is supplied by 1.8V, but the default iodomain setting is 3.3V. Signed-off-by: Janine Hagemann --- v4: No changes --- board/phytec/phycore_rk3288/phycore-rk3288.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c index ffe1833..8c1844a 100644 --- a/board/phytec/phycore_rk3288/phycore-rk3288.c +++ b/board/phytec/phycore_rk3288/phycore-rk3288.c @@ -11,6 +11,11 @@ #include #include #include +#include +#include +#include +#include +#include #include "som.h" static int valid_rk3288_som(struct rk3288_som *som) @@ -27,6 +32,15 @@ static int valid_rk3288_som(struct rk3288_som *som) return hw == som->bs; } +static void setup_iodomain(void) +{ + const u32 GRF_IO_VSEL_FLASH1_SHIFT = 3; + struct rk3288_grf *grf = + syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_FLASH1_SHIFT); +} + int rk_board_late_init(void) { int ret; @@ -34,6 +48,8 @@ int rk_board_late_init(void) struct rk3288_som opt; int off; + setup_iodomain(); + /* Get the identificatioin page of M24C32-D EEPROM */ off = fdt_path_offset(gd->fdt_blob, "eeprom0"); if (off < 0) { -- 2.7.4