[PATCH 00/14] clean up DPU for RM refactor

[PATCH 00/14] clean up DPU for RM refactor

[Jeykumar Sankaran]

Based on the comments received for the patch series[1] and to
make the review process easy a bit more easy, spliting up the 
patches for cleanup and resource manager refactor. This series 
cleans up and prepares the DPU for upcoming RM changes.

[1] https://patchwork.freedesktop.org/series/44669/

Thanks and Regards,
Jeykumar S.

Jeykumar Sankaran (14):
  drm/msm/dpu: remove debugfs support for misr
  drm/msm/dpu: remove scalar config definitions
  drm/msm/dpu: remove resource pool manager
  drm/msm/dpu: remove ping pong split topology variables
  drm/msm/dpu: enable master-slave encoders explicitly
  drm/msm/dpu: use kms stored hw mdp block
  drm/msm/dpu: iterate for assigned hw ctl in virtual encoder
  drm/msm/dpu: avoid querying for hw intf before assignment
  drm/msm/dpu: make crtc get_mixer_width helper static
  drm/msm/dpu: move hw resource tracking to crtc state
  drm/msm/dpu: rename hw_ctl to lm_ctl
  drm/msm/dpu: remove topology name
  drm/msm/dpu: remove display H_TILE from encoder
  drm/msm/dpu: remove cdm block support from resource manager

 drivers/gpu/drm/msm/Makefile                       |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c           | 449 +++------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h           | 111 +----
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        | 203 ++--------
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h        |   6 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |  20 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   |  31 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 116 +-----
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c         | 323 ---------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h         | 139 -------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c         |  14 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h         |   4 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c        |  29 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h        |   7 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c          |  29 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h          |   7 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c         |  18 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h         |  17 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c        |   3 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h        |  16 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c             | 107 +----
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h             |  24 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h          |   4 -
 23 files changed, 150 insertions(+), 1528 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h

-- 
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a Linux Foundation Collaborative Project

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[PATCH 01/14] drm/msm/dpu: remove debugfs support for misr

[Jeykumar Sankaran]

Strip down debugfs support for misr data read on layer mixers
and interfaces.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c           | 139 ---------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h           |   6 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        | 127 -------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   6 -
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  28 -----
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c        |  29 -----
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h        |   7 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c          |  29 -----
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h          |   7 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c        |   3 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h        |   6 -
 11 files changed, 387 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 07c2d15..a4fab042 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -47,8 +47,6 @@
 #define LEFT_MIXER 0
 #define RIGHT_MIXER 1
 
-#define MISR_BUFF_SIZE			256
-
 static inline struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
 {
 	struct msm_drm_private *priv;
@@ -1272,8 +1270,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg)
 	struct drm_crtc *crtc = arg;
 	struct dpu_crtc *dpu_crtc;
 	struct drm_encoder *encoder;
-	struct dpu_crtc_mixer *m;
-	u32 i, misr_status;
 
 	if (!crtc) {
 		DPU_ERROR("invalid crtc\n");
@@ -1294,29 +1290,8 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg)
 
 			dpu_encoder_virt_restore(encoder);
 		}
-
-		for (i = 0; i < dpu_crtc->num_mixers; ++i) {
-			m = &dpu_crtc->mixers[i];
-			if (!m->hw_lm || !m->hw_lm->ops.setup_misr ||
-					!dpu_crtc->misr_enable)
-				continue;
-
-			m->hw_lm->ops.setup_misr(m->hw_lm, true,
-					dpu_crtc->misr_frame_count);
-		}
 		break;
 	case DPU_POWER_EVENT_PRE_DISABLE:
-		for (i = 0; i < dpu_crtc->num_mixers; ++i) {
-			m = &dpu_crtc->mixers[i];
-			if (!m->hw_lm || !m->hw_lm->ops.collect_misr ||
-					!dpu_crtc->misr_enable)
-				continue;
-
-			misr_status = m->hw_lm->ops.collect_misr(m->hw_lm);
-			dpu_crtc->misr_data[i] = misr_status ? misr_status :
-							dpu_crtc->misr_data[i];
-		}
-		break;
 	case DPU_POWER_EVENT_POST_DISABLE:
 		/**
 		 * Nothing to do. All the planes on the CRTC will be
@@ -1847,113 +1822,6 @@ static int _dpu_debugfs_status_open(struct inode *inode, struct file *file)
 	return single_open(file, _dpu_debugfs_status_show, inode->i_private);
 }
 
-static ssize_t _dpu_crtc_misr_setup(struct file *file,
-		const char __user *user_buf, size_t count, loff_t *ppos)
-{
-	struct dpu_crtc *dpu_crtc;
-	struct dpu_crtc_mixer *m;
-	int i = 0, rc;
-	char buf[MISR_BUFF_SIZE + 1];
-	u32 frame_count, enable;
-	size_t buff_copy;
-
-	if (!file || !file->private_data)
-		return -EINVAL;
-
-	dpu_crtc = file->private_data;
-	buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
-	if (copy_from_user(buf, user_buf, buff_copy)) {
-		DPU_ERROR("buffer copy failed\n");
-		return -EINVAL;
-	}
-
-	buf[buff_copy] = 0; /* end of string */
-
-	if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
-		return -EINVAL;
-
-	rc = _dpu_crtc_power_enable(dpu_crtc, true);
-	if (rc)
-		return rc;
-
-	mutex_lock(&dpu_crtc->crtc_lock);
-	dpu_crtc->misr_enable = enable;
-	dpu_crtc->misr_frame_count = frame_count;
-	for (i = 0; i < dpu_crtc->num_mixers; ++i) {
-		dpu_crtc->misr_data[i] = 0;
-		m = &dpu_crtc->mixers[i];
-		if (!m->hw_lm || !m->hw_lm->ops.setup_misr)
-			continue;
-
-		m->hw_lm->ops.setup_misr(m->hw_lm, enable, frame_count);
-	}
-	mutex_unlock(&dpu_crtc->crtc_lock);
-	_dpu_crtc_power_enable(dpu_crtc, false);
-
-	return count;
-}
-
-static ssize_t _dpu_crtc_misr_read(struct file *file,
-		char __user *user_buff, size_t count, loff_t *ppos)
-{
-	struct dpu_crtc *dpu_crtc;
-	struct dpu_crtc_mixer *m;
-	int i = 0, rc;
-	u32 misr_status;
-	ssize_t len = 0;
-	char buf[MISR_BUFF_SIZE + 1] = {'\0'};
-
-	if (*ppos)
-		return 0;
-
-	if (!file || !file->private_data)
-		return -EINVAL;
-
-	dpu_crtc = file->private_data;
-	rc = _dpu_crtc_power_enable(dpu_crtc, true);
-	if (rc)
-		return rc;
-
-	mutex_lock(&dpu_crtc->crtc_lock);
-	if (!dpu_crtc->misr_enable) {
-		len += snprintf(buf + len, MISR_BUFF_SIZE - len,
-			"disabled\n");
-		goto buff_check;
-	}
-
-	for (i = 0; i < dpu_crtc->num_mixers; ++i) {
-		m = &dpu_crtc->mixers[i];
-		if (!m->hw_lm || !m->hw_lm->ops.collect_misr)
-			continue;
-
-		misr_status = m->hw_lm->ops.collect_misr(m->hw_lm);
-		dpu_crtc->misr_data[i] = misr_status ? misr_status :
-							dpu_crtc->misr_data[i];
-		len += snprintf(buf + len, MISR_BUFF_SIZE - len, "lm idx:%d\n",
-					m->hw_lm->idx - LM_0);
-		len += snprintf(buf + len, MISR_BUFF_SIZE - len, "0x%x\n",
-							dpu_crtc->misr_data[i]);
-	}
-
-buff_check:
-	if (count <= len) {
-		len = 0;
-		goto end;
-	}
-
-	if (copy_to_user(user_buff, buf, len)) {
-		len = -EFAULT;
-		goto end;
-	}
-
-	*ppos += len;   /* increase offset */
-
-end:
-	mutex_unlock(&dpu_crtc->crtc_lock);
-	_dpu_crtc_power_enable(dpu_crtc, false);
-	return len;
-}
-
 #define DEFINE_DPU_DEBUGFS_SEQ_FOPS(__prefix)                          \
 static int __prefix ## _open(struct inode *inode, struct file *file)	\
 {									\
@@ -2015,11 +1883,6 @@ static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc)
 		.llseek =	seq_lseek,
 		.release =	single_release,
 	};
-	static const struct file_operations debugfs_misr_fops = {
-		.open =		simple_open,
-		.read =		_dpu_crtc_misr_read,
-		.write =	_dpu_crtc_misr_setup,
-	};
 
 	if (!crtc)
 		return -EINVAL;
@@ -2042,8 +1905,6 @@ static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc)
 			dpu_crtc->debugfs_root,
 			&dpu_crtc->base,
 			&dpu_crtc_debugfs_state_fops);
-	debugfs_create_file("misr_data", 0600, dpu_crtc->debugfs_root,
-					dpu_crtc, &debugfs_misr_fops);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index a896791..53484b1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -156,9 +156,6 @@ struct dpu_crtc_frame_event {
  * @event_thread  : Pointer to event handler thread
  * @event_worker  : Event worker queue
  * @event_lock    : Spinlock around event handling code
- * @misr_enable   : boolean entry indicates misr enable/disable status.
- * @misr_frame_count  : misr frame count provided by client
- * @misr_data     : store misr data before turning off the clocks.
  * @phandle: Pointer to power handler
  * @power_event   : registered power event handle
  * @cur_perf      : current performance committed to clock/bandwidth driver
@@ -206,9 +203,6 @@ struct dpu_crtc {
 
 	/* for handling internal event thread */
 	spinlock_t event_lock;
-	bool misr_enable;
-	u32 misr_frame_count;
-	u32 misr_data[CRTC_DUAL_MIXERS];
 
 	struct dpu_power_handle *phandle;
 	struct dpu_power_event *power_event;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 5b0e944..991b22c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -65,8 +65,6 @@
 
 #define MAX_CHANNELS_PER_ENC 2
 
-#define MISR_BUFF_SIZE			256
-
 #define IDLE_SHORT_TIMEOUT	1
 
 #define MAX_VDISPLAY_SPLIT 1080
@@ -161,8 +159,6 @@ enum dpu_enc_rc_states {
  * @frame_done_timer:		watchdog timer for frame done event
  * @vsync_event_timer:		vsync timer
  * @disp_info:			local copy of msm_display_info struct
- * @misr_enable:		misr enable/disable status
- * @misr_frame_count:		misr frame count before start capturing the data
  * @idle_pc_supported:		indicate if idle power collaps is supported
  * @rc_lock:			resource control mutex lock to protect
  *				virt encoder over various state changes
@@ -202,8 +198,6 @@ struct dpu_encoder_virt {
 	struct timer_list vsync_event_timer;
 
 	struct msm_display_info disp_info;
-	bool misr_enable;
-	u32 misr_frame_count;
 
 	bool idle_pc_supported;
 	struct mutex rc_lock;
@@ -1193,11 +1187,6 @@ static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
 			if (phys->ops.enable)
 				phys->ops.enable(phys);
 		}
-
-		if (dpu_enc->misr_enable && (dpu_enc->disp_info.capabilities &
-		     MSM_DISPLAY_CAP_VID_MODE) && phys->ops.setup_misr)
-			phys->ops.setup_misr(phys, true,
-						dpu_enc->misr_frame_count);
 	}
 
 	if (dpu_enc->cur_master->ops.enable)
@@ -1949,113 +1938,6 @@ static int _dpu_encoder_debugfs_status_open(struct inode *inode,
 	return single_open(file, _dpu_encoder_status_show, inode->i_private);
 }
 
-static ssize_t _dpu_encoder_misr_setup(struct file *file,
-		const char __user *user_buf, size_t count, loff_t *ppos)
-{
-	struct dpu_encoder_virt *dpu_enc;
-	int i = 0, rc;
-	char buf[MISR_BUFF_SIZE + 1];
-	size_t buff_copy;
-	u32 frame_count, enable;
-
-	if (!file || !file->private_data)
-		return -EINVAL;
-
-	dpu_enc = file->private_data;
-
-	buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
-	if (copy_from_user(buf, user_buf, buff_copy))
-		return -EINVAL;
-
-	buf[buff_copy] = 0; /* end of string */
-
-	if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
-		return -EINVAL;
-
-	rc = _dpu_encoder_power_enable(dpu_enc, true);
-	if (rc)
-		return rc;
-
-	mutex_lock(&dpu_enc->enc_lock);
-	dpu_enc->misr_enable = enable;
-	dpu_enc->misr_frame_count = frame_count;
-	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
-		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
-
-		if (!phys || !phys->ops.setup_misr)
-			continue;
-
-		phys->ops.setup_misr(phys, enable, frame_count);
-	}
-	mutex_unlock(&dpu_enc->enc_lock);
-	_dpu_encoder_power_enable(dpu_enc, false);
-
-	return count;
-}
-
-static ssize_t _dpu_encoder_misr_read(struct file *file,
-		char __user *user_buff, size_t count, loff_t *ppos)
-{
-	struct dpu_encoder_virt *dpu_enc;
-	int i = 0, len = 0;
-	char buf[MISR_BUFF_SIZE + 1] = {'\0'};
-	int rc;
-
-	if (*ppos)
-		return 0;
-
-	if (!file || !file->private_data)
-		return -EINVAL;
-
-	dpu_enc = file->private_data;
-
-	rc = _dpu_encoder_power_enable(dpu_enc, true);
-	if (rc)
-		return rc;
-
-	mutex_lock(&dpu_enc->enc_lock);
-	if (!dpu_enc->misr_enable) {
-		len += snprintf(buf + len, MISR_BUFF_SIZE - len,
-			"disabled\n");
-		goto buff_check;
-	} else if (dpu_enc->disp_info.capabilities &
-						~MSM_DISPLAY_CAP_VID_MODE) {
-		len += snprintf(buf + len, MISR_BUFF_SIZE - len,
-			"unsupported\n");
-		goto buff_check;
-	}
-
-	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
-		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
-
-		if (!phys || !phys->ops.collect_misr)
-			continue;
-
-		len += snprintf(buf + len, MISR_BUFF_SIZE - len,
-			"Intf idx:%d\n", phys->intf_idx - INTF_0);
-		len += snprintf(buf + len, MISR_BUFF_SIZE - len, "0x%x\n",
-					phys->ops.collect_misr(phys));
-	}
-
-buff_check:
-	if (count <= len) {
-		len = 0;
-		goto end;
-	}
-
-	if (copy_to_user(user_buff, buf, len)) {
-		len = -EFAULT;
-		goto end;
-	}
-
-	*ppos += len;   /* increase offset */
-
-end:
-	mutex_unlock(&dpu_enc->enc_lock);
-	_dpu_encoder_power_enable(dpu_enc, false);
-	return len;
-}
-
 static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
 {
 	struct dpu_encoder_virt *dpu_enc;
@@ -2070,12 +1952,6 @@ static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
 		.release =	single_release,
 	};
 
-	static const struct file_operations debugfs_misr_fops = {
-		.open = simple_open,
-		.read = _dpu_encoder_misr_read,
-		.write = _dpu_encoder_misr_setup,
-	};
-
 	char name[DPU_NAME_SIZE];
 
 	if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
@@ -2099,9 +1975,6 @@ static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
 	debugfs_create_file("status", 0600,
 		dpu_enc->debugfs_root, dpu_enc, &debugfs_status_fops);
 
-	debugfs_create_file("misr_data", 0600,
-		dpu_enc->debugfs_root, dpu_enc, &debugfs_misr_fops);
-
 	for (i = 0; i < dpu_enc->num_phys_encs; i++)
 		if (dpu_enc->phys_encs[i] &&
 				dpu_enc->phys_encs[i]->ops.late_register)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index c7df8aa..b3917e0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -114,8 +114,6 @@ struct dpu_encoder_virt_ops {
  * @handle_post_kickoff:	Do any work necessary post-kickoff work
  * @trigger_start:		Process start event on physical encoder
  * @needs_single_flush:		Whether encoder slaves need to be flushed
- * @setup_misr:		Sets up MISR, enable and disables based on sysfs
- * @collect_misr:		Collects MISR data on frame update
  * @hw_reset:			Issue HW recovery such as CTL reset and clear
  *				DPU_ENC_ERR_NEEDS_HW_RESET state
  * @irq_control:		Handler to enable/disable all the encoder IRQs
@@ -154,10 +152,6 @@ struct dpu_encoder_phys_ops {
 	void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);
 	void (*trigger_start)(struct dpu_encoder_phys *phys_enc);
 	bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc);
-
-	void (*setup_misr)(struct dpu_encoder_phys *phys_encs,
-				bool enable, u32 frame_count);
-	u32 (*collect_misr)(struct dpu_encoder_phys *phys_enc);
 	void (*hw_reset)(struct dpu_encoder_phys *phys_enc);
 	void (*irq_control)(struct dpu_encoder_phys *phys, bool enable);
 	void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 14fc7c2..6fc3d3f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -756,32 +756,6 @@ static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc,
 	}
 }
 
-static void dpu_encoder_phys_vid_setup_misr(struct dpu_encoder_phys *phys_enc,
-						bool enable, u32 frame_count)
-{
-	struct dpu_encoder_phys_vid *vid_enc;
-
-	if (!phys_enc)
-		return;
-	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
-
-	if (vid_enc->hw_intf && vid_enc->hw_intf->ops.setup_misr)
-		vid_enc->hw_intf->ops.setup_misr(vid_enc->hw_intf,
-							enable, frame_count);
-}
-
-static u32 dpu_encoder_phys_vid_collect_misr(struct dpu_encoder_phys *phys_enc)
-{
-	struct dpu_encoder_phys_vid *vid_enc;
-
-	if (!phys_enc)
-		return 0;
-	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
-
-	return vid_enc->hw_intf && vid_enc->hw_intf->ops.collect_misr ?
-		vid_enc->hw_intf->ops.collect_misr(vid_enc->hw_intf) : 0;
-}
-
 static int dpu_encoder_phys_vid_get_line_count(
 		struct dpu_encoder_phys *phys_enc)
 {
@@ -817,8 +791,6 @@ static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops)
 	ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff;
 	ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff;
 	ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush;
-	ops->setup_misr = dpu_encoder_phys_vid_setup_misr;
-	ops->collect_misr = dpu_encoder_phys_vid_collect_misr;
 	ops->hw_reset = dpu_encoder_helper_hw_reset;
 	ops->get_line_count = dpu_encoder_phys_vid_get_line_count;
 }
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index d280df5..9c6bba0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -65,9 +65,6 @@
 #define   INTF_FRAME_COUNT              0x0AC
 #define   INTF_LINE_COUNT               0x0B0
 
-#define INTF_MISR_CTRL			0x180
-#define INTF_MISR_SIGNATURE		0x184
-
 static struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf,
 		struct dpu_mdss_cfg *m,
 		void __iomem *addr,
@@ -246,30 +243,6 @@ static void dpu_hw_intf_get_status(
 	}
 }
 
-static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf,
-						bool enable, u32 frame_count)
-{
-	struct dpu_hw_blk_reg_map *c = &intf->hw;
-	u32 config = 0;
-
-	DPU_REG_WRITE(c, INTF_MISR_CTRL, MISR_CTRL_STATUS_CLEAR);
-	/* clear misr data */
-	wmb();
-
-	if (enable)
-		config = (frame_count & MISR_FRAME_COUNT_MASK) |
-			MISR_CTRL_ENABLE | INTF_MISR_CTRL_FREE_RUN_MASK;
-
-	DPU_REG_WRITE(c, INTF_MISR_CTRL, config);
-}
-
-static u32 dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf)
-{
-	struct dpu_hw_blk_reg_map *c = &intf->hw;
-
-	return DPU_REG_READ(c, INTF_MISR_SIGNATURE);
-}
-
 static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf)
 {
 	struct dpu_hw_blk_reg_map *c;
@@ -289,8 +262,6 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
 	ops->setup_prg_fetch  = dpu_hw_intf_setup_prg_fetch;
 	ops->get_status = dpu_hw_intf_get_status;
 	ops->enable_timing = dpu_hw_intf_enable_timing_engine;
-	ops->setup_misr = dpu_hw_intf_setup_misr;
-	ops->collect_misr = dpu_hw_intf_collect_misr;
 	ops->get_line_count = dpu_hw_intf_get_line_count;
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index a79d735..3b77df4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -59,8 +59,6 @@ struct intf_status {
  * @ setup_prog_fetch : enables/disables the programmable fetch logic
  * @ enable_timing: enable/disable timing engine
  * @ get_status: returns if timing engine is enabled or not
- * @ setup_misr: enables/disables MISR in HW register
- * @ collect_misr: reads and stores MISR data from HW register
  * @ get_line_count: reads current vertical line counter
  */
 struct dpu_hw_intf_ops {
@@ -77,11 +75,6 @@ struct dpu_hw_intf_ops {
 	void (*get_status)(struct dpu_hw_intf *intf,
 			struct intf_status *status);
 
-	void (*setup_misr)(struct dpu_hw_intf *intf,
-			bool enable, u32 frame_count);
-
-	u32 (*collect_misr)(struct dpu_hw_intf *intf);
-
 	u32 (*get_line_count)(struct dpu_hw_intf *intf);
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index 4ab72b0..acb8dc8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -34,9 +34,6 @@
 #define LM_BLEND0_FG_ALPHA               0x04
 #define LM_BLEND0_BG_ALPHA               0x08
 
-#define LM_MISR_CTRL			0x310
-#define LM_MISR_SIGNATURE		0x314
-
 static struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer,
 		struct dpu_mdss_cfg *m,
 		void __iomem *addr,
@@ -171,30 +168,6 @@ static void dpu_hw_lm_gc(struct dpu_hw_mixer *mixer,
 {
 }
 
-static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx,
-				bool enable, u32 frame_count)
-{
-	struct dpu_hw_blk_reg_map *c = &ctx->hw;
-	u32 config = 0;
-
-	DPU_REG_WRITE(c, LM_MISR_CTRL, MISR_CTRL_STATUS_CLEAR);
-	/* clear misr data */
-	wmb();
-
-	if (enable)
-		config = (frame_count & MISR_FRAME_COUNT_MASK) |
-			MISR_CTRL_ENABLE | INTF_MISR_CTRL_FREE_RUN_MASK;
-
-	DPU_REG_WRITE(c, LM_MISR_CTRL, config);
-}
-
-static u32 dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx)
-{
-	struct dpu_hw_blk_reg_map *c = &ctx->hw;
-
-	return DPU_REG_READ(c, LM_MISR_SIGNATURE);
-}
-
 static void _setup_mixer_ops(struct dpu_mdss_cfg *m,
 		struct dpu_hw_lm_ops *ops,
 		unsigned long features)
@@ -207,8 +180,6 @@ static void _setup_mixer_ops(struct dpu_mdss_cfg *m,
 	ops->setup_alpha_out = dpu_hw_lm_setup_color3;
 	ops->setup_border_color = dpu_hw_lm_setup_border_color;
 	ops->setup_gc = dpu_hw_lm_gc;
-	ops->setup_misr = dpu_hw_lm_setup_misr;
-	ops->collect_misr = dpu_hw_lm_collect_misr;
 };
 
 static struct dpu_hw_blk_ops dpu_hw_ops = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
index e29e5da..5b036ac 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
@@ -66,13 +66,6 @@ struct dpu_hw_lm_ops {
 	 */
 	void (*setup_gc)(struct dpu_hw_mixer *mixer,
 			void *cfg);
-
-	/* setup_misr: enables/disables MISR in HW register */
-	void (*setup_misr)(struct dpu_hw_mixer *ctx,
-			bool enable, u32 frame_count);
-
-	/* collect_misr: reads and stores MISR data from HW register */
-	u32 (*collect_misr)(struct dpu_hw_mixer *ctx);
 };
 
 struct dpu_hw_mixer {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
index 4cabae4..cb5c017 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
@@ -50,9 +50,6 @@
 #define QSEED3_CLK_CTRL0                   0x54
 #define QSEED3_CLK_CTRL1                   0x58
 #define QSEED3_CLK_STATUS                  0x5C
-#define QSEED3_MISR_CTRL                   0x70
-#define QSEED3_MISR_SIGNATURE_0            0x74
-#define QSEED3_MISR_SIGNATURE_1            0x78
 #define QSEED3_PHASE_INIT_Y_H              0x90
 #define QSEED3_PHASE_INIT_Y_V              0x94
 #define QSEED3_PHASE_INIT_UV_H             0x98
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index 1240f50..cb02041 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -325,12 +325,6 @@ void dpu_reg_write(struct dpu_hw_blk_reg_map *c,
 #define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off)
 #define DPU_REG_READ(c, off) dpu_reg_read(c, off)
 
-#define MISR_FRAME_COUNT_MASK		0xFF
-#define MISR_CTRL_ENABLE		BIT(8)
-#define MISR_CTRL_STATUS		BIT(9)
-#define MISR_CTRL_STATUS_CLEAR		BIT(10)
-#define INTF_MISR_CTRL_FREE_RUN_MASK	BIT(31)
-
 void *dpu_hw_util_get_dir(void);
 
 void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
-- 
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a Linux Foundation Collaborative Project

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[PATCH 02/14] drm/msm/dpu: remove scalar config definitions

[Jeykumar Sankaran]

cleans up left out scalar config definitions from headers

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h    |  2 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 10 ----------
 2 files changed, 12 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 53484b1..34ce724 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -161,7 +161,6 @@ struct dpu_crtc_frame_event {
  * @cur_perf      : current performance committed to clock/bandwidth driver
  * @rp_lock       : serialization lock for resource pool
  * @rp_head       : list of active resource pool
- * @scl3_cfg_lut  : qseed3 lut config
  */
 struct dpu_crtc {
 	struct drm_crtc base;
@@ -172,7 +171,6 @@ struct dpu_crtc {
 	u32 num_mixers;
 	bool mixers_swapped;
 	struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
-	struct dpu_hw_scaler3_lut_cfg *scl3_lut_cfg;
 
 	struct drm_pending_vblank_event *event;
 	u32 vsync_count;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index cb02041..321fc64 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -148,16 +148,6 @@ struct dpu_hw_scaler3_cfg {
 	struct dpu_hw_scaler3_de_cfg de;
 };
 
-struct dpu_hw_scaler3_lut_cfg {
-	bool is_configured;
-	u32 *dir_lut;
-	size_t dir_len;
-	u32 *cir_lut;
-	size_t cir_len;
-	u32 *sep_lut;
-	size_t sep_len;
-};
-
 /**
  * struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure
  * @num_ext_pxls_lr: Number of total horizontal pixels
-- 
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[PATCH 03/14] drm/msm/dpu: remove resource pool manager

[Jeykumar Sankaran]

resource pool manager utility was introduced to manage
rotator sessions. Removing the support as the rotator
feature doesn't exist.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Reviewed-by: Sean Paul <seanpaul@chromium.org>

---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 205 -------------------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |  56 ---------
 2 files changed, 261 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index a4fab042..92eda3e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -97,187 +97,6 @@ static inline int _dpu_crtc_power_enable(struct dpu_crtc *dpu_crtc, bool enable)
 	return 0;
 }
 
-/**
- * _dpu_crtc_rp_to_crtc - get crtc from resource pool object
- * @rp: Pointer to resource pool
- * return: Pointer to drm crtc if success; null otherwise
- */
-static struct drm_crtc *_dpu_crtc_rp_to_crtc(struct dpu_crtc_respool *rp)
-{
-	if (!rp)
-		return NULL;
-
-	return container_of(rp, struct dpu_crtc_state, rp)->base.crtc;
-}
-
-/**
- * _dpu_crtc_rp_reclaim - reclaim unused, or all if forced, resources in pool
- * @rp: Pointer to resource pool
- * @force: True to reclaim all resources; otherwise, reclaim only unused ones
- * return: None
- */
-static void _dpu_crtc_rp_reclaim(struct dpu_crtc_respool *rp, bool force)
-{
-	struct dpu_crtc_res *res, *next;
-	struct drm_crtc *crtc;
-
-	crtc = _dpu_crtc_rp_to_crtc(rp);
-	if (!crtc) {
-		DPU_ERROR("invalid crtc\n");
-		return;
-	}
-
-	DPU_DEBUG("crtc%d.%u %s\n", crtc->base.id, rp->sequence_id,
-			force ? "destroy" : "free_unused");
-
-	list_for_each_entry_safe(res, next, &rp->res_list, list) {
-		if (!force && !(res->flags & DPU_CRTC_RES_FLAG_FREE))
-			continue;
-		DPU_DEBUG("crtc%d.%u reclaim res:0x%x/0x%llx/%pK/%d\n",
-				crtc->base.id, rp->sequence_id,
-				res->type, res->tag, res->val,
-				atomic_read(&res->refcount));
-		list_del(&res->list);
-		if (res->ops.put)
-			res->ops.put(res->val);
-		kfree(res);
-	}
-}
-
-/**
- * _dpu_crtc_rp_free_unused - free unused resource in pool
- * @rp: Pointer to resource pool
- * return: none
- */
-static void _dpu_crtc_rp_free_unused(struct dpu_crtc_respool *rp)
-{
-	mutex_lock(rp->rp_lock);
-	_dpu_crtc_rp_reclaim(rp, false);
-	mutex_unlock(rp->rp_lock);
-}
-
-/**
- * _dpu_crtc_rp_destroy - destroy resource pool
- * @rp: Pointer to resource pool
- * return: None
- */
-static void _dpu_crtc_rp_destroy(struct dpu_crtc_respool *rp)
-{
-	mutex_lock(rp->rp_lock);
-	list_del_init(&rp->rp_list);
-	_dpu_crtc_rp_reclaim(rp, true);
-	mutex_unlock(rp->rp_lock);
-}
-
-/**
- * _dpu_crtc_hw_blk_get - get callback for hardware block
- * @val: Resource handle
- * @type: Resource type
- * @tag: Search tag for given resource
- * return: Resource handle
- */
-static void *_dpu_crtc_hw_blk_get(void *val, u32 type, u64 tag)
-{
-	DPU_DEBUG("res:%d/0x%llx/%pK\n", type, tag, val);
-	return dpu_hw_blk_get(val, type, tag);
-}
-
-/**
- * _dpu_crtc_hw_blk_put - put callback for hardware block
- * @val: Resource handle
- * return: None
- */
-static void _dpu_crtc_hw_blk_put(void *val)
-{
-	DPU_DEBUG("res://%pK\n", val);
-	dpu_hw_blk_put(val);
-}
-
-/**
- * _dpu_crtc_rp_duplicate - duplicate resource pool and reset reference count
- * @rp: Pointer to original resource pool
- * @dup_rp: Pointer to duplicated resource pool
- * return: None
- */
-static void _dpu_crtc_rp_duplicate(struct dpu_crtc_respool *rp,
-		struct dpu_crtc_respool *dup_rp)
-{
-	struct dpu_crtc_res *res, *dup_res;
-	struct drm_crtc *crtc;
-
-	if (!rp || !dup_rp || !rp->rp_head) {
-		DPU_ERROR("invalid resource pool\n");
-		return;
-	}
-
-	crtc = _dpu_crtc_rp_to_crtc(rp);
-	if (!crtc) {
-		DPU_ERROR("invalid crtc\n");
-		return;
-	}
-
-	DPU_DEBUG("crtc%d.%u duplicate\n", crtc->base.id, rp->sequence_id);
-
-	mutex_lock(rp->rp_lock);
-	dup_rp->sequence_id = rp->sequence_id + 1;
-	INIT_LIST_HEAD(&dup_rp->res_list);
-	dup_rp->ops = rp->ops;
-	list_for_each_entry(res, &rp->res_list, list) {
-		dup_res = kzalloc(sizeof(struct dpu_crtc_res), GFP_KERNEL);
-		if (!dup_res) {
-			mutex_unlock(rp->rp_lock);
-			return;
-		}
-		INIT_LIST_HEAD(&dup_res->list);
-		atomic_set(&dup_res->refcount, 0);
-		dup_res->type = res->type;
-		dup_res->tag = res->tag;
-		dup_res->val = res->val;
-		dup_res->ops = res->ops;
-		dup_res->flags = DPU_CRTC_RES_FLAG_FREE;
-		DPU_DEBUG("crtc%d.%u dup res:0x%x/0x%llx/%pK/%d\n",
-				crtc->base.id, dup_rp->sequence_id,
-				dup_res->type, dup_res->tag, dup_res->val,
-				atomic_read(&dup_res->refcount));
-		list_add_tail(&dup_res->list, &dup_rp->res_list);
-		if (dup_res->ops.get)
-			dup_res->ops.get(dup_res->val, 0, -1);
-	}
-
-	dup_rp->rp_lock = rp->rp_lock;
-	dup_rp->rp_head = rp->rp_head;
-	INIT_LIST_HEAD(&dup_rp->rp_list);
-	list_add_tail(&dup_rp->rp_list, rp->rp_head);
-	mutex_unlock(rp->rp_lock);
-}
-
-/**
- * _dpu_crtc_rp_reset - reset resource pool after allocation
- * @rp: Pointer to original resource pool
- * @rp_lock: Pointer to serialization resource pool lock
- * @rp_head: Pointer to crtc resource pool head
- * return: None
- */
-static void _dpu_crtc_rp_reset(struct dpu_crtc_respool *rp,
-		struct mutex *rp_lock, struct list_head *rp_head)
-{
-	if (!rp || !rp_lock || !rp_head) {
-		DPU_ERROR("invalid resource pool\n");
-		return;
-	}
-
-	mutex_lock(rp_lock);
-	rp->rp_lock = rp_lock;
-	rp->rp_head = rp_head;
-	INIT_LIST_HEAD(&rp->rp_list);
-	rp->sequence_id = 0;
-	INIT_LIST_HEAD(&rp->res_list);
-	rp->ops.get = _dpu_crtc_hw_blk_get;
-	rp->ops.put = _dpu_crtc_hw_blk_put;
-	list_add_tail(&rp->rp_list, rp->rp_head);
-	mutex_unlock(rp_lock);
-}
-
 static void dpu_crtc_destroy(struct drm_crtc *crtc)
 {
 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
@@ -965,8 +784,6 @@ static void dpu_crtc_destroy_state(struct drm_crtc *crtc,
 
 	DPU_DEBUG("crtc%d\n", crtc->base.id);
 
-	_dpu_crtc_rp_destroy(&cstate->rp);
-
 	__drm_atomic_helper_crtc_destroy_state(state);
 
 	kfree(cstate);
@@ -1220,8 +1037,6 @@ static struct drm_crtc_state *dpu_crtc_duplicate_state(struct drm_crtc *crtc)
 	/* duplicate base helper */
 	__drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base);
 
-	_dpu_crtc_rp_duplicate(&old_cstate->rp, &cstate->rp);
-
 	return &cstate->base;
 }
 
@@ -1258,9 +1073,6 @@ static void dpu_crtc_reset(struct drm_crtc *crtc)
 		return;
 	}
 
-	_dpu_crtc_rp_reset(&cstate->rp, &dpu_crtc->rp_lock,
-			&dpu_crtc->rp_head);
-
 	cstate->base.crtc = crtc;
 	crtc->state = &cstate->base;
 }
@@ -1670,7 +1482,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 	}
 
 end:
-	_dpu_crtc_rp_free_unused(&cstate->rp);
 	kfree(pstates);
 	return rc;
 }
@@ -1839,8 +1650,6 @@ static int dpu_crtc_debugfs_state_show(struct seq_file *s, void *v)
 {
 	struct drm_crtc *crtc = (struct drm_crtc *) s->private;
 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
-	struct dpu_crtc_res *res;
-	struct dpu_crtc_respool *rp;
 	int i;
 
 	seq_printf(s, "client type: %d\n", dpu_crtc_get_client_type(crtc));
@@ -1857,17 +1666,6 @@ static int dpu_crtc_debugfs_state_show(struct seq_file *s, void *v)
 				dpu_crtc->cur_perf.max_per_pipe_ib[i]);
 	}
 
-	mutex_lock(&dpu_crtc->rp_lock);
-	list_for_each_entry(rp, &dpu_crtc->rp_head, rp_list) {
-		seq_printf(s, "rp.%d: ", rp->sequence_id);
-		list_for_each_entry(res, &rp->res_list, list)
-			seq_printf(s, "0x%x/0x%llx/%pK/%d ",
-					res->type, res->tag, res->val,
-					atomic_read(&res->refcount));
-		seq_puts(s, "\n");
-	}
-	mutex_unlock(&dpu_crtc->rp_lock);
-
 	return 0;
 }
 DEFINE_DPU_DEBUGFS_SEQ_FOPS(dpu_crtc_debugfs_state);
@@ -1982,9 +1780,6 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
 	spin_lock_init(&dpu_crtc->spin_lock);
 	atomic_set(&dpu_crtc->frame_pending, 0);
 
-	mutex_init(&dpu_crtc->rp_lock);
-	INIT_LIST_HEAD(&dpu_crtc->rp_head);
-
 	init_completion(&dpu_crtc->frame_done_comp);
 
 	INIT_LIST_HEAD(&dpu_crtc->frame_event_list);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 34ce724..5498c00 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -159,8 +159,6 @@ struct dpu_crtc_frame_event {
  * @phandle: Pointer to power handler
  * @power_event   : registered power event handle
  * @cur_perf      : current performance committed to clock/bandwidth driver
- * @rp_lock       : serialization lock for resource pool
- * @rp_head       : list of active resource pool
  */
 struct dpu_crtc {
 	struct drm_crtc base;
@@ -207,65 +205,12 @@ struct dpu_crtc {
 
 	struct dpu_core_perf_params cur_perf;
 
-	struct mutex rp_lock;
-	struct list_head rp_head;
-
 	struct dpu_crtc_smmu_state_data smmu_state;
 };
 
 #define to_dpu_crtc(x) container_of(x, struct dpu_crtc, base)
 
 /**
- * struct dpu_crtc_res_ops - common operations for crtc resources
- * @get: get given resource
- * @put: put given resource
- */
-struct dpu_crtc_res_ops {
-	void *(*get)(void *val, u32 type, u64 tag);
-	void (*put)(void *val);
-};
-
-#define DPU_CRTC_RES_FLAG_FREE		BIT(0)
-
-/**
- * struct dpu_crtc_res - definition of crtc resources
- * @list: list of crtc resource
- * @type: crtc resource type
- * @tag: unique identifier per type
- * @refcount: reference/usage count
- * @ops: callback operations
- * @val: resource handle associated with type/tag
- * @flags: customization flags
- */
-struct dpu_crtc_res {
-	struct list_head list;
-	u32 type;
-	u64 tag;
-	atomic_t refcount;
-	struct dpu_crtc_res_ops ops;
-	void *val;
-	u32 flags;
-};
-
-/**
- * dpu_crtc_respool - crtc resource pool
- * @rp_lock: pointer to serialization lock
- * @rp_head: pointer to head of active resource pools of this crtc
- * @rp_list: list of crtc resource pool
- * @sequence_id: sequence identifier, incremented per state duplication
- * @res_list: list of resource managed by this resource pool
- * @ops: resource operations for parent resource pool
- */
-struct dpu_crtc_respool {
-	struct mutex *rp_lock;
-	struct list_head *rp_head;
-	struct list_head rp_list;
-	u32 sequence_id;
-	struct list_head res_list;
-	struct dpu_crtc_res_ops ops;
-};
-
-/**
  * struct dpu_crtc_state - dpu container for atomic crtc state
  * @base: Base drm crtc state structure
  * @is_ppsplit    : Whether current topology requires PPSplit special handling
@@ -290,7 +235,6 @@ struct dpu_crtc_state {
 	uint64_t input_fence_timeout_ns;
 
 	struct dpu_core_perf_params new_perf;
-	struct dpu_crtc_respool rp;
 };
 
 #define to_dpu_crtc_state(x) \
-- 
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[PATCH 04/14] drm/msm/dpu: remove ping pong split topology variables

[Jeykumar Sankaran]

removes left out variables of previous ping pong
split topology cleanup.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 5498c00..ec9c538 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -213,7 +213,6 @@ struct dpu_crtc {
 /**
  * struct dpu_crtc_state - dpu container for atomic crtc state
  * @base: Base drm crtc state structure
- * @is_ppsplit    : Whether current topology requires PPSplit special handling
  * @bw_control    : true if bw/clk controlled by core bw/clk properties
  * @bw_split_vote : true if bw controlled by llcc/dram bw properties
  * @lm_bounds     : LM boundaries based on current mode full resolution, no ROI.
@@ -228,8 +227,6 @@ struct dpu_crtc_state {
 
 	bool bw_control;
 	bool bw_split_vote;
-
-	bool is_ppsplit;
 	struct drm_rect lm_bounds[CRTC_DUAL_MIXERS];
 
 	uint64_t input_fence_timeout_ns;
-- 
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[PATCH 05/14] drm/msm/dpu: enable master-slave encoders explicitly

[Jeykumar Sankaran]

Identify slave-master encoders during initialization and enable
the encoders explicitly as the current logic has redundant and
ambiguous loops.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 46 ++++++++++-------------------
 1 file changed, 15 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 991b22c..b223bd2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -180,6 +180,7 @@ struct dpu_encoder_virt {
 	unsigned int num_phys_encs;
 	struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
 	struct dpu_encoder_phys *cur_master;
+	struct dpu_encoder_phys *cur_slave;
 	struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
 
 	bool intfs_swapped;
@@ -1141,7 +1142,8 @@ void dpu_encoder_virt_restore(struct drm_encoder *drm_enc)
 static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
 {
 	struct dpu_encoder_virt *dpu_enc = NULL;
-	int i, ret = 0;
+	struct dpu_encoder_phys *phys  = NULL;
+	int ret = 0;
 	struct drm_display_mode *cur_mode = NULL;
 
 	if (!drm_enc) {
@@ -1154,21 +1156,14 @@ static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
 	trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
 			     cur_mode->vdisplay);
 
-	dpu_enc->cur_master = NULL;
-	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
-		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
+	/* always enable slave encoder before master */
+	phys = dpu_enc->cur_slave;
+	if (phys && phys->ops.enable)
+		phys->ops.enable(phys);
 
-		if (phys && phys->ops.is_master && phys->ops.is_master(phys)) {
-			DPU_DEBUG_ENC(dpu_enc, "master is now idx %d\n", i);
-			dpu_enc->cur_master = phys;
-			break;
-		}
-	}
-
-	if (!dpu_enc->cur_master) {
-		DPU_ERROR("virt encoder has no master! num_phys %d\n", i);
-		return;
-	}
+	phys = dpu_enc->cur_master;
+	if (phys && phys->ops.enable)
+		phys->ops.enable(phys);
 
 	ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
 	if (ret) {
@@ -1177,21 +1172,6 @@ static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
 		return;
 	}
 
-	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
-		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
-
-		if (!phys)
-			continue;
-
-		if (phys != dpu_enc->cur_master) {
-			if (phys->ops.enable)
-				phys->ops.enable(phys);
-		}
-	}
-
-	if (dpu_enc->cur_master->ops.enable)
-		dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
-
 	_dpu_encoder_virt_enable_helper(drm_enc);
 }
 
@@ -2062,6 +2042,11 @@ static int dpu_encoder_virt_add_phys_encs(
 		++dpu_enc->num_phys_encs;
 	}
 
+	if (params->split_role == ENC_ROLE_SLAVE)
+		dpu_enc->cur_slave = enc;
+	else
+		dpu_enc->cur_master = enc;
+
 	return 0;
 }
 
@@ -2228,7 +2213,6 @@ int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc,
 	if (ret)
 		goto fail;
 
-	dpu_enc->cur_master = NULL;
 	spin_lock_init(&dpu_enc->enc_spinlock);
 
 	atomic_set(&dpu_enc->frame_done_timeout, 0);
-- 
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[PATCH 06/14] drm/msm/dpu: use kms stored hw mdp block

[Jeykumar Sankaran]

Avoid querying RM for hw mdp block. Use the one
stored in KMS during initialization.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 12 +-----------
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c |  9 +--------
 2 files changed, 2 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 3084675..c8c4612 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -823,7 +823,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
 {
 	struct dpu_encoder_phys *phys_enc = NULL;
 	struct dpu_encoder_phys_cmd *cmd_enc = NULL;
-	struct dpu_hw_mdp *hw_mdp;
 	struct dpu_encoder_irq *irq;
 	int i, ret = 0;
 
@@ -836,14 +835,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
 		goto fail;
 	}
 	phys_enc = &cmd_enc->base;
-
-	hw_mdp = dpu_rm_get_mdp(&p->dpu_kms->rm);
-	if (IS_ERR_OR_NULL(hw_mdp)) {
-		ret = PTR_ERR(hw_mdp);
-		DPU_ERROR("failed to get mdptop\n");
-		goto fail_mdp_init;
-	}
-	phys_enc->hw_mdptop = hw_mdp;
+	phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
 	phys_enc->intf_idx = p->intf_idx;
 
 	dpu_encoder_phys_cmd_init_ops(&phys_enc->ops);
@@ -898,8 +890,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
 
 	return phys_enc;
 
-fail_mdp_init:
-	kfree(cmd_enc);
 fail:
 	return ERR_PTR(ret);
 }
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 6fc3d3f..ecb8c65 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -801,7 +801,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
 	struct dpu_encoder_phys *phys_enc = NULL;
 	struct dpu_encoder_phys_vid *vid_enc = NULL;
 	struct dpu_rm_hw_iter iter;
-	struct dpu_hw_mdp *hw_mdp;
 	struct dpu_encoder_irq *irq;
 	int i, ret = 0;
 
@@ -818,13 +817,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
 
 	phys_enc = &vid_enc->base;
 
-	hw_mdp = dpu_rm_get_mdp(&p->dpu_kms->rm);
-	if (IS_ERR_OR_NULL(hw_mdp)) {
-		ret = PTR_ERR(hw_mdp);
-		DPU_ERROR("failed to get mdptop\n");
-		goto fail;
-	}
-	phys_enc->hw_mdptop = hw_mdp;
+	phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
 	phys_enc->intf_idx = p->intf_idx;
 
 	/**
-- 
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[PATCH 07/14] drm/msm/dpu: iterate for assigned hw ctl in virtual encoder

[Jeykumar Sankaran]

Instead of iterating for hw ctrl per physical encoder, this
patch moves the iterations and assignment to the virtual encoder.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        | 22 +++++++++++++++++++---
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   | 19 -------------------
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 19 -------------------
 3 files changed, 19 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index b223bd2..dbf669e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1011,9 +1011,10 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 	struct dpu_kms *dpu_kms;
 	struct list_head *connector_list;
 	struct drm_connector *conn = NULL, *conn_iter;
-	struct dpu_rm_hw_iter pp_iter;
+	struct dpu_rm_hw_iter pp_iter, ctl_iter;
 	struct msm_display_topology topology;
 	enum dpu_rm_topology_name topology_name;
+	struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL };
 	int i = 0, ret;
 
 	if (!drm_enc) {
@@ -1061,17 +1062,32 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 		dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) pp_iter.hw;
 	}
 
+	dpu_rm_init_hw_iter(&ctl_iter, drm_enc->base.id, DPU_HW_BLK_CTL);
+	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
+		if (!dpu_rm_get_hw(&dpu_kms->rm, &ctl_iter))
+			break;
+		hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw;
+	}
+
 	topology_name = dpu_rm_get_topology_name(topology);
 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 
 		if (phys) {
 			if (!dpu_enc->hw_pp[i]) {
-				DPU_ERROR_ENC(dpu_enc,
-				    "invalid pingpong block for the encoder\n");
+				DPU_ERROR_ENC(dpu_enc, "no pp block assigned"
+					     "at idx: %d\n", i);
 				return;
 			}
 			phys->hw_pp = dpu_enc->hw_pp[i];
+
+			if (!hw_ctl[i]) {
+				DPU_ERROR_ENC(dpu_enc, "no ctl block assigned"
+					     "at idx: %d\n", i);
+				return;
+			}
+			phys->hw_ctl = hw_ctl[i];
+
 			phys->connector = conn->state->connector;
 			phys->topology_name = topology_name;
 			if (phys->ops.mode_set)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index c8c4612..5c89868 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -196,9 +196,6 @@ static void dpu_encoder_phys_cmd_mode_set(
 {
 	struct dpu_encoder_phys_cmd *cmd_enc =
 		to_dpu_encoder_phys_cmd(phys_enc);
-	struct dpu_rm *rm = &phys_enc->dpu_kms->rm;
-	struct dpu_rm_hw_iter iter;
-	int i, instance;
 
 	if (!phys_enc || !mode || !adj_mode) {
 		DPU_ERROR("invalid args\n");
@@ -208,22 +205,6 @@ static void dpu_encoder_phys_cmd_mode_set(
 	DPU_DEBUG_CMDENC(cmd_enc, "caching mode:\n");
 	drm_mode_debug_printmodeline(adj_mode);
 
-	instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0;
-
-	/* Retrieve previously allocated HW Resources. Shouldn't fail */
-	dpu_rm_init_hw_iter(&iter, phys_enc->parent->base.id, DPU_HW_BLK_CTL);
-	for (i = 0; i <= instance; i++) {
-		if (dpu_rm_get_hw(rm, &iter))
-			phys_enc->hw_ctl = (struct dpu_hw_ctl *)iter.hw;
-	}
-
-	if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
-		DPU_ERROR_CMDENC(cmd_enc, "failed to init ctl: %ld\n",
-				PTR_ERR(phys_enc->hw_ctl));
-		phys_enc->hw_ctl = NULL;
-		return;
-	}
-
 	_dpu_encoder_phys_cmd_setup_irq_hw_idx(phys_enc);
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index ecb8c65..ca0963c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -395,9 +395,6 @@ static void dpu_encoder_phys_vid_mode_set(
 		struct drm_display_mode *mode,
 		struct drm_display_mode *adj_mode)
 {
-	struct dpu_rm *rm;
-	struct dpu_rm_hw_iter iter;
-	int i, instance;
 	struct dpu_encoder_phys_vid *vid_enc;
 
 	if (!phys_enc || !phys_enc->dpu_kms) {
@@ -405,7 +402,6 @@ static void dpu_encoder_phys_vid_mode_set(
 		return;
 	}
 
-	rm = &phys_enc->dpu_kms->rm;
 	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
 
 	if (adj_mode) {
@@ -414,21 +410,6 @@ static void dpu_encoder_phys_vid_mode_set(
 		DPU_DEBUG_VIDENC(vid_enc, "caching mode:\n");
 	}
 
-	instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0;
-
-	/* Retrieve previously allocated HW Resources. Shouldn't fail */
-	dpu_rm_init_hw_iter(&iter, phys_enc->parent->base.id, DPU_HW_BLK_CTL);
-	for (i = 0; i <= instance; i++) {
-		if (dpu_rm_get_hw(rm, &iter))
-			phys_enc->hw_ctl = (struct dpu_hw_ctl *)iter.hw;
-	}
-	if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
-		DPU_ERROR_VIDENC(vid_enc, "failed to init ctl, %ld\n",
-				PTR_ERR(phys_enc->hw_ctl));
-		phys_enc->hw_ctl = NULL;
-		return;
-	}
-
 	_dpu_encoder_phys_vid_setup_irq_hw_idx(phys_enc);
 }
 
-- 
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[PATCH 08/14] drm/msm/dpu: avoid querying for hw intf before assignment

[Jeykumar Sankaran]

Resource manager assigns hw_intf blocks for the encoder only on
modeset. If queried for hw_intf objects during init, it will be
NULL. Since hw_intf objects are needed only during encoder enable,
defer the query to encoder enable which will be triggered after
modeset.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 53 +++++++---------------
 1 file changed, 16 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index ca0963c..6de13f4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -462,7 +462,7 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
 {
 	struct msm_drm_private *priv;
 	struct dpu_encoder_phys_vid *vid_enc;
-	struct dpu_hw_intf *intf;
+	struct dpu_rm_hw_iter iter;
 	struct dpu_hw_ctl *ctl;
 	u32 flush_mask = 0;
 
@@ -474,11 +474,20 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
 	priv = phys_enc->parent->dev->dev_private;
 
 	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
-	intf = vid_enc->hw_intf;
 	ctl = phys_enc->hw_ctl;
-	if (!vid_enc->hw_intf || !phys_enc->hw_ctl) {
-		DPU_ERROR("invalid hw_intf %d hw_ctl %d\n",
-				vid_enc->hw_intf != 0, phys_enc->hw_ctl != 0);
+
+	dpu_rm_init_hw_iter(&iter, phys_enc->parent->base.id, DPU_HW_BLK_INTF);
+	while (dpu_rm_get_hw(&phys_enc->dpu_kms->rm, &iter)) {
+		struct dpu_hw_intf *hw_intf = (struct dpu_hw_intf *)iter.hw;
+
+		if (hw_intf->idx == phys_enc->intf_idx) {
+			vid_enc->hw_intf = hw_intf;
+			break;
+		}
+	}
+
+	if (!vid_enc->hw_intf) {
+		DPU_ERROR("hw_intf not assigned\n");
 		return;
 	}
 
@@ -500,7 +509,7 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
 		!dpu_encoder_phys_vid_is_master(phys_enc))
 		goto skip_flush;
 
-	ctl->ops.get_bitmask_intf(ctl, &flush_mask, intf->idx);
+	ctl->ops.get_bitmask_intf(ctl, &flush_mask, vid_enc->hw_intf->idx);
 	ctl->ops.update_pending_flush(ctl, flush_mask);
 
 skip_flush:
@@ -531,22 +540,13 @@ static void dpu_encoder_phys_vid_get_hw_resources(
 		struct dpu_encoder_hw_resources *hw_res,
 		struct drm_connector_state *conn_state)
 {
-	struct dpu_encoder_phys_vid *vid_enc;
-
 	if (!phys_enc || !hw_res) {
 		DPU_ERROR("invalid arg(s), enc %d hw_res %d conn_state %d\n",
 				phys_enc != 0, hw_res != 0, conn_state != 0);
 		return;
 	}
 
-	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
-	if (!vid_enc->hw_intf) {
-		DPU_ERROR("invalid arg(s), hw_intf\n");
-		return;
-	}
-
-	DPU_DEBUG_VIDENC(vid_enc, "\n");
-	hw_res->intfs[vid_enc->hw_intf->idx - INTF_0] = INTF_MODE_VIDEO;
+	hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_VIDEO;
 }
 
 static int _dpu_encoder_phys_vid_wait_for_vblank(
@@ -781,7 +781,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
 {
 	struct dpu_encoder_phys *phys_enc = NULL;
 	struct dpu_encoder_phys_vid *vid_enc = NULL;
-	struct dpu_rm_hw_iter iter;
 	struct dpu_encoder_irq *irq;
 	int i, ret = 0;
 
@@ -801,26 +800,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
 	phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
 	phys_enc->intf_idx = p->intf_idx;
 
-	/**
-	 * hw_intf resource permanently assigned to this encoder
-	 * Other resources allocated at atomic commit time by use case
-	 */
-	dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_INTF);
-	while (dpu_rm_get_hw(&p->dpu_kms->rm, &iter)) {
-		struct dpu_hw_intf *hw_intf = (struct dpu_hw_intf *)iter.hw;
-
-		if (hw_intf->idx == p->intf_idx) {
-			vid_enc->hw_intf = hw_intf;
-			break;
-		}
-	}
-
-	if (!vid_enc->hw_intf) {
-		ret = -EINVAL;
-		DPU_ERROR("failed to get hw_intf\n");
-		goto fail;
-	}
-
 	DPU_DEBUG_VIDENC(vid_enc, "\n");
 
 	dpu_encoder_phys_vid_init_ops(&phys_enc->ops);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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[PATCH 09/14] drm/msm/dpu: make crtc get_mixer_width helper static

[Jeykumar Sankaran]

Mark CRTC get_mixer_width helper API static as it is
not used outside the file.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 21 ++++++++++++++++++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 18 ------------------
 2 files changed, 18 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 92eda3e..e061847 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -47,6 +47,20 @@
 #define LEFT_MIXER 0
 #define RIGHT_MIXER 1
 
+static inline int _dpu_crtc_get_mixer_width(struct dpu_crtc *dpu_crtc,
+	struct dpu_crtc_state *cstate, struct drm_display_mode *mode)
+{
+	u32 mixer_width;
+
+	if (!dpu_crtc || !cstate || !mode)
+		return 0;
+
+	mixer_width = (cstate->num_mixers == CRTC_DUAL_MIXERS ?
+			mode->hdisplay / CRTC_DUAL_MIXERS : mode->hdisplay);
+
+	return mixer_width;
+}
+
 static inline struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
 {
 	struct msm_drm_private *priv;
@@ -601,7 +615,8 @@ static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
 	cstate = to_dpu_crtc_state(state);
 
 	adj_mode = &state->adjusted_mode;
-	crtc_split_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, adj_mode);
+	crtc_split_width = _dpu_crtc_get_mixer_width(dpu_crtc, cstate,
+						    adj_mode);
 
 	for (i = 0; i < dpu_crtc->num_mixers; i++) {
 		struct drm_rect *r = &cstate->lm_bounds[i];
@@ -1299,7 +1314,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 
 	memset(pipe_staged, 0, sizeof(pipe_staged));
 
-	mixer_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
+	mixer_width = _dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
 
 	_dpu_crtc_setup_lm_bounds(crtc, state);
 
@@ -1536,7 +1551,7 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
 
 	mutex_lock(&dpu_crtc->crtc_lock);
 	mode = &crtc->state->adjusted_mode;
-	out_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
+	out_width = _dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
 
 	seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id,
 				mode->hdisplay, mode->vdisplay);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index ec9c538..5e4dc5c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -238,24 +238,6 @@ struct dpu_crtc_state {
 	container_of(x, struct dpu_crtc_state, base)
 
 /**
- * dpu_crtc_get_mixer_width - get the mixer width
- * Mixer width will be same as panel width(/2 for split)
- */
-static inline int dpu_crtc_get_mixer_width(struct dpu_crtc *dpu_crtc,
-	struct dpu_crtc_state *cstate, struct drm_display_mode *mode)
-{
-	u32 mixer_width;
-
-	if (!dpu_crtc || !cstate || !mode)
-		return 0;
-
-	mixer_width = (dpu_crtc->num_mixers == CRTC_DUAL_MIXERS ?
-			mode->hdisplay / CRTC_DUAL_MIXERS : mode->hdisplay);
-
-	return mixer_width;
-}
-
-/**
  * dpu_crtc_get_mixer_height - get the mixer height
  * Mixer height will be same as panel height
  */
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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[PATCH 10/14] drm/msm/dpu: move hw resource tracking to crtc state

[Jeykumar Sankaran]

Prep changes for state based resource management.

Moves all the hw block tracking for the crtc to the state
object.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 60 ++++++++++++++++++--------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 22 ++++++------
 2 files changed, 44 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index e061847..7ab320d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -163,9 +163,9 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
 	crtc_state = to_dpu_crtc_state(crtc->state);
 
 	lm_horiz_position = 0;
-	for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
+	for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) {
 		const struct drm_rect *lm_roi = &crtc_state->lm_bounds[lm_idx];
-		struct dpu_hw_mixer *hw_lm = dpu_crtc->mixers[lm_idx].hw_lm;
+		struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm;
 		struct dpu_hw_mixer_cfg cfg;
 
 		if (!lm_roi || !drm_rect_visible(lm_roi))
@@ -246,7 +246,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
 					   fb ? fb->modifier : 0);
 
 		/* blend config update */
-		for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
+		for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
 			_dpu_crtc_setup_blend_cfg(mixer + lm_idx,
 						pstate, format);
 
@@ -270,7 +270,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
 static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
 {
 	struct dpu_crtc *dpu_crtc;
-	struct dpu_crtc_state *dpu_crtc_state;
+	struct dpu_crtc_state *cstate;
 	struct dpu_crtc_mixer *mixer;
 	struct dpu_hw_ctl *ctl;
 	struct dpu_hw_mixer *lm;
@@ -281,17 +281,17 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
 		return;
 
 	dpu_crtc = to_dpu_crtc(crtc);
-	dpu_crtc_state = to_dpu_crtc_state(crtc->state);
-	mixer = dpu_crtc->mixers;
+	cstate = to_dpu_crtc_state(crtc->state);
+	mixer = cstate->mixers;
 
 	DPU_DEBUG("%s\n", dpu_crtc->name);
 
-	if (dpu_crtc->num_mixers > CRTC_DUAL_MIXERS) {
-		DPU_ERROR("invalid number mixers: %d\n", dpu_crtc->num_mixers);
+	if (cstate->num_mixers > CRTC_DUAL_MIXERS) {
+		DPU_ERROR("invalid number mixers: %d\n", cstate->num_mixers);
 		return;
 	}
 
-	for (i = 0; i < dpu_crtc->num_mixers; i++) {
+	for (i = 0; i < cstate->num_mixers; i++) {
 		if (!mixer[i].hw_lm || !mixer[i].hw_ctl) {
 			DPU_ERROR("invalid lm or ctl assigned to mixer\n");
 			return;
@@ -308,7 +308,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
 
 	_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer);
 
-	for (i = 0; i < dpu_crtc->num_mixers; i++) {
+	for (i = 0; i < cstate->num_mixers; i++) {
 		ctl = mixer[i].hw_ctl;
 		lm = mixer[i].hw_lm;
 
@@ -530,7 +530,7 @@ static void _dpu_crtc_setup_mixer_for_encoder(
 		struct drm_crtc *crtc,
 		struct drm_encoder *enc)
 {
-	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
+	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
 	struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
 	struct dpu_rm *rm = &dpu_kms->rm;
 	struct dpu_crtc_mixer *mixer;
@@ -542,8 +542,8 @@ static void _dpu_crtc_setup_mixer_for_encoder(
 	dpu_rm_init_hw_iter(&ctl_iter, enc->base.id, DPU_HW_BLK_CTL);
 
 	/* Set up all the mixers and ctls reserved by this encoder */
-	for (i = dpu_crtc->num_mixers; i < ARRAY_SIZE(dpu_crtc->mixers); i++) {
-		mixer = &dpu_crtc->mixers[i];
+	for (i = cstate->num_mixers; i < ARRAY_SIZE(cstate->mixers); i++) {
+		mixer = &cstate->mixers[i];
 
 		if (!dpu_rm_get_hw(rm, &lm_iter))
 			break;
@@ -568,7 +568,7 @@ static void _dpu_crtc_setup_mixer_for_encoder(
 
 		mixer->encoder = enc;
 
-		dpu_crtc->num_mixers++;
+		cstate->num_mixers++;
 		DPU_DEBUG("setup mixer %d: lm %d\n",
 				i, mixer->hw_lm->idx - LM_0);
 		DPU_DEBUG("setup mixer %d: ctl %d\n",
@@ -579,11 +579,11 @@ static void _dpu_crtc_setup_mixer_for_encoder(
 static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
 {
 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
+	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
 	struct drm_encoder *enc;
 
-	dpu_crtc->num_mixers = 0;
-	dpu_crtc->mixers_swapped = false;
-	memset(dpu_crtc->mixers, 0, sizeof(dpu_crtc->mixers));
+	cstate->num_mixers = 0;
+	memset(cstate->mixers, 0, sizeof(cstate->mixers));
 
 	mutex_lock(&dpu_crtc->crtc_lock);
 	/* Check for mixers on all encoders attached to this crtc */
@@ -618,7 +618,7 @@ static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
 	crtc_split_width = _dpu_crtc_get_mixer_width(dpu_crtc, cstate,
 						    adj_mode);
 
-	for (i = 0; i < dpu_crtc->num_mixers; i++) {
+	for (i = 0; i < cstate->num_mixers; i++) {
 		struct drm_rect *r = &cstate->lm_bounds[i];
 		r->x1 = crtc_split_width * i;
 		r->y1 = 0;
@@ -635,6 +635,7 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
 		struct drm_crtc_state *old_state)
 {
 	struct dpu_crtc *dpu_crtc;
+	struct dpu_crtc_state *cstate;
 	struct drm_encoder *encoder;
 	struct drm_device *dev;
 	unsigned long flags;
@@ -654,10 +655,11 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
 	DPU_DEBUG("crtc%d\n", crtc->base.id);
 
 	dpu_crtc = to_dpu_crtc(crtc);
+	cstate = to_dpu_crtc_state(crtc->state);
 	dev = crtc->dev;
 	smmu_state = &dpu_crtc->smmu_state;
 
-	if (!dpu_crtc->num_mixers) {
+	if (!cstate->num_mixers) {
 		_dpu_crtc_setup_mixers(crtc);
 		_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
 	}
@@ -684,7 +686,7 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
 	 * it means we are trying to flush a CRTC whose state is disabled:
 	 * nothing else needs to be done.
 	 */
-	if (unlikely(!dpu_crtc->num_mixers))
+	if (unlikely(!cstate->num_mixers))
 		return;
 
 	_dpu_crtc_blend_setup(crtc);
@@ -748,7 +750,7 @@ static void dpu_crtc_atomic_flush(struct drm_crtc *crtc,
 	 * it means we are trying to flush a CRTC whose state is disabled:
 	 * nothing else needs to be done.
 	 */
-	if (unlikely(!dpu_crtc->num_mixers))
+	if (unlikely(!cstate->num_mixers))
 		return;
 
 	/*
@@ -863,7 +865,7 @@ void dpu_crtc_commit_kickoff(struct drm_crtc *crtc)
 	 * it means we are trying to start a CRTC whose state is disabled:
 	 * nothing else needs to be done.
 	 */
-	if (unlikely(!dpu_crtc->num_mixers))
+	if (unlikely(!cstate->num_mixers))
 		return;
 
 	DPU_ATRACE_BEGIN("crtc_commit");
@@ -1097,12 +1099,14 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg)
 	struct drm_crtc *crtc = arg;
 	struct dpu_crtc *dpu_crtc;
 	struct drm_encoder *encoder;
+	struct dpu_crtc_state *cstate;
 
 	if (!crtc) {
 		DPU_ERROR("invalid crtc\n");
 		return;
 	}
 	dpu_crtc = to_dpu_crtc(crtc);
+	cstate = to_dpu_crtc_state(dpu_crtc->base.state);
 
 	mutex_lock(&dpu_crtc->crtc_lock);
 
@@ -1197,9 +1201,8 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
 		dpu_power_handle_unregister_event(dpu_crtc->phandle,
 				dpu_crtc->power_event);
 
-	memset(dpu_crtc->mixers, 0, sizeof(dpu_crtc->mixers));
-	dpu_crtc->num_mixers = 0;
-	dpu_crtc->mixers_swapped = false;
+	memset(cstate->mixers, 0, sizeof(cstate->mixers));
+	cstate->num_mixers = 0;
 
 	/* disable clk & bw control until clk & bw properties are set */
 	cstate->bw_control = false;
@@ -1547,6 +1550,8 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
 
 	dpu_crtc = s->private;
 	crtc = &dpu_crtc->base;
+
+	drm_modeset_lock(&crtc->mutex, NULL);
 	cstate = to_dpu_crtc_state(crtc->state);
 
 	mutex_lock(&dpu_crtc->crtc_lock);
@@ -1558,8 +1563,8 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
 
 	seq_puts(s, "\n");
 
-	for (i = 0; i < dpu_crtc->num_mixers; ++i) {
-		m = &dpu_crtc->mixers[i];
+	for (i = 0; i < cstate->num_mixers; ++i) {
+		m = &cstate->mixers[i];
 		if (!m->hw_lm)
 			seq_printf(s, "\tmixer[%d] has no lm\n", i);
 		else if (!m->hw_ctl)
@@ -1639,6 +1644,7 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
 	seq_printf(s, "vblank_enable:%d\n", dpu_crtc->vblank_requested);
 
 	mutex_unlock(&dpu_crtc->crtc_lock);
+	drm_modeset_unlock(&crtc->mutex);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 5e4dc5c..7aa772f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -121,11 +121,6 @@ struct dpu_crtc_frame_event {
  * struct dpu_crtc - virtualized CRTC data structure
  * @base          : Base drm crtc structure
  * @name          : ASCII description of this crtc
- * @num_ctls      : Number of ctl paths in use
- * @num_mixers    : Number of mixers in use
- * @mixers_swapped: Whether the mixers have been swapped for left/right update
- *                  especially in the case of DSC Merge.
- * @mixers        : List of active mixers
  * @event         : Pointer to last received drm vblank event. If there is a
  *                  pending vblank event, this will be non-null.
  * @vsync_count   : Running count of received vsync events
@@ -164,12 +159,6 @@ struct dpu_crtc {
 	struct drm_crtc base;
 	char name[DPU_CRTC_NAME_SIZE];
 
-	/* HW Resources reserved for the crtc */
-	u32 num_ctls;
-	u32 num_mixers;
-	bool mixers_swapped;
-	struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
-
 	struct drm_pending_vblank_event *event;
 	u32 vsync_count;
 
@@ -221,6 +210,10 @@ struct dpu_crtc {
  * @property_values: Current crtc property values
  * @input_fence_timeout_ns : Cached input fence timeout, in ns
  * @new_perf: new performance state being requested
+ * @num_mixers    : Number of mixers in use
+ * @mixers        : List of active mixers
+ * @num_ctls      : Number of ctl paths in use
+ * @hw_ctls       : List of active ctl paths
  */
 struct dpu_crtc_state {
 	struct drm_crtc_state base;
@@ -232,6 +225,13 @@ struct dpu_crtc_state {
 	uint64_t input_fence_timeout_ns;
 
 	struct dpu_core_perf_params new_perf;
+
+	/* HW Resources reserved for the crtc */
+	u32 num_mixers;
+	struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
+
+	u32 num_ctls;
+	struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS];
 };
 
 #define to_dpu_crtc_state(x) \
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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[PATCH 11/14] drm/msm/dpu: rename hw_ctl to lm_ctl

[Jeykumar Sankaran]

Rename hw_ctl to lm_ctl to mean the ctl associated
with the hw layer mixer block.

sed -i 's/\([*@.>]\)hw_ctl\([^s]\)/\1lm_ctl\2/g' dpu_crtc.c dpu_crtc.h

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 26 +++++++++++++-------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |  4 ++--
 2 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 7ab320d..aeb0f1a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -202,7 +202,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
 		return;
 	}
 
-	ctl = mixer->hw_ctl;
+	ctl = mixer->lm_ctl;
 	lm = mixer->hw_lm;
 	stage_cfg = &dpu_crtc->stage_cfg;
 	cstate = to_dpu_crtc_state(crtc->state);
@@ -292,15 +292,15 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
 	}
 
 	for (i = 0; i < cstate->num_mixers; i++) {
-		if (!mixer[i].hw_lm || !mixer[i].hw_ctl) {
+		if (!mixer[i].hw_lm || !mixer[i].lm_ctl) {
 			DPU_ERROR("invalid lm or ctl assigned to mixer\n");
 			return;
 		}
 		mixer[i].mixer_op_mode = 0;
 		mixer[i].flush_mask = 0;
-		if (mixer[i].hw_ctl->ops.clear_all_blendstages)
-			mixer[i].hw_ctl->ops.clear_all_blendstages(
-					mixer[i].hw_ctl);
+		if (mixer[i].lm_ctl->ops.clear_all_blendstages)
+			mixer[i].lm_ctl->ops.clear_all_blendstages(
+					mixer[i].lm_ctl);
 	}
 
 	/* initialize stage cfg */
@@ -309,7 +309,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
 	_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer);
 
 	for (i = 0; i < cstate->num_mixers; i++) {
-		ctl = mixer[i].hw_ctl;
+		ctl = mixer[i].lm_ctl;
 		lm = mixer[i].hw_lm;
 
 		lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
@@ -553,14 +553,14 @@ static void _dpu_crtc_setup_mixer_for_encoder(
 		if (!dpu_rm_get_hw(rm, &ctl_iter)) {
 			DPU_DEBUG("no ctl assigned to lm %d, using previous\n",
 					mixer->hw_lm->idx - LM_0);
-			mixer->hw_ctl = last_valid_ctl;
+			mixer->lm_ctl = last_valid_ctl;
 		} else {
-			mixer->hw_ctl = (struct dpu_hw_ctl *)ctl_iter.hw;
-			last_valid_ctl = mixer->hw_ctl;
+			mixer->lm_ctl = (struct dpu_hw_ctl *)ctl_iter.hw;
+			last_valid_ctl = mixer->lm_ctl;
 		}
 
 		/* Shouldn't happen, mixers are always >= ctls */
-		if (!mixer->hw_ctl) {
+		if (!mixer->lm_ctl) {
 			DPU_ERROR("no valid ctls found for lm %d\n",
 					mixer->hw_lm->idx - LM_0);
 			return;
@@ -572,7 +572,7 @@ static void _dpu_crtc_setup_mixer_for_encoder(
 		DPU_DEBUG("setup mixer %d: lm %d\n",
 				i, mixer->hw_lm->idx - LM_0);
 		DPU_DEBUG("setup mixer %d: ctl %d\n",
-				i, mixer->hw_ctl->idx - CTL_0);
+				i, mixer->lm_ctl->idx - CTL_0);
 	}
 }
 
@@ -1567,11 +1567,11 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
 		m = &cstate->mixers[i];
 		if (!m->hw_lm)
 			seq_printf(s, "\tmixer[%d] has no lm\n", i);
-		else if (!m->hw_ctl)
+		else if (!m->lm_ctl)
 			seq_printf(s, "\tmixer[%d] has no ctl\n", i);
 		else
 			seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n",
-				m->hw_lm->idx - LM_0, m->hw_ctl->idx - CTL_0,
+				m->hw_lm->idx - LM_0, m->lm_ctl->idx - CTL_0,
 				out_width, mode->vdisplay);
 	}
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 7aa772f..9b1056c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -83,14 +83,14 @@ struct dpu_crtc_smmu_state_data {
 /**
  * struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC
  * @hw_lm:	LM HW Driver context
- * @hw_ctl:	CTL Path HW driver context
+ * @lm_ctl:	CTL Path HW driver context
  * @encoder:	Encoder attached to this lm & ctl
  * @mixer_op_mode:	mixer blending operation mode
  * @flush_mask:	mixer flush mask for ctl, mixer and pipe
  */
 struct dpu_crtc_mixer {
 	struct dpu_hw_mixer *hw_lm;
-	struct dpu_hw_ctl *hw_ctl;
+	struct dpu_hw_ctl *lm_ctl;
 	struct drm_encoder *encoder;
 	u32 mixer_op_mode;
 	u32 flush_mask;
-- 
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a Linux Foundation Collaborative Project

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[PATCH 12/14] drm/msm/dpu: remove topology name

[Jeykumar Sankaran]

Strip down the support for topology enums. It
can be replaced with simple hw count checks.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        |  3 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h        |  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |  9 ++++--
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  7 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c             | 36 ++++++----------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h             | 24 ---------------
 6 files changed, 19 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index dbf669e..56ef349 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1013,7 +1013,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 	struct drm_connector *conn = NULL, *conn_iter;
 	struct dpu_rm_hw_iter pp_iter, ctl_iter;
 	struct msm_display_topology topology;
-	enum dpu_rm_topology_name topology_name;
 	struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL };
 	int i = 0, ret;
 
@@ -1069,7 +1068,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 		hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw;
 	}
 
-	topology_name = dpu_rm_get_topology_name(topology);
 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
 
@@ -1089,7 +1087,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 			phys->hw_ctl = hw_ctl[i];
 
 			phys->connector = conn->state->connector;
-			phys->topology_name = topology_name;
 			if (phys->ops.mode_set)
 				phys->ops.mode_set(phys, mode, adj_mode);
 		}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index 60f809f..c5600e6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -35,7 +35,6 @@
  * @needs_cdm:	Encoder requests a CDM based on pixel format conversion needs
  * @display_num_of_h_tiles: Number of horizontal tiles in case of split
  *                          interface
- * @topology:   Topology of the display
  */
 struct dpu_encoder_hw_resources {
 	enum dpu_intf_mode intfs[INTF_MAX];
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index b3917e0..b5fc65c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -24,6 +24,7 @@
 #include "dpu_hw_top.h"
 #include "dpu_hw_cdm.h"
 #include "dpu_encoder.h"
+#include "dpu_crtc.h"
 
 #define DPU_ENCODER_NAME_MAX	16
 
@@ -213,7 +214,6 @@ struct dpu_encoder_irq {
  * @split_role:		Role to play in a split-panel configuration
  * @intf_mode:		Interface mode
  * @intf_idx:		Interface index on dpu hardware
- * @topology_name:	topology selected for the display
  * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
  * @enable_state:	Enable state tracking
  * @vblank_refcount:	Reference count of vblank request
@@ -243,7 +243,6 @@ struct dpu_encoder_phys {
 	enum dpu_enc_split_role split_role;
 	enum dpu_intf_mode intf_mode;
 	enum dpu_intf intf_idx;
-	enum dpu_rm_topology_name topology_name;
 	spinlock_t *enc_spinlock;
 	enum dpu_enc_enable_state enable_state;
 	atomic_t vblank_refcount;
@@ -361,11 +360,15 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
 static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
 		struct dpu_encoder_phys *phys_enc)
 {
+	struct dpu_crtc_state *dpu_cstate;
+
 	if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
 		return BLEND_3D_NONE;
 
+	dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
+
 	if (phys_enc->split_role == ENC_ROLE_SOLO &&
-	    phys_enc->topology_name == DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE)
+	    (dpu_cstate->num_mixers == 2))
 		return BLEND_3D_H_ROW_INT;
 
 	return BLEND_3D_NONE;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 6de13f4..1643e2f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -355,13 +355,14 @@ static void dpu_encoder_phys_vid_underrun_irq(void *arg, int irq_idx)
 
 static bool _dpu_encoder_phys_is_dual_ctl(struct dpu_encoder_phys *phys_enc)
 {
+	struct dpu_crtc_state *dpu_cstate;
+
 	if (!phys_enc)
 		return false;
 
-	if (phys_enc->topology_name == DPU_RM_TOPOLOGY_DUALPIPE)
-		return true;
+	dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
 
-	return false;
+	return (dpu_cstate->num_ctls > 1);
 }
 
 static bool dpu_encoder_phys_vid_needs_single_flush(
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 13c0a36..fbd489f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -33,7 +33,6 @@
 				(t).num_intf == (r).num_intf)
 
 struct dpu_rm_topology_def {
-	enum dpu_rm_topology_name top_name;
 	int num_lm;
 	int num_comp_enc;
 	int num_intf;
@@ -42,10 +41,10 @@ struct dpu_rm_topology_def {
 };
 
 static const struct dpu_rm_topology_def g_top_table[] = {
-	{   DPU_RM_TOPOLOGY_NONE,                 0, 0, 0, 0, false },
-	{   DPU_RM_TOPOLOGY_SINGLEPIPE,           1, 0, 1, 1, false },
-	{   DPU_RM_TOPOLOGY_DUALPIPE,             2, 0, 2, 2, true  },
-	{   DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,     2, 0, 1, 1, false },
+	{   0, 0, 0, 0, false },
+	{   1, 0, 1, 1, false },
+	{   2, 0, 2, 2, true  },
+	{   2, 0, 1, 1, false },
 };
 
 /**
@@ -72,13 +71,11 @@ struct dpu_rm_requirements {
  * @enc_id:	Reservations are tracked by Encoder DRM object ID.
  *		CRTCs may be connected to multiple Encoders.
  *		An encoder or connector id identifies the display path.
- * @topology	DRM<->HW topology use case
  */
 struct dpu_rm_rsvp {
 	struct list_head list;
 	uint32_t seq;
 	uint32_t enc_id;
-	enum dpu_rm_topology_name topology;
 };
 
 /**
@@ -122,8 +119,8 @@ static void _dpu_rm_print_rsvps(
 	DPU_DEBUG("%d\n", stage);
 
 	list_for_each_entry(rsvp, &rm->rsvps, list) {
-		DRM_DEBUG_KMS("%d rsvp[s%ue%u] topology %d\n", stage, rsvp->seq,
-			      rsvp->enc_id, rsvp->topology);
+		DRM_DEBUG_KMS("%d rsvp[s%ue%u]\n", stage, rsvp->seq,
+			      rsvp->enc_id);
 	}
 
 	for (type = 0; type < DPU_HW_BLK_MAX; type++) {
@@ -146,18 +143,6 @@ struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm)
 	return rm->hw_mdp;
 }
 
-enum dpu_rm_topology_name
-dpu_rm_get_topology_name(struct msm_display_topology topology)
-{
-	int i;
-
-	for (i = 0; i < DPU_RM_TOPOLOGY_MAX; i++)
-		if (RM_IS_TOPOLOGY_MATCH(g_top_table[i], topology))
-			return g_top_table[i].top_name;
-
-	return DPU_RM_TOPOLOGY_NONE;
-}
-
 void dpu_rm_init_hw_iter(
 		struct dpu_rm_hw_iter *iter,
 		uint32_t enc_id,
@@ -760,7 +745,6 @@ static int _dpu_rm_make_next_rsvp(
 	/* Create reservation info, tag reserved blocks with it as we go */
 	rsvp->seq = ++rm->rsvp_next_seq;
 	rsvp->enc_id = enc->base.id;
-	rsvp->topology = reqs->topology->top_name;
 	list_add_tail(&rsvp->list, &rm->rsvps);
 
 	ret = _dpu_rm_reserve_lms(rm, rsvp, reqs);
@@ -807,7 +791,7 @@ static int _dpu_rm_populate_requirements(
 
 	dpu_encoder_get_hw_resources(enc, &reqs->hw_res, conn_state);
 
-	for (i = 0; i < DPU_RM_TOPOLOGY_MAX; i++) {
+	for (i = 0; i < ARRAY_SIZE(g_top_table); i++) {
 		if (RM_IS_TOPOLOGY_MATCH(g_top_table[i],
 					req_topology)) {
 			reqs->topology = &g_top_table[i];
@@ -831,9 +815,8 @@ static int _dpu_rm_populate_requirements(
 
 	DRM_DEBUG_KMS("top_ctrl: 0x%llX num_h_tiles: %d\n", reqs->top_ctrl,
 		      reqs->hw_res.display_num_of_h_tiles);
-	DRM_DEBUG_KMS("num_lm: %d num_ctl: %d topology: %d split_display: %d\n",
+	DRM_DEBUG_KMS("num_lm: %d num_ctl: %d split_display: %d\n",
 		      reqs->topology->num_lm, reqs->topology->num_ctl,
-		      reqs->topology->top_name,
 		      reqs->topology->needs_split_display);
 
 	return 0;
@@ -969,8 +952,7 @@ static int _dpu_rm_commit_rsvp(
 	}
 
 	if (!ret)
-		DRM_DEBUG_KMS("rsrv enc %d topology %d\n", rsvp->enc_id,
-			      rsvp->topology);
+		DRM_DEBUG_KMS("rsrv enc %d\n", rsvp->enc_id);
 
 	return ret;
 }
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index ffd1841..6fd9e7b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -21,21 +21,6 @@
 #include "dpu_hw_top.h"
 
 /**
- * enum dpu_rm_topology_name - HW resource use case in use by connector
- * @DPU_RM_TOPOLOGY_NONE:                 No topology in use currently
- * @DPU_RM_TOPOLOGY_SINGLEPIPE:           1 LM, 1 PP, 1 INTF/WB
- * @DPU_RM_TOPOLOGY_DUALPIPE:             2 LM, 2 PP, 2 INTF/WB
- * @DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE:     2 LM, 2 PP, 3DMux, 1 INTF/WB
- */
-enum dpu_rm_topology_name {
-	DPU_RM_TOPOLOGY_NONE = 0,
-	DPU_RM_TOPOLOGY_SINGLEPIPE,
-	DPU_RM_TOPOLOGY_DUALPIPE,
-	DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,
-	DPU_RM_TOPOLOGY_MAX,
-};
-
-/**
  * enum dpu_rm_topology_control - HW resource use case in use by connector
  * @DPU_RM_TOPCTL_RESERVE_LOCK: If set, in AtomicTest phase, after a successful
  *                              test, reserve the resources for this display.
@@ -187,13 +172,4 @@ void dpu_rm_init_hw_iter(
  */
 int dpu_rm_check_property_topctl(uint64_t val);
 
-/**
- * dpu_rm_get_topology_name - returns the name of the the given topology
- *                            definition
- * @topology: topology definition
- * @Return: name of the topology
- */
-enum dpu_rm_topology_name
-dpu_rm_get_topology_name(struct msm_display_topology topology);
-
 #endif /* __DPU_RM_H__ */
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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[PATCH 13/14] drm/msm/dpu: remove display H_TILE from encoder

[Jeykumar Sankaran]

Encoder H_TILE values are not used for allocating the hw blocks.
no. of hw_intf blocks provides the info.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 5 -----
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 3 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c      | 3 +--
 3 files changed, 1 insertion(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 56ef349..bfc082d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -175,8 +175,6 @@ struct dpu_encoder_virt {
 	spinlock_t enc_spinlock;
 	uint32_t bus_scaling_client;
 
-	uint32_t display_num_of_h_tiles;
-
 	unsigned int num_phys_encs;
 	struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
 	struct dpu_encoder_phys *cur_master;
@@ -455,7 +453,6 @@ void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc,
 
 	/* Query resources used by phys encs, expected to be without overlap */
 	memset(hw_res, 0, sizeof(*hw_res));
-	hw_res->display_num_of_h_tiles = dpu_enc->display_num_of_h_tiles;
 
 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
@@ -2103,8 +2100,6 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
 
 	WARN_ON(disp_info->num_of_h_tiles < 1);
 
-	dpu_enc->display_num_of_h_tiles = disp_info->num_of_h_tiles;
-
 	DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
 
 	if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index c5600e6..e453271 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -33,13 +33,10 @@
  * Encoder functions and data types
  * @intfs:	Interfaces this encoder is using, INTF_MODE_NONE if unused
  * @needs_cdm:	Encoder requests a CDM based on pixel format conversion needs
- * @display_num_of_h_tiles: Number of horizontal tiles in case of split
- *                          interface
  */
 struct dpu_encoder_hw_resources {
 	enum dpu_intf_mode intfs[INTF_MAX];
 	bool needs_cdm;
-	u32 display_num_of_h_tiles;
 };
 
 /**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index fbd489f..388ae65 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -813,8 +813,7 @@ static int _dpu_rm_populate_requirements(
 		conn_state->connector->connector_type == DRM_MODE_CONNECTOR_DSI)
 		reqs->top_ctrl |= BIT(DPU_RM_TOPCTL_DS);
 
-	DRM_DEBUG_KMS("top_ctrl: 0x%llX num_h_tiles: %d\n", reqs->top_ctrl,
-		      reqs->hw_res.display_num_of_h_tiles);
+	DRM_DEBUG_KMS("top_ctrl: 0x%llX\n", reqs->top_ctrl);
 	DRM_DEBUG_KMS("num_lm: %d num_ctl: %d split_display: %d\n",
 		      reqs->topology->num_lm, reqs->topology->num_ctl,
 		      reqs->topology->needs_split_display);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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[PATCH 14/14] drm/msm/dpu: remove cdm block support from resource manager

[Jeykumar Sankaran]

Support for CDM block is not present in DPU. Remove CDM
handlers from resource manager.

Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
---
 drivers/gpu/drm/msm/Makefile                     |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h      |   2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h |   5 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c       | 323 -----------------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h       | 139 ----------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c       |  14 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h       |   4 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c       |  18 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h       |  17 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c           |  68 +----
 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h        |   4 -
 11 files changed, 2 insertions(+), 593 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 261fa79..19ab521 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -58,7 +58,6 @@ msm-y := \
 	disp/dpu1/dpu_formats.o \
 	disp/dpu1/dpu_hw_blk.o \
 	disp/dpu1/dpu_hw_catalog.o \
-	disp/dpu1/dpu_hw_cdm.o \
 	disp/dpu1/dpu_hw_ctl.o \
 	disp/dpu1/dpu_hw_interrupts.o \
 	disp/dpu1/dpu_hw_intf.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
index e453271..e844afa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
@@ -32,11 +32,9 @@
 /**
  * Encoder functions and data types
  * @intfs:	Interfaces this encoder is using, INTF_MODE_NONE if unused
- * @needs_cdm:	Encoder requests a CDM based on pixel format conversion needs
  */
 struct dpu_encoder_hw_resources {
 	enum dpu_intf_mode intfs[INTF_MAX];
-	bool needs_cdm;
 };
 
 /**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index b5fc65c..f796683 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -22,7 +22,6 @@
 #include "dpu_hw_pingpong.h"
 #include "dpu_hw_ctl.h"
 #include "dpu_hw_top.h"
-#include "dpu_hw_cdm.h"
 #include "dpu_encoder.h"
 #include "dpu_crtc.h"
 
@@ -205,8 +204,6 @@ struct dpu_encoder_irq {
  * @parent_ops:		Callbacks exposed by the parent to the phys_enc
  * @hw_mdptop:		Hardware interface to the top registers
  * @hw_ctl:		Hardware interface to the ctl registers
- * @hw_cdm:		Hardware interface to the cdm registers
- * @cdm_cfg:		Chroma-down hardware configuration
  * @hw_pp:		Hardware interface to the ping pong registers
  * @dpu_kms:		Pointer to the dpu_kms top level
  * @cached_mode:	DRM mode cached at mode_set time, acted on in enable
@@ -235,8 +232,6 @@ struct dpu_encoder_phys {
 	const struct dpu_encoder_virt_ops *parent_ops;
 	struct dpu_hw_mdp *hw_mdptop;
 	struct dpu_hw_ctl *hw_ctl;
-	struct dpu_hw_cdm *hw_cdm;
-	struct dpu_hw_cdm_cfg cdm_cfg;
 	struct dpu_hw_pingpong *hw_pp;
 	struct dpu_kms *dpu_kms;
 	struct drm_display_mode cached_mode;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
deleted file mode 100644
index 554874b..0000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
+++ /dev/null
@@ -1,323 +0,0 @@
-/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "dpu_hw_mdss.h"
-#include "dpu_hwio.h"
-#include "dpu_hw_catalog.h"
-#include "dpu_hw_cdm.h"
-#include "dpu_dbg.h"
-#include "dpu_kms.h"
-
-#define CDM_CSC_10_OPMODE                  0x000
-#define CDM_CSC_10_BASE                    0x004
-
-#define CDM_CDWN2_OP_MODE                  0x100
-#define CDM_CDWN2_CLAMP_OUT                0x104
-#define CDM_CDWN2_PARAMS_3D_0              0x108
-#define CDM_CDWN2_PARAMS_3D_1              0x10C
-#define CDM_CDWN2_COEFF_COSITE_H_0         0x110
-#define CDM_CDWN2_COEFF_COSITE_H_1         0x114
-#define CDM_CDWN2_COEFF_COSITE_H_2         0x118
-#define CDM_CDWN2_COEFF_OFFSITE_H_0        0x11C
-#define CDM_CDWN2_COEFF_OFFSITE_H_1        0x120
-#define CDM_CDWN2_COEFF_OFFSITE_H_2        0x124
-#define CDM_CDWN2_COEFF_COSITE_V           0x128
-#define CDM_CDWN2_COEFF_OFFSITE_V          0x12C
-#define CDM_CDWN2_OUT_SIZE                 0x130
-
-#define CDM_HDMI_PACK_OP_MODE              0x200
-#define CDM_CSC_10_MATRIX_COEFF_0          0x004
-
-/**
- * Horizontal coefficients for cosite chroma downscale
- * s13 representation of coefficients
- */
-static u32 cosite_h_coeff[] = {0x00000016, 0x000001cc, 0x0100009e};
-
-/**
- * Horizontal coefficients for offsite chroma downscale
- */
-static u32 offsite_h_coeff[] = {0x000b0005, 0x01db01eb, 0x00e40046};
-
-/**
- * Vertical coefficients for cosite chroma downscale
- */
-static u32 cosite_v_coeff[] = {0x00080004};
-/**
- * Vertical coefficients for offsite chroma downscale
- */
-static u32 offsite_v_coeff[] = {0x00060002};
-
-/* Limited Range rgb2yuv coeff with clamp and bias values for CSC 10 module */
-static struct dpu_csc_cfg rgb2yuv_cfg = {
-	{
-		0x0083, 0x0102, 0x0032,
-		0x1fb5, 0x1f6c, 0x00e1,
-		0x00e1, 0x1f45, 0x1fdc
-	},
-	{ 0x00, 0x00, 0x00 },
-	{ 0x0040, 0x0200, 0x0200 },
-	{ 0x000, 0x3ff, 0x000, 0x3ff, 0x000, 0x3ff },
-	{ 0x040, 0x3ac, 0x040, 0x3c0, 0x040, 0x3c0 },
-};
-
-static struct dpu_cdm_cfg *_cdm_offset(enum dpu_cdm cdm,
-		struct dpu_mdss_cfg *m,
-		void __iomem *addr,
-		struct dpu_hw_blk_reg_map *b)
-{
-	int i;
-
-	for (i = 0; i < m->cdm_count; i++) {
-		if (cdm == m->cdm[i].id) {
-			b->base_off = addr;
-			b->blk_off = m->cdm[i].base;
-			b->length = m->cdm[i].len;
-			b->hwversion = m->hwversion;
-			b->log_mask = DPU_DBG_MASK_CDM;
-			return &m->cdm[i];
-		}
-	}
-
-	return ERR_PTR(-EINVAL);
-}
-
-static int dpu_hw_cdm_setup_csc_10bit(struct dpu_hw_cdm *ctx,
-		struct dpu_csc_cfg *data)
-{
-	dpu_hw_csc_setup(&ctx->hw, CDM_CSC_10_MATRIX_COEFF_0, data, true);
-
-	return 0;
-}
-
-static int dpu_hw_cdm_setup_cdwn(struct dpu_hw_cdm *ctx,
-		struct dpu_hw_cdm_cfg *cfg)
-{
-	struct dpu_hw_blk_reg_map *c = &ctx->hw;
-	u32 opmode = 0;
-	u32 out_size = 0;
-
-	if (cfg->output_bit_depth == CDM_CDWN_OUTPUT_10BIT)
-		opmode &= ~BIT(7);
-	else
-		opmode |= BIT(7);
-
-	/* ENABLE DWNS_H bit */
-	opmode |= BIT(1);
-
-	switch (cfg->h_cdwn_type) {
-	case CDM_CDWN_DISABLE:
-		/* CLEAR METHOD_H field */
-		opmode &= ~(0x18);
-		/* CLEAR DWNS_H bit */
-		opmode &= ~BIT(1);
-		break;
-	case CDM_CDWN_PIXEL_DROP:
-		/* Clear METHOD_H field (pixel drop is 0) */
-		opmode &= ~(0x18);
-		break;
-	case CDM_CDWN_AVG:
-		/* Clear METHOD_H field (Average is 0x1) */
-		opmode &= ~(0x18);
-		opmode |= (0x1 << 0x3);
-		break;
-	case CDM_CDWN_COSITE:
-		/* Clear METHOD_H field (Average is 0x2) */
-		opmode &= ~(0x18);
-		opmode |= (0x2 << 0x3);
-		/* Co-site horizontal coefficients */
-		DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_0,
-				cosite_h_coeff[0]);
-		DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_1,
-				cosite_h_coeff[1]);
-		DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_2,
-				cosite_h_coeff[2]);
-		break;
-	case CDM_CDWN_OFFSITE:
-		/* Clear METHOD_H field (Average is 0x3) */
-		opmode &= ~(0x18);
-		opmode |= (0x3 << 0x3);
-
-		/* Off-site horizontal coefficients */
-		DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_0,
-				offsite_h_coeff[0]);
-		DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_1,
-				offsite_h_coeff[1]);
-		DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_2,
-				offsite_h_coeff[2]);
-		break;
-	default:
-		pr_err("%s invalid horz down sampling type\n", __func__);
-		return -EINVAL;
-	}
-
-	/* ENABLE DWNS_V bit */
-	opmode |= BIT(2);
-
-	switch (cfg->v_cdwn_type) {
-	case CDM_CDWN_DISABLE:
-		/* CLEAR METHOD_V field */
-		opmode &= ~(0x60);
-		/* CLEAR DWNS_V bit */
-		opmode &= ~BIT(2);
-		break;
-	case CDM_CDWN_PIXEL_DROP:
-		/* Clear METHOD_V field (pixel drop is 0) */
-		opmode &= ~(0x60);
-		break;
-	case CDM_CDWN_AVG:
-		/* Clear METHOD_V field (Average is 0x1) */
-		opmode &= ~(0x60);
-		opmode |= (0x1 << 0x5);
-		break;
-	case CDM_CDWN_COSITE:
-		/* Clear METHOD_V field (Average is 0x2) */
-		opmode &= ~(0x60);
-		opmode |= (0x2 << 0x5);
-		/* Co-site vertical coefficients */
-		DPU_REG_WRITE(c,
-				CDM_CDWN2_COEFF_COSITE_V,
-				cosite_v_coeff[0]);
-		break;
-	case CDM_CDWN_OFFSITE:
-		/* Clear METHOD_V field (Average is 0x3) */
-		opmode &= ~(0x60);
-		opmode |= (0x3 << 0x5);
-
-		/* Off-site vertical coefficients */
-		DPU_REG_WRITE(c,
-				CDM_CDWN2_COEFF_OFFSITE_V,
-				offsite_v_coeff[0]);
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	if (cfg->v_cdwn_type || cfg->h_cdwn_type)
-		opmode |= BIT(0); /* EN CDWN module */
-	else
-		opmode &= ~BIT(0);
-
-	out_size = (cfg->output_width & 0xFFFF) |
-		((cfg->output_height & 0xFFFF) << 16);
-	DPU_REG_WRITE(c, CDM_CDWN2_OUT_SIZE, out_size);
-	DPU_REG_WRITE(c, CDM_CDWN2_OP_MODE, opmode);
-	DPU_REG_WRITE(c, CDM_CDWN2_CLAMP_OUT,
-			((0x3FF << 16) | 0x0));
-
-	return 0;
-}
-
-static int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx,
-		struct dpu_hw_cdm_cfg *cdm)
-{
-	struct dpu_hw_blk_reg_map *c = &ctx->hw;
-	const struct dpu_format *fmt = cdm->output_fmt;
-	struct cdm_output_cfg cdm_cfg = { 0 };
-	u32 opmode = 0;
-	u32 csc = 0;
-
-	if (!DPU_FORMAT_IS_YUV(fmt))
-		return -EINVAL;
-
-	if (cdm->output_type == CDM_CDWN_OUTPUT_HDMI) {
-		if (fmt->chroma_sample != DPU_CHROMA_H1V2)
-			return -EINVAL; /*unsupported format */
-		opmode = BIT(0);
-		opmode |= (fmt->chroma_sample << 1);
-		cdm_cfg.intf_en = true;
-	}
-
-	csc |= BIT(2);
-	csc &= ~BIT(1);
-	csc |= BIT(0);
-
-	if (ctx->hw_mdp && ctx->hw_mdp->ops.setup_cdm_output)
-		ctx->hw_mdp->ops.setup_cdm_output(ctx->hw_mdp, &cdm_cfg);
-
-	DPU_REG_WRITE(c, CDM_CSC_10_OPMODE, csc);
-	DPU_REG_WRITE(c, CDM_HDMI_PACK_OP_MODE, opmode);
-	return 0;
-}
-
-static void dpu_hw_cdm_disable(struct dpu_hw_cdm *ctx)
-{
-	struct cdm_output_cfg cdm_cfg = { 0 };
-
-	if (ctx->hw_mdp && ctx->hw_mdp->ops.setup_cdm_output)
-		ctx->hw_mdp->ops.setup_cdm_output(ctx->hw_mdp, &cdm_cfg);
-}
-
-static void _setup_cdm_ops(struct dpu_hw_cdm_ops *ops,
-	unsigned long features)
-{
-	ops->setup_csc_data = dpu_hw_cdm_setup_csc_10bit;
-	ops->setup_cdwn = dpu_hw_cdm_setup_cdwn;
-	ops->enable = dpu_hw_cdm_enable;
-	ops->disable = dpu_hw_cdm_disable;
-}
-
-static struct dpu_hw_blk_ops dpu_hw_ops = {
-	.start = NULL,
-	.stop = NULL,
-};
-
-struct dpu_hw_cdm *dpu_hw_cdm_init(enum dpu_cdm idx,
-		void __iomem *addr,
-		struct dpu_mdss_cfg *m,
-		struct dpu_hw_mdp *hw_mdp)
-{
-	struct dpu_hw_cdm *c;
-	struct dpu_cdm_cfg *cfg;
-	int rc;
-
-	c = kzalloc(sizeof(*c), GFP_KERNEL);
-	if (!c)
-		return ERR_PTR(-ENOMEM);
-
-	cfg = _cdm_offset(idx, m, addr, &c->hw);
-	if (IS_ERR_OR_NULL(cfg)) {
-		kfree(c);
-		return ERR_PTR(-EINVAL);
-	}
-
-	c->idx = idx;
-	c->caps = cfg;
-	_setup_cdm_ops(&c->ops, c->caps->features);
-	c->hw_mdp = hw_mdp;
-
-	rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_CDM, idx, &dpu_hw_ops);
-	if (rc) {
-		DPU_ERROR("failed to init hw blk %d\n", rc);
-		goto blk_init_error;
-	}
-
-	/*
-	 * Perform any default initialization for the chroma down module
-	 * @setup default csc coefficients
-	 */
-	dpu_hw_cdm_setup_csc_10bit(c, &rgb2yuv_cfg);
-
-	return c;
-
-blk_init_error:
-	kzfree(c);
-
-	return ERR_PTR(rc);
-}
-
-void dpu_hw_cdm_destroy(struct dpu_hw_cdm *cdm)
-{
-	if (cdm)
-		dpu_hw_blk_destroy(&cdm->base);
-	kfree(cdm);
-}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h
deleted file mode 100644
index 5cceb1e..0000000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _DPU_HW_CDM_H
-#define _DPU_HW_CDM_H
-
-#include "dpu_hw_mdss.h"
-#include "dpu_hw_top.h"
-#include "dpu_hw_blk.h"
-
-struct dpu_hw_cdm;
-
-struct dpu_hw_cdm_cfg {
-	u32 output_width;
-	u32 output_height;
-	u32 output_bit_depth;
-	u32 h_cdwn_type;
-	u32 v_cdwn_type;
-	const struct dpu_format *output_fmt;
-	u32 output_type;
-	int flags;
-};
-
-enum dpu_hw_cdwn_type {
-	CDM_CDWN_DISABLE,
-	CDM_CDWN_PIXEL_DROP,
-	CDM_CDWN_AVG,
-	CDM_CDWN_COSITE,
-	CDM_CDWN_OFFSITE,
-};
-
-enum dpu_hw_cdwn_output_type {
-	CDM_CDWN_OUTPUT_HDMI,
-	CDM_CDWN_OUTPUT_WB,
-};
-
-enum dpu_hw_cdwn_output_bit_depth {
-	CDM_CDWN_OUTPUT_8BIT,
-	CDM_CDWN_OUTPUT_10BIT,
-};
-
-/**
- * struct dpu_hw_cdm_ops : Interface to the chroma down Hw driver functions
- *                         Assumption is these functions will be called after
- *                         clocks are enabled
- *  @setup_csc:            Programs the csc matrix
- *  @setup_cdwn:           Sets up the chroma down sub module
- *  @enable:               Enables the output to interface and programs the
- *                         output packer
- *  @disable:              Puts the cdm in bypass mode
- */
-struct dpu_hw_cdm_ops {
-	/**
-	 * Programs the CSC matrix for conversion from RGB space to YUV space,
-	 * it is optional to call this function as this matrix is automatically
-	 * set during initialization, user should call this if it wants
-	 * to program a different matrix than default matrix.
-	 * @cdm:          Pointer to the chroma down context structure
-	 * @data          Pointer to CSC configuration data
-	 * return:        0 if success; error code otherwise
-	 */
-	int (*setup_csc_data)(struct dpu_hw_cdm *cdm,
-			struct dpu_csc_cfg *data);
-
-	/**
-	 * Programs the Chroma downsample part.
-	 * @cdm         Pointer to chroma down context
-	 */
-	int (*setup_cdwn)(struct dpu_hw_cdm *cdm,
-	struct dpu_hw_cdm_cfg *cfg);
-
-	/**
-	 * Enable the CDM module
-	 * @cdm         Pointer to chroma down context
-	 */
-	int (*enable)(struct dpu_hw_cdm *cdm,
-	struct dpu_hw_cdm_cfg *cfg);
-
-	/**
-	 * Disable the CDM module
-	 * @cdm         Pointer to chroma down context
-	 */
-	void (*disable)(struct dpu_hw_cdm *cdm);
-};
-
-struct dpu_hw_cdm {
-	struct dpu_hw_blk base;
-	struct dpu_hw_blk_reg_map hw;
-
-	/* chroma down */
-	const struct dpu_cdm_cfg *caps;
-	enum  dpu_cdm  idx;
-
-	/* mdp top hw driver */
-	struct dpu_hw_mdp *hw_mdp;
-
-	/* ops */
-	struct dpu_hw_cdm_ops ops;
-};
-
-/**
- * dpu_hw_cdm - convert base object dpu_hw_base to container
- * @hw: Pointer to base hardware block
- * return: Pointer to hardware block container
- */
-static inline struct dpu_hw_cdm *to_dpu_hw_cdm(struct dpu_hw_blk *hw)
-{
-	return container_of(hw, struct dpu_hw_cdm, base);
-}
-
-/**
- * dpu_hw_cdm_init - initializes the cdm hw driver object.
- * should be called once before accessing every cdm.
- * @idx:  cdm index for which driver object is required
- * @addr: mapped register io address of MDP
- * @m :   pointer to mdss catalog data
- * @hw_mdp:  pointer to mdp top hw driver object
- */
-struct dpu_hw_cdm *dpu_hw_cdm_init(enum dpu_cdm idx,
-		void __iomem *addr,
-		struct dpu_mdss_cfg *m,
-		struct dpu_hw_mdp *hw_mdp);
-
-/**
- * dpu_hw_cdm_destroy - destroys CDM driver context
- * @cdm:   pointer to CDM driver context
- */
-void dpu_hw_cdm_destroy(struct dpu_hw_cdm *cdm);
-
-#endif /*_DPU_HW_CDM_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 06be7cf..b394a18 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -224,19 +224,6 @@ static inline int dpu_hw_ctl_get_bitmask_intf(struct dpu_hw_ctl *ctx,
 	return 0;
 }
 
-static inline int dpu_hw_ctl_get_bitmask_cdm(struct dpu_hw_ctl *ctx,
-		u32 *flushbits, enum dpu_cdm cdm)
-{
-	switch (cdm) {
-	case CDM_0:
-		*flushbits |= BIT(26);
-		break;
-	default:
-		return -EINVAL;
-	}
-	return 0;
-}
-
 static u32 dpu_hw_ctl_poll_reset_status(struct dpu_hw_ctl *ctx, u32 timeout_us)
 {
 	struct dpu_hw_blk_reg_map *c = &ctx->hw;
@@ -485,7 +472,6 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
 	ops->get_bitmask_sspp = dpu_hw_ctl_get_bitmask_sspp;
 	ops->get_bitmask_mixer = dpu_hw_ctl_get_bitmask_mixer;
 	ops->get_bitmask_intf = dpu_hw_ctl_get_bitmask_intf;
-	ops->get_bitmask_cdm = dpu_hw_ctl_get_bitmask_cdm;
 };
 
 static struct dpu_hw_blk_ops dpu_hw_ops = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
index c66a71f..6f313fa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
@@ -142,10 +142,6 @@ struct dpu_hw_ctl_ops {
 		u32 *flushbits,
 		enum dpu_intf blk);
 
-	int (*get_bitmask_cdm)(struct dpu_hw_ctl *ctx,
-		u32 *flushbits,
-		enum dpu_cdm blk);
-
 	/**
 	 * Set all blend stages to disabled
 	 * @ctx       : ctl path ctx pointer
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
index db2798e..b878125 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
@@ -98,23 +98,6 @@ static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp,
 	DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1);
 }
 
-static void dpu_hw_setup_cdm_output(struct dpu_hw_mdp *mdp,
-		struct cdm_output_cfg *cfg)
-{
-	struct dpu_hw_blk_reg_map *c;
-	u32 out_ctl = 0;
-
-	if (!mdp || !cfg)
-		return;
-
-	c = &mdp->hw;
-
-	if (cfg->intf_en)
-		out_ctl |= BIT(19);
-
-	DPU_REG_WRITE(c, MDP_OUT_CTL_0, out_ctl);
-}
-
 static bool dpu_hw_setup_clk_force_ctrl(struct dpu_hw_mdp *mdp,
 		enum dpu_clk_ctrl_type clk_ctrl, bool enable)
 {
@@ -307,7 +290,6 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
 		unsigned long cap)
 {
 	ops->setup_split_pipe = dpu_hw_setup_split_pipe;
-	ops->setup_cdm_output = dpu_hw_setup_cdm_output;
 	ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl;
 	ops->get_danger_status = dpu_hw_get_danger_status;
 	ops->setup_vsync_source = dpu_hw_setup_vsync_source;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
index 899925a..192e338 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
@@ -52,14 +52,6 @@ struct split_pipe_cfg {
 };
 
 /**
- * struct cdm_output_cfg: output configuration for cdm
- * @intf_en   : enable/disable interface output
- */
-struct cdm_output_cfg {
-	bool intf_en;
-};
-
-/**
  * struct dpu_danger_safe_status: danger and safe status signals
  * @mdp: top level status
  * @sspp: source pipe status
@@ -89,7 +81,6 @@ struct dpu_vsync_source_cfg {
  * Assumption is these functions will be called after clocks are enabled.
  * @setup_split_pipe : Programs the pipe control registers
  * @setup_pp_split : Programs the pp split control registers
- * @setup_cdm_output : programs cdm control
  * @setup_traffic_shaper : programs traffic shaper control
  */
 struct dpu_hw_mdp_ops {
@@ -102,14 +93,6 @@ struct dpu_hw_mdp_ops {
 			struct split_pipe_cfg *p);
 
 	/**
-	 * setup_cdm_output() : Setup selection control of the cdm data path
-	 * @mdp  : mdp top context driver
-	 * @cfg  : cdm output configuration
-	 */
-	void (*setup_cdm_output)(struct dpu_hw_mdp *mdp,
-			struct cdm_output_cfg *cfg);
-
-	/**
 	 * setup_traffic_shaper() : Setup traffic shaper control
 	 * @mdp  : mdp top context driver
 	 * @cfg  : traffic shaper configuration
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 388ae65..e08b3bd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -16,7 +16,6 @@
 #include "dpu_kms.h"
 #include "dpu_hw_lm.h"
 #include "dpu_hw_ctl.h"
-#include "dpu_hw_cdm.h"
 #include "dpu_hw_pingpong.h"
 #include "dpu_hw_intf.h"
 #include "dpu_encoder.h"
@@ -214,9 +213,6 @@ static void _dpu_rm_hw_destroy(enum dpu_hw_blk_type type, void *hw)
 	case DPU_HW_BLK_CTL:
 		dpu_hw_ctl_destroy(hw);
 		break;
-	case DPU_HW_BLK_CDM:
-		dpu_hw_cdm_destroy(hw);
-		break;
 	case DPU_HW_BLK_PINGPONG:
 		dpu_hw_pingpong_destroy(hw);
 		break;
@@ -290,9 +286,6 @@ static int _dpu_rm_hw_blk_create(
 	case DPU_HW_BLK_CTL:
 		hw = dpu_hw_ctl_init(id, mmio, cat);
 		break;
-	case DPU_HW_BLK_CDM:
-		hw = dpu_hw_cdm_init(id, mmio, cat, hw_mdp);
-		break;
 	case DPU_HW_BLK_PINGPONG:
 		hw = dpu_hw_pingpong_init(id, mmio, cat);
 		break;
@@ -423,15 +416,6 @@ int dpu_rm_init(struct dpu_rm *rm,
 		}
 	}
 
-	for (i = 0; i < cat->cdm_count; i++) {
-		rc = _dpu_rm_hw_blk_create(rm, cat, mmio, DPU_HW_BLK_CDM,
-				cat->cdm[i].id, &cat->cdm[i]);
-		if (rc) {
-			DPU_ERROR("failed: cdm hw not available\n");
-			goto fail;
-		}
-	}
-
 	return 0;
 
 fail:
@@ -628,55 +612,11 @@ static int _dpu_rm_reserve_ctls(
 	return 0;
 }
 
-static int _dpu_rm_reserve_cdm(
-		struct dpu_rm *rm,
-		struct dpu_rm_rsvp *rsvp,
-		uint32_t id,
-		enum dpu_hw_blk_type type)
-{
-	struct dpu_rm_hw_iter iter;
-
-	DRM_DEBUG_KMS("type %d id %d\n", type, id);
-
-	dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_CDM);
-	while (_dpu_rm_get_hw_locked(rm, &iter)) {
-		const struct dpu_hw_cdm *cdm = to_dpu_hw_cdm(iter.blk->hw);
-		const struct dpu_cdm_cfg *caps = cdm->caps;
-		bool match = false;
-
-		if (RESERVED_BY_OTHER(iter.blk, rsvp))
-			continue;
-
-		if (type == DPU_HW_BLK_INTF && id != INTF_MAX)
-			match = test_bit(id, &caps->intf_connect);
-
-		DRM_DEBUG_KMS("iter: type:%d id:%d enc:%d cdm:%lu match:%d\n",
-			      iter.blk->type, iter.blk->id, rsvp->enc_id,
-			      caps->intf_connect, match);
-
-		if (!match)
-			continue;
-
-		trace_dpu_rm_reserve_cdm(iter.blk->id, iter.blk->type,
-					 rsvp->enc_id);
-		iter.blk->rsvp_nxt = rsvp;
-		break;
-	}
-
-	if (!iter.hw) {
-		DPU_ERROR("couldn't reserve cdm for type %d id %d\n", type, id);
-		return -ENAVAIL;
-	}
-
-	return 0;
-}
-
 static int _dpu_rm_reserve_intf(
 		struct dpu_rm *rm,
 		struct dpu_rm_rsvp *rsvp,
 		uint32_t id,
-		enum dpu_hw_blk_type type,
-		bool needs_cdm)
+		enum dpu_hw_blk_type type)
 {
 	struct dpu_rm_hw_iter iter;
 	int ret = 0;
@@ -704,9 +644,6 @@ static int _dpu_rm_reserve_intf(
 		return -EINVAL;
 	}
 
-	if (needs_cdm)
-		ret = _dpu_rm_reserve_cdm(rm, rsvp, id, type);
-
 	return ret;
 }
 
@@ -723,7 +660,7 @@ static int _dpu_rm_reserve_intf_related_hw(
 			continue;
 		id = i + INTF_0;
 		ret = _dpu_rm_reserve_intf(rm, rsvp, id,
-				DPU_HW_BLK_INTF, hw_res->needs_cdm);
+				DPU_HW_BLK_INTF);
 		if (ret)
 			return ret;
 	}
@@ -769,7 +706,6 @@ static int _dpu_rm_make_next_rsvp(
 		return ret;
 	}
 
-	/* Assign INTFs and blks whose usage is tied to them: CTL & CDM */
 	ret = _dpu_rm_reserve_intf_related_hw(rm, rsvp, &reqs->hw_res);
 	if (ret)
 		return ret;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
index ae0ca50..0be51db 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
@@ -868,10 +868,6 @@
 	TP_printk("id:%d type:%d enc_id:%u", __entry->id, __entry->type,
 		  __entry->enc_id)
 );
-DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_cdm,
-	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id),
-	TP_ARGS(id, type, enc_id)
-);
 DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_intf,
 	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id),
 	TP_ARGS(id, type, enc_id)
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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Re: [PATCH 01/14] drm/msm/dpu: remove debugfs support for misr

[Sean Paul]

On Tue, Aug 28, 2018 at 05:39:50PM -0700, Jeykumar Sankaran wrote:
> Strip down debugfs support for misr data read on layer mixers
> and interfaces.

Could you please start explaining not only the what, but also the why? I'm
certain there's a very good reason for this change, however you don't state it,
so I'm left to figure it out on my own. No one has ever said "your commit
message is too detailed, please make it more vague" :)

> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c           | 139 ---------------------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h           |   6 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        | 127 -------------------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   6 -
>  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  28 -----
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c        |  29 -----
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h        |   7 --
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c          |  29 -----
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h          |   7 --
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c        |   3 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h        |   6 -
>  11 files changed, 387 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index 07c2d15..a4fab042 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -47,8 +47,6 @@
>  #define LEFT_MIXER 0
>  #define RIGHT_MIXER 1
>  
> -#define MISR_BUFF_SIZE			256
> -
>  static inline struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
>  {
>  	struct msm_drm_private *priv;
> @@ -1272,8 +1270,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg)
>  	struct drm_crtc *crtc = arg;
>  	struct dpu_crtc *dpu_crtc;
>  	struct drm_encoder *encoder;
> -	struct dpu_crtc_mixer *m;
> -	u32 i, misr_status;
>  
>  	if (!crtc) {
>  		DPU_ERROR("invalid crtc\n");
> @@ -1294,29 +1290,8 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg)
>  
>  			dpu_encoder_virt_restore(encoder);
>  		}
> -
> -		for (i = 0; i < dpu_crtc->num_mixers; ++i) {
> -			m = &dpu_crtc->mixers[i];
> -			if (!m->hw_lm || !m->hw_lm->ops.setup_misr ||
> -					!dpu_crtc->misr_enable)
> -				continue;
> -
> -			m->hw_lm->ops.setup_misr(m->hw_lm, true,
> -					dpu_crtc->misr_frame_count);
> -		}
>  		break;
>  	case DPU_POWER_EVENT_PRE_DISABLE:

It looks like no one uses PRE_DISABLE now so it can be removed, ditto for
PRE_ENABLE. Since they're called at the same time anyways, lets just merge
PRE/POST_ENABLE/DISABLE into DPU_POWER_EVENT_ENABLE and DPU_POWER_EVENT_DISABLE.

In a separate patch, of course.

> -		for (i = 0; i < dpu_crtc->num_mixers; ++i) {
> -			m = &dpu_crtc->mixers[i];
> -			if (!m->hw_lm || !m->hw_lm->ops.collect_misr ||
> -					!dpu_crtc->misr_enable)
> -				continue;
> -
> -			misr_status = m->hw_lm->ops.collect_misr(m->hw_lm);
> -			dpu_crtc->misr_data[i] = misr_status ? misr_status :
> -							dpu_crtc->misr_data[i];
> -		}
> -		break;
>  	case DPU_POWER_EVENT_POST_DISABLE:
>  		/**
>  		 * Nothing to do. All the planes on the CRTC will be
> @@ -1847,113 +1822,6 @@ static int _dpu_debugfs_status_open(struct inode *inode, struct file *file)
>  	return single_open(file, _dpu_debugfs_status_show, inode->i_private);
>  }
>  
> -static ssize_t _dpu_crtc_misr_setup(struct file *file,
> -		const char __user *user_buf, size_t count, loff_t *ppos)
> -{
> -	struct dpu_crtc *dpu_crtc;
> -	struct dpu_crtc_mixer *m;
> -	int i = 0, rc;
> -	char buf[MISR_BUFF_SIZE + 1];
> -	u32 frame_count, enable;
> -	size_t buff_copy;
> -
> -	if (!file || !file->private_data)
> -		return -EINVAL;
> -
> -	dpu_crtc = file->private_data;
> -	buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
> -	if (copy_from_user(buf, user_buf, buff_copy)) {
> -		DPU_ERROR("buffer copy failed\n");
> -		return -EINVAL;
> -	}
> -
> -	buf[buff_copy] = 0; /* end of string */
> -
> -	if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
> -		return -EINVAL;
> -
> -	rc = _dpu_crtc_power_enable(dpu_crtc, true);
> -	if (rc)
> -		return rc;
> -
> -	mutex_lock(&dpu_crtc->crtc_lock);
> -	dpu_crtc->misr_enable = enable;
> -	dpu_crtc->misr_frame_count = frame_count;
> -	for (i = 0; i < dpu_crtc->num_mixers; ++i) {
> -		dpu_crtc->misr_data[i] = 0;
> -		m = &dpu_crtc->mixers[i];
> -		if (!m->hw_lm || !m->hw_lm->ops.setup_misr)
> -			continue;
> -
> -		m->hw_lm->ops.setup_misr(m->hw_lm, enable, frame_count);
> -	}
> -	mutex_unlock(&dpu_crtc->crtc_lock);
> -	_dpu_crtc_power_enable(dpu_crtc, false);
> -
> -	return count;
> -}
> -
> -static ssize_t _dpu_crtc_misr_read(struct file *file,
> -		char __user *user_buff, size_t count, loff_t *ppos)
> -{
> -	struct dpu_crtc *dpu_crtc;
> -	struct dpu_crtc_mixer *m;
> -	int i = 0, rc;
> -	u32 misr_status;
> -	ssize_t len = 0;
> -	char buf[MISR_BUFF_SIZE + 1] = {'\0'};
> -
> -	if (*ppos)
> -		return 0;
> -
> -	if (!file || !file->private_data)
> -		return -EINVAL;
> -
> -	dpu_crtc = file->private_data;
> -	rc = _dpu_crtc_power_enable(dpu_crtc, true);
> -	if (rc)
> -		return rc;
> -
> -	mutex_lock(&dpu_crtc->crtc_lock);
> -	if (!dpu_crtc->misr_enable) {
> -		len += snprintf(buf + len, MISR_BUFF_SIZE - len,
> -			"disabled\n");
> -		goto buff_check;
> -	}
> -
> -	for (i = 0; i < dpu_crtc->num_mixers; ++i) {
> -		m = &dpu_crtc->mixers[i];
> -		if (!m->hw_lm || !m->hw_lm->ops.collect_misr)
> -			continue;
> -
> -		misr_status = m->hw_lm->ops.collect_misr(m->hw_lm);
> -		dpu_crtc->misr_data[i] = misr_status ? misr_status :
> -							dpu_crtc->misr_data[i];
> -		len += snprintf(buf + len, MISR_BUFF_SIZE - len, "lm idx:%d\n",
> -					m->hw_lm->idx - LM_0);
> -		len += snprintf(buf + len, MISR_BUFF_SIZE - len, "0x%x\n",
> -							dpu_crtc->misr_data[i]);
> -	}
> -
> -buff_check:
> -	if (count <= len) {
> -		len = 0;
> -		goto end;
> -	}
> -
> -	if (copy_to_user(user_buff, buf, len)) {
> -		len = -EFAULT;
> -		goto end;
> -	}
> -
> -	*ppos += len;   /* increase offset */
> -
> -end:
> -	mutex_unlock(&dpu_crtc->crtc_lock);
> -	_dpu_crtc_power_enable(dpu_crtc, false);
> -	return len;
> -}
> -
>  #define DEFINE_DPU_DEBUGFS_SEQ_FOPS(__prefix)                          \
>  static int __prefix ## _open(struct inode *inode, struct file *file)	\
>  {									\
> @@ -2015,11 +1883,6 @@ static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc)
>  		.llseek =	seq_lseek,
>  		.release =	single_release,
>  	};
> -	static const struct file_operations debugfs_misr_fops = {
> -		.open =		simple_open,
> -		.read =		_dpu_crtc_misr_read,
> -		.write =	_dpu_crtc_misr_setup,
> -	};
>  
>  	if (!crtc)
>  		return -EINVAL;
> @@ -2042,8 +1905,6 @@ static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc)
>  			dpu_crtc->debugfs_root,
>  			&dpu_crtc->base,
>  			&dpu_crtc_debugfs_state_fops);
> -	debugfs_create_file("misr_data", 0600, dpu_crtc->debugfs_root,
> -					dpu_crtc, &debugfs_misr_fops);
>  
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> index a896791..53484b1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> @@ -156,9 +156,6 @@ struct dpu_crtc_frame_event {
>   * @event_thread  : Pointer to event handler thread
>   * @event_worker  : Event worker queue
>   * @event_lock    : Spinlock around event handling code
> - * @misr_enable   : boolean entry indicates misr enable/disable status.
> - * @misr_frame_count  : misr frame count provided by client
> - * @misr_data     : store misr data before turning off the clocks.
>   * @phandle: Pointer to power handler
>   * @power_event   : registered power event handle
>   * @cur_perf      : current performance committed to clock/bandwidth driver
> @@ -206,9 +203,6 @@ struct dpu_crtc {
>  
>  	/* for handling internal event thread */
>  	spinlock_t event_lock;
> -	bool misr_enable;
> -	u32 misr_frame_count;
> -	u32 misr_data[CRTC_DUAL_MIXERS];
>  
>  	struct dpu_power_handle *phandle;
>  	struct dpu_power_event *power_event;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 5b0e944..991b22c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -65,8 +65,6 @@
>  
>  #define MAX_CHANNELS_PER_ENC 2
>  
> -#define MISR_BUFF_SIZE			256
> -
>  #define IDLE_SHORT_TIMEOUT	1
>  
>  #define MAX_VDISPLAY_SPLIT 1080
> @@ -161,8 +159,6 @@ enum dpu_enc_rc_states {
>   * @frame_done_timer:		watchdog timer for frame done event
>   * @vsync_event_timer:		vsync timer
>   * @disp_info:			local copy of msm_display_info struct
> - * @misr_enable:		misr enable/disable status
> - * @misr_frame_count:		misr frame count before start capturing the data
>   * @idle_pc_supported:		indicate if idle power collaps is supported
>   * @rc_lock:			resource control mutex lock to protect
>   *				virt encoder over various state changes
> @@ -202,8 +198,6 @@ struct dpu_encoder_virt {
>  	struct timer_list vsync_event_timer;
>  
>  	struct msm_display_info disp_info;
> -	bool misr_enable;
> -	u32 misr_frame_count;
>  
>  	bool idle_pc_supported;
>  	struct mutex rc_lock;
> @@ -1193,11 +1187,6 @@ static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
>  			if (phys->ops.enable)
>  				phys->ops.enable(phys);
>  		}
> -
> -		if (dpu_enc->misr_enable && (dpu_enc->disp_info.capabilities &
> -		     MSM_DISPLAY_CAP_VID_MODE) && phys->ops.setup_misr)
> -			phys->ops.setup_misr(phys, true,
> -						dpu_enc->misr_frame_count);
>  	}
>  
>  	if (dpu_enc->cur_master->ops.enable)
> @@ -1949,113 +1938,6 @@ static int _dpu_encoder_debugfs_status_open(struct inode *inode,
>  	return single_open(file, _dpu_encoder_status_show, inode->i_private);
>  }
>  
> -static ssize_t _dpu_encoder_misr_setup(struct file *file,
> -		const char __user *user_buf, size_t count, loff_t *ppos)
> -{
> -	struct dpu_encoder_virt *dpu_enc;
> -	int i = 0, rc;
> -	char buf[MISR_BUFF_SIZE + 1];
> -	size_t buff_copy;
> -	u32 frame_count, enable;
> -
> -	if (!file || !file->private_data)
> -		return -EINVAL;
> -
> -	dpu_enc = file->private_data;
> -
> -	buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
> -	if (copy_from_user(buf, user_buf, buff_copy))
> -		return -EINVAL;
> -
> -	buf[buff_copy] = 0; /* end of string */
> -
> -	if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
> -		return -EINVAL;
> -
> -	rc = _dpu_encoder_power_enable(dpu_enc, true);
> -	if (rc)
> -		return rc;
> -
> -	mutex_lock(&dpu_enc->enc_lock);
> -	dpu_enc->misr_enable = enable;
> -	dpu_enc->misr_frame_count = frame_count;
> -	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
> -		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
> -
> -		if (!phys || !phys->ops.setup_misr)
> -			continue;
> -
> -		phys->ops.setup_misr(phys, enable, frame_count);
> -	}
> -	mutex_unlock(&dpu_enc->enc_lock);
> -	_dpu_encoder_power_enable(dpu_enc, false);
> -
> -	return count;
> -}
> -
> -static ssize_t _dpu_encoder_misr_read(struct file *file,
> -		char __user *user_buff, size_t count, loff_t *ppos)
> -{
> -	struct dpu_encoder_virt *dpu_enc;
> -	int i = 0, len = 0;
> -	char buf[MISR_BUFF_SIZE + 1] = {'\0'};
> -	int rc;
> -
> -	if (*ppos)
> -		return 0;
> -
> -	if (!file || !file->private_data)
> -		return -EINVAL;
> -
> -	dpu_enc = file->private_data;
> -
> -	rc = _dpu_encoder_power_enable(dpu_enc, true);
> -	if (rc)
> -		return rc;
> -
> -	mutex_lock(&dpu_enc->enc_lock);
> -	if (!dpu_enc->misr_enable) {
> -		len += snprintf(buf + len, MISR_BUFF_SIZE - len,
> -			"disabled\n");
> -		goto buff_check;
> -	} else if (dpu_enc->disp_info.capabilities &
> -						~MSM_DISPLAY_CAP_VID_MODE) {
> -		len += snprintf(buf + len, MISR_BUFF_SIZE - len,
> -			"unsupported\n");
> -		goto buff_check;
> -	}
> -
> -	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
> -		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
> -
> -		if (!phys || !phys->ops.collect_misr)
> -			continue;
> -
> -		len += snprintf(buf + len, MISR_BUFF_SIZE - len,
> -			"Intf idx:%d\n", phys->intf_idx - INTF_0);
> -		len += snprintf(buf + len, MISR_BUFF_SIZE - len, "0x%x\n",
> -					phys->ops.collect_misr(phys));
> -	}
> -
> -buff_check:
> -	if (count <= len) {
> -		len = 0;
> -		goto end;
> -	}
> -
> -	if (copy_to_user(user_buff, buf, len)) {
> -		len = -EFAULT;
> -		goto end;
> -	}
> -
> -	*ppos += len;   /* increase offset */
> -
> -end:
> -	mutex_unlock(&dpu_enc->enc_lock);
> -	_dpu_encoder_power_enable(dpu_enc, false);
> -	return len;
> -}
> -
>  static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
>  {
>  	struct dpu_encoder_virt *dpu_enc;
> @@ -2070,12 +1952,6 @@ static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
>  		.release =	single_release,
>  	};
>  
> -	static const struct file_operations debugfs_misr_fops = {
> -		.open = simple_open,
> -		.read = _dpu_encoder_misr_read,
> -		.write = _dpu_encoder_misr_setup,
> -	};
> -
>  	char name[DPU_NAME_SIZE];
>  
>  	if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
> @@ -2099,9 +1975,6 @@ static int _dpu_encoder_init_debugfs(struct drm_encoder *drm_enc)
>  	debugfs_create_file("status", 0600,
>  		dpu_enc->debugfs_root, dpu_enc, &debugfs_status_fops);
>  
> -	debugfs_create_file("misr_data", 0600,
> -		dpu_enc->debugfs_root, dpu_enc, &debugfs_misr_fops);
> -
>  	for (i = 0; i < dpu_enc->num_phys_encs; i++)
>  		if (dpu_enc->phys_encs[i] &&
>  				dpu_enc->phys_encs[i]->ops.late_register)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> index c7df8aa..b3917e0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> @@ -114,8 +114,6 @@ struct dpu_encoder_virt_ops {
>   * @handle_post_kickoff:	Do any work necessary post-kickoff work
>   * @trigger_start:		Process start event on physical encoder
>   * @needs_single_flush:		Whether encoder slaves need to be flushed
> - * @setup_misr:		Sets up MISR, enable and disables based on sysfs
> - * @collect_misr:		Collects MISR data on frame update
>   * @hw_reset:			Issue HW recovery such as CTL reset and clear
>   *				DPU_ENC_ERR_NEEDS_HW_RESET state
>   * @irq_control:		Handler to enable/disable all the encoder IRQs
> @@ -154,10 +152,6 @@ struct dpu_encoder_phys_ops {
>  	void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);
>  	void (*trigger_start)(struct dpu_encoder_phys *phys_enc);
>  	bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc);
> -
> -	void (*setup_misr)(struct dpu_encoder_phys *phys_encs,
> -				bool enable, u32 frame_count);
> -	u32 (*collect_misr)(struct dpu_encoder_phys *phys_enc);
>  	void (*hw_reset)(struct dpu_encoder_phys *phys_enc);
>  	void (*irq_control)(struct dpu_encoder_phys *phys, bool enable);
>  	void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index 14fc7c2..6fc3d3f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -756,32 +756,6 @@ static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc,
>  	}
>  }
>  
> -static void dpu_encoder_phys_vid_setup_misr(struct dpu_encoder_phys *phys_enc,
> -						bool enable, u32 frame_count)
> -{
> -	struct dpu_encoder_phys_vid *vid_enc;
> -
> -	if (!phys_enc)
> -		return;
> -	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
> -
> -	if (vid_enc->hw_intf && vid_enc->hw_intf->ops.setup_misr)
> -		vid_enc->hw_intf->ops.setup_misr(vid_enc->hw_intf,
> -							enable, frame_count);
> -}
> -
> -static u32 dpu_encoder_phys_vid_collect_misr(struct dpu_encoder_phys *phys_enc)
> -{
> -	struct dpu_encoder_phys_vid *vid_enc;
> -
> -	if (!phys_enc)
> -		return 0;
> -	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
> -
> -	return vid_enc->hw_intf && vid_enc->hw_intf->ops.collect_misr ?
> -		vid_enc->hw_intf->ops.collect_misr(vid_enc->hw_intf) : 0;
> -}
> -
>  static int dpu_encoder_phys_vid_get_line_count(
>  		struct dpu_encoder_phys *phys_enc)
>  {
> @@ -817,8 +791,6 @@ static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops)
>  	ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff;
>  	ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff;
>  	ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush;
> -	ops->setup_misr = dpu_encoder_phys_vid_setup_misr;
> -	ops->collect_misr = dpu_encoder_phys_vid_collect_misr;
>  	ops->hw_reset = dpu_encoder_helper_hw_reset;
>  	ops->get_line_count = dpu_encoder_phys_vid_get_line_count;
>  }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> index d280df5..9c6bba0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> @@ -65,9 +65,6 @@
>  #define   INTF_FRAME_COUNT              0x0AC
>  #define   INTF_LINE_COUNT               0x0B0
>  
> -#define INTF_MISR_CTRL			0x180
> -#define INTF_MISR_SIGNATURE		0x184
> -
>  static struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf,
>  		struct dpu_mdss_cfg *m,
>  		void __iomem *addr,
> @@ -246,30 +243,6 @@ static void dpu_hw_intf_get_status(
>  	}
>  }
>  
> -static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf,
> -						bool enable, u32 frame_count)
> -{
> -	struct dpu_hw_blk_reg_map *c = &intf->hw;
> -	u32 config = 0;
> -
> -	DPU_REG_WRITE(c, INTF_MISR_CTRL, MISR_CTRL_STATUS_CLEAR);
> -	/* clear misr data */
> -	wmb();
> -
> -	if (enable)
> -		config = (frame_count & MISR_FRAME_COUNT_MASK) |
> -			MISR_CTRL_ENABLE | INTF_MISR_CTRL_FREE_RUN_MASK;
> -
> -	DPU_REG_WRITE(c, INTF_MISR_CTRL, config);
> -}
> -
> -static u32 dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf)
> -{
> -	struct dpu_hw_blk_reg_map *c = &intf->hw;
> -
> -	return DPU_REG_READ(c, INTF_MISR_SIGNATURE);
> -}
> -
>  static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf)
>  {
>  	struct dpu_hw_blk_reg_map *c;
> @@ -289,8 +262,6 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
>  	ops->setup_prg_fetch  = dpu_hw_intf_setup_prg_fetch;
>  	ops->get_status = dpu_hw_intf_get_status;
>  	ops->enable_timing = dpu_hw_intf_enable_timing_engine;
> -	ops->setup_misr = dpu_hw_intf_setup_misr;
> -	ops->collect_misr = dpu_hw_intf_collect_misr;
>  	ops->get_line_count = dpu_hw_intf_get_line_count;
>  }
>  
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> index a79d735..3b77df4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> @@ -59,8 +59,6 @@ struct intf_status {
>   * @ setup_prog_fetch : enables/disables the programmable fetch logic
>   * @ enable_timing: enable/disable timing engine
>   * @ get_status: returns if timing engine is enabled or not
> - * @ setup_misr: enables/disables MISR in HW register
> - * @ collect_misr: reads and stores MISR data from HW register
>   * @ get_line_count: reads current vertical line counter
>   */
>  struct dpu_hw_intf_ops {
> @@ -77,11 +75,6 @@ struct dpu_hw_intf_ops {
>  	void (*get_status)(struct dpu_hw_intf *intf,
>  			struct intf_status *status);
>  
> -	void (*setup_misr)(struct dpu_hw_intf *intf,
> -			bool enable, u32 frame_count);
> -
> -	u32 (*collect_misr)(struct dpu_hw_intf *intf);
> -
>  	u32 (*get_line_count)(struct dpu_hw_intf *intf);
>  };
>  
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
> index 4ab72b0..acb8dc8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
> @@ -34,9 +34,6 @@
>  #define LM_BLEND0_FG_ALPHA               0x04
>  #define LM_BLEND0_BG_ALPHA               0x08
>  
> -#define LM_MISR_CTRL			0x310
> -#define LM_MISR_SIGNATURE		0x314
> -
>  static struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer,
>  		struct dpu_mdss_cfg *m,
>  		void __iomem *addr,
> @@ -171,30 +168,6 @@ static void dpu_hw_lm_gc(struct dpu_hw_mixer *mixer,
>  {
>  }
>  
> -static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx,
> -				bool enable, u32 frame_count)
> -{
> -	struct dpu_hw_blk_reg_map *c = &ctx->hw;
> -	u32 config = 0;
> -
> -	DPU_REG_WRITE(c, LM_MISR_CTRL, MISR_CTRL_STATUS_CLEAR);
> -	/* clear misr data */
> -	wmb();
> -
> -	if (enable)
> -		config = (frame_count & MISR_FRAME_COUNT_MASK) |
> -			MISR_CTRL_ENABLE | INTF_MISR_CTRL_FREE_RUN_MASK;
> -
> -	DPU_REG_WRITE(c, LM_MISR_CTRL, config);
> -}
> -
> -static u32 dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx)
> -{
> -	struct dpu_hw_blk_reg_map *c = &ctx->hw;
> -
> -	return DPU_REG_READ(c, LM_MISR_SIGNATURE);
> -}
> -
>  static void _setup_mixer_ops(struct dpu_mdss_cfg *m,
>  		struct dpu_hw_lm_ops *ops,
>  		unsigned long features)
> @@ -207,8 +180,6 @@ static void _setup_mixer_ops(struct dpu_mdss_cfg *m,
>  	ops->setup_alpha_out = dpu_hw_lm_setup_color3;
>  	ops->setup_border_color = dpu_hw_lm_setup_border_color;
>  	ops->setup_gc = dpu_hw_lm_gc;
> -	ops->setup_misr = dpu_hw_lm_setup_misr;
> -	ops->collect_misr = dpu_hw_lm_collect_misr;
>  };
>  
>  static struct dpu_hw_blk_ops dpu_hw_ops = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
> index e29e5da..5b036ac 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
> @@ -66,13 +66,6 @@ struct dpu_hw_lm_ops {
>  	 */
>  	void (*setup_gc)(struct dpu_hw_mixer *mixer,
>  			void *cfg);
> -
> -	/* setup_misr: enables/disables MISR in HW register */
> -	void (*setup_misr)(struct dpu_hw_mixer *ctx,
> -			bool enable, u32 frame_count);
> -
> -	/* collect_misr: reads and stores MISR data from HW register */
> -	u32 (*collect_misr)(struct dpu_hw_mixer *ctx);
>  };
>  
>  struct dpu_hw_mixer {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
> index 4cabae4..cb5c017 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
> @@ -50,9 +50,6 @@
>  #define QSEED3_CLK_CTRL0                   0x54
>  #define QSEED3_CLK_CTRL1                   0x58
>  #define QSEED3_CLK_STATUS                  0x5C
> -#define QSEED3_MISR_CTRL                   0x70
> -#define QSEED3_MISR_SIGNATURE_0            0x74
> -#define QSEED3_MISR_SIGNATURE_1            0x78
>  #define QSEED3_PHASE_INIT_Y_H              0x90
>  #define QSEED3_PHASE_INIT_Y_V              0x94
>  #define QSEED3_PHASE_INIT_UV_H             0x98
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> index 1240f50..cb02041 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> @@ -325,12 +325,6 @@ void dpu_reg_write(struct dpu_hw_blk_reg_map *c,
>  #define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off)
>  #define DPU_REG_READ(c, off) dpu_reg_read(c, off)
>  
> -#define MISR_FRAME_COUNT_MASK		0xFF
> -#define MISR_CTRL_ENABLE		BIT(8)
> -#define MISR_CTRL_STATUS		BIT(9)
> -#define MISR_CTRL_STATUS_CLEAR		BIT(10)
> -#define INTF_MISR_CTRL_FREE_RUN_MASK	BIT(31)
> -
>  void *dpu_hw_util_get_dir(void);
>  
>  void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [PATCH 05/14] drm/msm/dpu: enable master-slave encoders explicitly

[Sean Paul]

On Tue, Aug 28, 2018 at 05:39:54PM -0700, Jeykumar Sankaran wrote:
> Identify slave-master encoders during initialization and enable
> the encoders explicitly as the current logic has redundant and
> ambiguous loops.

Please include a "Changes in vX" section so I don't need to figure it out myself.

> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 46 ++++++++++-------------------
>  1 file changed, 15 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 991b22c..b223bd2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -180,6 +180,7 @@ struct dpu_encoder_virt {
>  	unsigned int num_phys_encs;
>  	struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
>  	struct dpu_encoder_phys *cur_master;
> +	struct dpu_encoder_phys *cur_slave;
>  	struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
>  
>  	bool intfs_swapped;
> @@ -1141,7 +1142,8 @@ void dpu_encoder_virt_restore(struct drm_encoder *drm_enc)
>  static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
>  {
>  	struct dpu_encoder_virt *dpu_enc = NULL;
> -	int i, ret = 0;
> +	struct dpu_encoder_phys *phys  = NULL;
> +	int ret = 0;
>  	struct drm_display_mode *cur_mode = NULL;
>  
>  	if (!drm_enc) {
> @@ -1154,21 +1156,14 @@ static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
>  	trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
>  			     cur_mode->vdisplay);
>  
> -	dpu_enc->cur_master = NULL;
> -	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
> -		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
> +	/* always enable slave encoder before master */
> +	phys = dpu_enc->cur_slave;

I think this variable makes things less readable. It made sense in the loop since
you're indented an extra level and they're obfuscated anyways, but since they're
explicit now, could you please just use dpu_enc->cur_slave/master directly?

With this nit and the added changelog in the commit addressed,

Reviewed-by: Sean Paul <seanpaul@chromium.org>


> +	if (phys && phys->ops.enable)
> +		phys->ops.enable(phys);
>  
> -		if (phys && phys->ops.is_master && phys->ops.is_master(phys)) {
> -			DPU_DEBUG_ENC(dpu_enc, "master is now idx %d\n", i);
> -			dpu_enc->cur_master = phys;
> -			break;
> -		}
> -	}
> -
> -	if (!dpu_enc->cur_master) {
> -		DPU_ERROR("virt encoder has no master! num_phys %d\n", i);
> -		return;
> -	}
> +	phys = dpu_enc->cur_master;
> +	if (phys && phys->ops.enable)
> +		phys->ops.enable(phys);
>  
>  	ret = dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_KICKOFF);
>  	if (ret) {
> @@ -1177,21 +1172,6 @@ static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
>  		return;
>  	}
>  
> -	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
> -		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
> -
> -		if (!phys)
> -			continue;
> -
> -		if (phys != dpu_enc->cur_master) {
> -			if (phys->ops.enable)
> -				phys->ops.enable(phys);
> -		}
> -	}
> -
> -	if (dpu_enc->cur_master->ops.enable)
> -		dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
> -
>  	_dpu_encoder_virt_enable_helper(drm_enc);
>  }
>  
> @@ -2062,6 +2042,11 @@ static int dpu_encoder_virt_add_phys_encs(
>  		++dpu_enc->num_phys_encs;
>  	}
>  
> +	if (params->split_role == ENC_ROLE_SLAVE)
> +		dpu_enc->cur_slave = enc;
> +	else
> +		dpu_enc->cur_master = enc;
> +
>  	return 0;
>  }
>  
> @@ -2228,7 +2213,6 @@ int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc,
>  	if (ret)
>  		goto fail;
>  
> -	dpu_enc->cur_master = NULL;
>  	spin_lock_init(&dpu_enc->enc_spinlock);
>  
>  	atomic_set(&dpu_enc->frame_done_timeout, 0);
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
dri-devel mailing list
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Re: [PATCH 07/14] drm/msm/dpu: iterate for assigned hw ctl in virtual encoder

[Sean Paul]

On Tue, Aug 28, 2018 at 05:39:56PM -0700, Jeykumar Sankaran wrote:
> Instead of iterating for hw ctrl per physical encoder, this
> patch moves the iterations and assignment to the virtual encoder.
> 

Missing "Changes in" section as well as _why_ you're doing this in your
description.

> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        | 22 +++++++++++++++++++---
>  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   | 19 -------------------
>  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 19 -------------------
>  3 files changed, 19 insertions(+), 41 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index b223bd2..dbf669e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -1011,9 +1011,10 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
>  	struct dpu_kms *dpu_kms;
>  	struct list_head *connector_list;
>  	struct drm_connector *conn = NULL, *conn_iter;
> -	struct dpu_rm_hw_iter pp_iter;
> +	struct dpu_rm_hw_iter pp_iter, ctl_iter;
>  	struct msm_display_topology topology;
>  	enum dpu_rm_topology_name topology_name;
> +	struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL };
>  	int i = 0, ret;
>  
>  	if (!drm_enc) {
> @@ -1061,17 +1062,32 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
>  		dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) pp_iter.hw;
>  	}
>  
> +	dpu_rm_init_hw_iter(&ctl_iter, drm_enc->base.id, DPU_HW_BLK_CTL);
> +	for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
> +		if (!dpu_rm_get_hw(&dpu_kms->rm, &ctl_iter))
> +			break;
> +		hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw;
> +	}
> +
>  	topology_name = dpu_rm_get_topology_name(topology);
>  	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
>  		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
>  
>  		if (phys) {
>  			if (!dpu_enc->hw_pp[i]) {
> -				DPU_ERROR_ENC(dpu_enc,
> -				    "invalid pingpong block for the encoder\n");
> +				DPU_ERROR_ENC(dpu_enc, "no pp block assigned"
> +					     "at idx: %d\n", i);
>  				return;
>  			}
>  			phys->hw_pp = dpu_enc->hw_pp[i];
> +
> +			if (!hw_ctl[i]) {

Should you check this before you assign hw_pp?

> +				DPU_ERROR_ENC(dpu_enc, "no ctl block assigned"
> +					     "at idx: %d\n", i);
> +				return;
> +			}
> +			phys->hw_ctl = hw_ctl[i];
> +
>  			phys->connector = conn->state->connector;
>  			phys->topology_name = topology_name;
>  			if (phys->ops.mode_set)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> index c8c4612..5c89868 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> @@ -196,9 +196,6 @@ static void dpu_encoder_phys_cmd_mode_set(
>  {
>  	struct dpu_encoder_phys_cmd *cmd_enc =
>  		to_dpu_encoder_phys_cmd(phys_enc);
> -	struct dpu_rm *rm = &phys_enc->dpu_kms->rm;
> -	struct dpu_rm_hw_iter iter;
> -	int i, instance;
>  
>  	if (!phys_enc || !mode || !adj_mode) {
>  		DPU_ERROR("invalid args\n");
> @@ -208,22 +205,6 @@ static void dpu_encoder_phys_cmd_mode_set(
>  	DPU_DEBUG_CMDENC(cmd_enc, "caching mode:\n");
>  	drm_mode_debug_printmodeline(adj_mode);
>  
> -	instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0;
> -
> -	/* Retrieve previously allocated HW Resources. Shouldn't fail */
> -	dpu_rm_init_hw_iter(&iter, phys_enc->parent->base.id, DPU_HW_BLK_CTL);
> -	for (i = 0; i <= instance; i++) {
> -		if (dpu_rm_get_hw(rm, &iter))
> -			phys_enc->hw_ctl = (struct dpu_hw_ctl *)iter.hw;
> -	}
> -
> -	if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
> -		DPU_ERROR_CMDENC(cmd_enc, "failed to init ctl: %ld\n",
> -				PTR_ERR(phys_enc->hw_ctl));
> -		phys_enc->hw_ctl = NULL;
> -		return;
> -	}
> -
>  	_dpu_encoder_phys_cmd_setup_irq_hw_idx(phys_enc);
>  }
>  
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index ecb8c65..ca0963c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -395,9 +395,6 @@ static void dpu_encoder_phys_vid_mode_set(
>  		struct drm_display_mode *mode,
>  		struct drm_display_mode *adj_mode)
>  {
> -	struct dpu_rm *rm;
> -	struct dpu_rm_hw_iter iter;
> -	int i, instance;
>  	struct dpu_encoder_phys_vid *vid_enc;
>  
>  	if (!phys_enc || !phys_enc->dpu_kms) {
> @@ -405,7 +402,6 @@ static void dpu_encoder_phys_vid_mode_set(
>  		return;
>  	}
>  
> -	rm = &phys_enc->dpu_kms->rm;
>  	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
>  
>  	if (adj_mode) {
> @@ -414,21 +410,6 @@ static void dpu_encoder_phys_vid_mode_set(
>  		DPU_DEBUG_VIDENC(vid_enc, "caching mode:\n");
>  	}
>  
> -	instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0;
> -
> -	/* Retrieve previously allocated HW Resources. Shouldn't fail */
> -	dpu_rm_init_hw_iter(&iter, phys_enc->parent->base.id, DPU_HW_BLK_CTL);
> -	for (i = 0; i <= instance; i++) {
> -		if (dpu_rm_get_hw(rm, &iter))
> -			phys_enc->hw_ctl = (struct dpu_hw_ctl *)iter.hw;
> -	}
> -	if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
> -		DPU_ERROR_VIDENC(vid_enc, "failed to init ctl, %ld\n",
> -				PTR_ERR(phys_enc->hw_ctl));
> -		phys_enc->hw_ctl = NULL;
> -		return;
> -	}
> -
>  	_dpu_encoder_phys_vid_setup_irq_hw_idx(phys_enc);
>  }
>  
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
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Re: [PATCH 08/14] drm/msm/dpu: avoid querying for hw intf before assignment

[Sean Paul]

On Tue, Aug 28, 2018 at 05:39:57PM -0700, Jeykumar Sankaran wrote:
> Resource manager assigns hw_intf blocks for the encoder only on
> modeset. If queried for hw_intf objects during init, it will be
> NULL. Since hw_intf objects are needed only during encoder enable,

s/during/after/ it looks like you need it on disable as well.

> defer the query to encoder enable which will be triggered after
> modeset.
> 

Missing changelog again.

With that,

Reviewed-by: Sean Paul <seanpaul@chromium.org>


> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> ---
>  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 53 +++++++---------------
>  1 file changed, 16 insertions(+), 37 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index ca0963c..6de13f4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -462,7 +462,7 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
>  {
>  	struct msm_drm_private *priv;
>  	struct dpu_encoder_phys_vid *vid_enc;
> -	struct dpu_hw_intf *intf;
> +	struct dpu_rm_hw_iter iter;
>  	struct dpu_hw_ctl *ctl;
>  	u32 flush_mask = 0;
>  
> @@ -474,11 +474,20 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
>  	priv = phys_enc->parent->dev->dev_private;
>  
>  	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
> -	intf = vid_enc->hw_intf;
>  	ctl = phys_enc->hw_ctl;
> -	if (!vid_enc->hw_intf || !phys_enc->hw_ctl) {
> -		DPU_ERROR("invalid hw_intf %d hw_ctl %d\n",
> -				vid_enc->hw_intf != 0, phys_enc->hw_ctl != 0);
> +
> +	dpu_rm_init_hw_iter(&iter, phys_enc->parent->base.id, DPU_HW_BLK_INTF);
> +	while (dpu_rm_get_hw(&phys_enc->dpu_kms->rm, &iter)) {
> +		struct dpu_hw_intf *hw_intf = (struct dpu_hw_intf *)iter.hw;
> +
> +		if (hw_intf->idx == phys_enc->intf_idx) {
> +			vid_enc->hw_intf = hw_intf;
> +			break;
> +		}
> +	}
> +
> +	if (!vid_enc->hw_intf) {
> +		DPU_ERROR("hw_intf not assigned\n");
>  		return;
>  	}
>  
> @@ -500,7 +509,7 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
>  		!dpu_encoder_phys_vid_is_master(phys_enc))
>  		goto skip_flush;
>  
> -	ctl->ops.get_bitmask_intf(ctl, &flush_mask, intf->idx);
> +	ctl->ops.get_bitmask_intf(ctl, &flush_mask, vid_enc->hw_intf->idx);
>  	ctl->ops.update_pending_flush(ctl, flush_mask);
>  
>  skip_flush:
> @@ -531,22 +540,13 @@ static void dpu_encoder_phys_vid_get_hw_resources(
>  		struct dpu_encoder_hw_resources *hw_res,
>  		struct drm_connector_state *conn_state)
>  {
> -	struct dpu_encoder_phys_vid *vid_enc;
> -
>  	if (!phys_enc || !hw_res) {
>  		DPU_ERROR("invalid arg(s), enc %d hw_res %d conn_state %d\n",
>  				phys_enc != 0, hw_res != 0, conn_state != 0);
>  		return;
>  	}
>  
> -	vid_enc = to_dpu_encoder_phys_vid(phys_enc);
> -	if (!vid_enc->hw_intf) {
> -		DPU_ERROR("invalid arg(s), hw_intf\n");
> -		return;
> -	}
> -
> -	DPU_DEBUG_VIDENC(vid_enc, "\n");
> -	hw_res->intfs[vid_enc->hw_intf->idx - INTF_0] = INTF_MODE_VIDEO;
> +	hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_VIDEO;
>  }
>  
>  static int _dpu_encoder_phys_vid_wait_for_vblank(
> @@ -781,7 +781,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
>  {
>  	struct dpu_encoder_phys *phys_enc = NULL;
>  	struct dpu_encoder_phys_vid *vid_enc = NULL;
> -	struct dpu_rm_hw_iter iter;
>  	struct dpu_encoder_irq *irq;
>  	int i, ret = 0;
>  
> @@ -801,26 +800,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
>  	phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
>  	phys_enc->intf_idx = p->intf_idx;
>  
> -	/**
> -	 * hw_intf resource permanently assigned to this encoder
> -	 * Other resources allocated at atomic commit time by use case
> -	 */
> -	dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_INTF);
> -	while (dpu_rm_get_hw(&p->dpu_kms->rm, &iter)) {
> -		struct dpu_hw_intf *hw_intf = (struct dpu_hw_intf *)iter.hw;
> -
> -		if (hw_intf->idx == p->intf_idx) {
> -			vid_enc->hw_intf = hw_intf;
> -			break;
> -		}
> -	}
> -
> -	if (!vid_enc->hw_intf) {
> -		ret = -EINVAL;
> -		DPU_ERROR("failed to get hw_intf\n");
> -		goto fail;
> -	}
> -
>  	DPU_DEBUG_VIDENC(vid_enc, "\n");
>  
>  	dpu_encoder_phys_vid_init_ops(&phys_enc->ops);
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
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Re: [PATCH 09/14] drm/msm/dpu: make crtc get_mixer_width helper static

[Sean Paul]

On Tue, Aug 28, 2018 at 05:39:58PM -0700, Jeykumar Sankaran wrote:
> Mark CRTC get_mixer_width helper API static as it is
> not used outside the file.
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 21 ++++++++++++++++++---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 18 ------------------
>  2 files changed, 18 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index 92eda3e..e061847 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -47,6 +47,20 @@
>  #define LEFT_MIXER 0
>  #define RIGHT_MIXER 1
>  
> +static inline int _dpu_crtc_get_mixer_width(struct dpu_crtc *dpu_crtc,
> +	struct dpu_crtc_state *cstate, struct drm_display_mode *mode)
> +{
> +	u32 mixer_width;
> +
> +	if (!dpu_crtc || !cstate || !mode)
> +		return 0;
> +
> +	mixer_width = (cstate->num_mixers == CRTC_DUAL_MIXERS ?
> +			mode->hdisplay / CRTC_DUAL_MIXERS : mode->hdisplay);
> +
> +	return mixer_width;
> +}

This function feels a little too beefy to be inline.

However(!!): 
 - None of the NULL checks are needed
 - the mixer_width local variable isn't needed
 - dpu_crtc isn't even used
 - the divisor is always == cstate->num_mixers

So you can actually get an inline-worth function out of this, all of that
simplifies down to:

static inline int dpu_crtc_get_mixer_width(struct dpu_crtc_state *cstate,
                                           struct drm_display_mode *mode)
{
        return mode->hdisplay / cstate->num_mixers;
}

> +
>  static inline struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
>  {
>  	struct msm_drm_private *priv;
> @@ -601,7 +615,8 @@ static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
>  	cstate = to_dpu_crtc_state(state);
>  
>  	adj_mode = &state->adjusted_mode;
> -	crtc_split_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, adj_mode);
> +	crtc_split_width = _dpu_crtc_get_mixer_width(dpu_crtc, cstate,
> +						    adj_mode);
>  
>  	for (i = 0; i < dpu_crtc->num_mixers; i++) {
>  		struct drm_rect *r = &cstate->lm_bounds[i];
> @@ -1299,7 +1314,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
>  
>  	memset(pipe_staged, 0, sizeof(pipe_staged));
>  
> -	mixer_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
> +	mixer_width = _dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
>  
>  	_dpu_crtc_setup_lm_bounds(crtc, state);
>  
> @@ -1536,7 +1551,7 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
>  
>  	mutex_lock(&dpu_crtc->crtc_lock);
>  	mode = &crtc->state->adjusted_mode;
> -	out_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
> +	out_width = _dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
>  
>  	seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id,
>  				mode->hdisplay, mode->vdisplay);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> index ec9c538..5e4dc5c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> @@ -238,24 +238,6 @@ struct dpu_crtc_state {
>  	container_of(x, struct dpu_crtc_state, base)
>  
>  /**
> - * dpu_crtc_get_mixer_width - get the mixer width
> - * Mixer width will be same as panel width(/2 for split)
> - */
> -static inline int dpu_crtc_get_mixer_width(struct dpu_crtc *dpu_crtc,
> -	struct dpu_crtc_state *cstate, struct drm_display_mode *mode)
> -{
> -	u32 mixer_width;
> -
> -	if (!dpu_crtc || !cstate || !mode)
> -		return 0;
> -
> -	mixer_width = (dpu_crtc->num_mixers == CRTC_DUAL_MIXERS ?
> -			mode->hdisplay / CRTC_DUAL_MIXERS : mode->hdisplay);
> -
> -	return mixer_width;
> -}
> -
> -/**
>   * dpu_crtc_get_mixer_height - get the mixer height
>   * Mixer height will be same as panel height
>   */
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
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Re: [PATCH 10/14] drm/msm/dpu: move hw resource tracking to crtc state

[Sean Paul]

On Tue, Aug 28, 2018 at 05:39:59PM -0700, Jeykumar Sankaran wrote:
> Prep changes for state based resource management.
> 
> Moves all the hw block tracking for the crtc to the state
> object.

Changes in v4...

> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 60 ++++++++++++++++++--------------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 22 ++++++------
>  2 files changed, 44 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index e061847..7ab320d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -163,9 +163,9 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
>  	crtc_state = to_dpu_crtc_state(crtc->state);
>  
>  	lm_horiz_position = 0;
> -	for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
> +	for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) {
>  		const struct drm_rect *lm_roi = &crtc_state->lm_bounds[lm_idx];
> -		struct dpu_hw_mixer *hw_lm = dpu_crtc->mixers[lm_idx].hw_lm;
> +		struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm;
>  		struct dpu_hw_mixer_cfg cfg;
>  
>  		if (!lm_roi || !drm_rect_visible(lm_roi))
> @@ -246,7 +246,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
>  					   fb ? fb->modifier : 0);
>  
>  		/* blend config update */
> -		for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
> +		for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
>  			_dpu_crtc_setup_blend_cfg(mixer + lm_idx,
>  						pstate, format);
>  
> @@ -270,7 +270,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
>  static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
>  {
>  	struct dpu_crtc *dpu_crtc;
> -	struct dpu_crtc_state *dpu_crtc_state;
> +	struct dpu_crtc_state *cstate;
>  	struct dpu_crtc_mixer *mixer;
>  	struct dpu_hw_ctl *ctl;
>  	struct dpu_hw_mixer *lm;
> @@ -281,17 +281,17 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
>  		return;
>  
>  	dpu_crtc = to_dpu_crtc(crtc);
> -	dpu_crtc_state = to_dpu_crtc_state(crtc->state);
> -	mixer = dpu_crtc->mixers;
> +	cstate = to_dpu_crtc_state(crtc->state);
> +	mixer = cstate->mixers;
>  
>  	DPU_DEBUG("%s\n", dpu_crtc->name);
>  
> -	if (dpu_crtc->num_mixers > CRTC_DUAL_MIXERS) {
> -		DPU_ERROR("invalid number mixers: %d\n", dpu_crtc->num_mixers);
> +	if (cstate->num_mixers > CRTC_DUAL_MIXERS) {

This is not possible.

> +		DPU_ERROR("invalid number mixers: %d\n", cstate->num_mixers);
>  		return;
>  	}
>  
> -	for (i = 0; i < dpu_crtc->num_mixers; i++) {
> +	for (i = 0; i < cstate->num_mixers; i++) {
>  		if (!mixer[i].hw_lm || !mixer[i].hw_ctl) {
>  			DPU_ERROR("invalid lm or ctl assigned to mixer\n");
>  			return;
> @@ -308,7 +308,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
>  
>  	_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer);
>  
> -	for (i = 0; i < dpu_crtc->num_mixers; i++) {
> +	for (i = 0; i < cstate->num_mixers; i++) {
>  		ctl = mixer[i].hw_ctl;
>  		lm = mixer[i].hw_lm;
>  
> @@ -530,7 +530,7 @@ static void _dpu_crtc_setup_mixer_for_encoder(
>  		struct drm_crtc *crtc,
>  		struct drm_encoder *enc)
>  {
> -	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
> +	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
>  	struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
>  	struct dpu_rm *rm = &dpu_kms->rm;
>  	struct dpu_crtc_mixer *mixer;
> @@ -542,8 +542,8 @@ static void _dpu_crtc_setup_mixer_for_encoder(
>  	dpu_rm_init_hw_iter(&ctl_iter, enc->base.id, DPU_HW_BLK_CTL);
>  
>  	/* Set up all the mixers and ctls reserved by this encoder */
> -	for (i = dpu_crtc->num_mixers; i < ARRAY_SIZE(dpu_crtc->mixers); i++) {
> -		mixer = &dpu_crtc->mixers[i];
> +	for (i = cstate->num_mixers; i < ARRAY_SIZE(cstate->mixers); i++) {
> +		mixer = &cstate->mixers[i];
>  
>  		if (!dpu_rm_get_hw(rm, &lm_iter))
>  			break;
> @@ -568,7 +568,7 @@ static void _dpu_crtc_setup_mixer_for_encoder(
>  
>  		mixer->encoder = enc;
>  
> -		dpu_crtc->num_mixers++;
> +		cstate->num_mixers++;
>  		DPU_DEBUG("setup mixer %d: lm %d\n",
>  				i, mixer->hw_lm->idx - LM_0);
>  		DPU_DEBUG("setup mixer %d: ctl %d\n",
> @@ -579,11 +579,11 @@ static void _dpu_crtc_setup_mixer_for_encoder(
>  static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
>  {
>  	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
> +	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
>  	struct drm_encoder *enc;
>  
> -	dpu_crtc->num_mixers = 0;
> -	dpu_crtc->mixers_swapped = false;
> -	memset(dpu_crtc->mixers, 0, sizeof(dpu_crtc->mixers));
> +	cstate->num_mixers = 0;
> +	memset(cstate->mixers, 0, sizeof(cstate->mixers));

Why is this necessary?

>  
>  	mutex_lock(&dpu_crtc->crtc_lock);
>  	/* Check for mixers on all encoders attached to this crtc */
> @@ -618,7 +618,7 @@ static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
>  	crtc_split_width = _dpu_crtc_get_mixer_width(dpu_crtc, cstate,
>  						    adj_mode);
>  
> -	for (i = 0; i < dpu_crtc->num_mixers; i++) {
> +	for (i = 0; i < cstate->num_mixers; i++) {
>  		struct drm_rect *r = &cstate->lm_bounds[i];
>  		r->x1 = crtc_split_width * i;
>  		r->y1 = 0;
> @@ -635,6 +635,7 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
>  		struct drm_crtc_state *old_state)
>  {
>  	struct dpu_crtc *dpu_crtc;
> +	struct dpu_crtc_state *cstate;
>  	struct drm_encoder *encoder;
>  	struct drm_device *dev;
>  	unsigned long flags;
> @@ -654,10 +655,11 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
>  	DPU_DEBUG("crtc%d\n", crtc->base.id);
>  
>  	dpu_crtc = to_dpu_crtc(crtc);
> +	cstate = to_dpu_crtc_state(crtc->state);
>  	dev = crtc->dev;
>  	smmu_state = &dpu_crtc->smmu_state;
>  
> -	if (!dpu_crtc->num_mixers) {
> +	if (!cstate->num_mixers) {
>  		_dpu_crtc_setup_mixers(crtc);
>  		_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
>  	}
> @@ -684,7 +686,7 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
>  	 * it means we are trying to flush a CRTC whose state is disabled:
>  	 * nothing else needs to be done.
>  	 */
> -	if (unlikely(!dpu_crtc->num_mixers))
> +	if (unlikely(!cstate->num_mixers))
>  		return;
>  
>  	_dpu_crtc_blend_setup(crtc);
> @@ -748,7 +750,7 @@ static void dpu_crtc_atomic_flush(struct drm_crtc *crtc,
>  	 * it means we are trying to flush a CRTC whose state is disabled:
>  	 * nothing else needs to be done.
>  	 */
> -	if (unlikely(!dpu_crtc->num_mixers))
> +	if (unlikely(!cstate->num_mixers))
>  		return;
>  
>  	/*
> @@ -863,7 +865,7 @@ void dpu_crtc_commit_kickoff(struct drm_crtc *crtc)
>  	 * it means we are trying to start a CRTC whose state is disabled:
>  	 * nothing else needs to be done.
>  	 */
> -	if (unlikely(!dpu_crtc->num_mixers))
> +	if (unlikely(!cstate->num_mixers))
>  		return;
>  
>  	DPU_ATRACE_BEGIN("crtc_commit");
> @@ -1097,12 +1099,14 @@ static void dpu_crtc_handle_power_event(u32 event_type, void *arg)
>  	struct drm_crtc *crtc = arg;
>  	struct dpu_crtc *dpu_crtc;
>  	struct drm_encoder *encoder;
> +	struct dpu_crtc_state *cstate;
>  
>  	if (!crtc) {
>  		DPU_ERROR("invalid crtc\n");
>  		return;
>  	}
>  	dpu_crtc = to_dpu_crtc(crtc);
> +	cstate = to_dpu_crtc_state(dpu_crtc->base.state);
>  
>  	mutex_lock(&dpu_crtc->crtc_lock);
>  
> @@ -1197,9 +1201,8 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
>  		dpu_power_handle_unregister_event(dpu_crtc->phandle,
>  				dpu_crtc->power_event);
>  
> -	memset(dpu_crtc->mixers, 0, sizeof(dpu_crtc->mixers));
> -	dpu_crtc->num_mixers = 0;
> -	dpu_crtc->mixers_swapped = false;
> +	memset(cstate->mixers, 0, sizeof(cstate->mixers));

Same question here, why is this necessary?

> +	cstate->num_mixers = 0;
>  
>  	/* disable clk & bw control until clk & bw properties are set */
>  	cstate->bw_control = false;
> @@ -1547,6 +1550,8 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
>  
>  	dpu_crtc = s->private;
>  	crtc = &dpu_crtc->base;
> +
> +	drm_modeset_lock(&crtc->mutex, NULL);

When I suggested this, I was hoping you'd put it in a separate patch.
Additionally, you'll probably want modeset_lock_all instead.

>  	cstate = to_dpu_crtc_state(crtc->state);
>  
>  	mutex_lock(&dpu_crtc->crtc_lock);
> @@ -1558,8 +1563,8 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
>  
>  	seq_puts(s, "\n");
>  
> -	for (i = 0; i < dpu_crtc->num_mixers; ++i) {
> -		m = &dpu_crtc->mixers[i];
> +	for (i = 0; i < cstate->num_mixers; ++i) {
> +		m = &cstate->mixers[i];
>  		if (!m->hw_lm)
>  			seq_printf(s, "\tmixer[%d] has no lm\n", i);
>  		else if (!m->hw_ctl)
> @@ -1639,6 +1644,7 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
>  	seq_printf(s, "vblank_enable:%d\n", dpu_crtc->vblank_requested);
>  
>  	mutex_unlock(&dpu_crtc->crtc_lock);
> +	drm_modeset_unlock(&crtc->mutex);
>  
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> index 5e4dc5c..7aa772f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> @@ -121,11 +121,6 @@ struct dpu_crtc_frame_event {
>   * struct dpu_crtc - virtualized CRTC data structure
>   * @base          : Base drm crtc structure
>   * @name          : ASCII description of this crtc
> - * @num_ctls      : Number of ctl paths in use
> - * @num_mixers    : Number of mixers in use
> - * @mixers_swapped: Whether the mixers have been swapped for left/right update
> - *                  especially in the case of DSC Merge.
> - * @mixers        : List of active mixers
>   * @event         : Pointer to last received drm vblank event. If there is a
>   *                  pending vblank event, this will be non-null.
>   * @vsync_count   : Running count of received vsync events
> @@ -164,12 +159,6 @@ struct dpu_crtc {
>  	struct drm_crtc base;
>  	char name[DPU_CRTC_NAME_SIZE];
>  
> -	/* HW Resources reserved for the crtc */
> -	u32 num_ctls;
> -	u32 num_mixers;
> -	bool mixers_swapped;
> -	struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
> -
>  	struct drm_pending_vblank_event *event;
>  	u32 vsync_count;
>  
> @@ -221,6 +210,10 @@ struct dpu_crtc {
>   * @property_values: Current crtc property values
>   * @input_fence_timeout_ns : Cached input fence timeout, in ns
>   * @new_perf: new performance state being requested
> + * @num_mixers    : Number of mixers in use
> + * @mixers        : List of active mixers
> + * @num_ctls      : Number of ctl paths in use
> + * @hw_ctls       : List of active ctl paths
>   */
>  struct dpu_crtc_state {
>  	struct drm_crtc_state base;
> @@ -232,6 +225,13 @@ struct dpu_crtc_state {
>  	uint64_t input_fence_timeout_ns;
>  
>  	struct dpu_core_perf_params new_perf;
> +
> +	/* HW Resources reserved for the crtc */
> +	u32 num_mixers;
> +	struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
> +
> +	u32 num_ctls;
> +	struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS];
>  };
>  
>  #define to_dpu_crtc_state(x) \
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH 11/14] drm/msm/dpu: rename hw_ctl to lm_ctl

[Sean Paul]

On Tue, Aug 28, 2018 at 05:40:00PM -0700, Jeykumar Sankaran wrote:
> Rename hw_ctl to lm_ctl to mean the ctl associated
> with the hw layer mixer block.
> 
> sed -i 's/\([*@.>]\)hw_ctl\([^s]\)/\1lm_ctl\2/g' dpu_crtc.c dpu_crtc.h
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 26 +++++++++++++-------------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |  4 ++--
>  2 files changed, 15 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index 7ab320d..aeb0f1a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -202,7 +202,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
>  		return;
>  	}
>  
> -	ctl = mixer->hw_ctl;
> +	ctl = mixer->lm_ctl;
>  	lm = mixer->hw_lm;
>  	stage_cfg = &dpu_crtc->stage_cfg;
>  	cstate = to_dpu_crtc_state(crtc->state);
> @@ -292,15 +292,15 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
>  	}
>  
>  	for (i = 0; i < cstate->num_mixers; i++) {
> -		if (!mixer[i].hw_lm || !mixer[i].hw_ctl) {
> +		if (!mixer[i].hw_lm || !mixer[i].lm_ctl) {
>  			DPU_ERROR("invalid lm or ctl assigned to mixer\n");
>  			return;
>  		}
>  		mixer[i].mixer_op_mode = 0;
>  		mixer[i].flush_mask = 0;
> -		if (mixer[i].hw_ctl->ops.clear_all_blendstages)
> -			mixer[i].hw_ctl->ops.clear_all_blendstages(
> -					mixer[i].hw_ctl);
> +		if (mixer[i].lm_ctl->ops.clear_all_blendstages)
> +			mixer[i].lm_ctl->ops.clear_all_blendstages(
> +					mixer[i].lm_ctl);
>  	}
>  
>  	/* initialize stage cfg */
> @@ -309,7 +309,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
>  	_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer);
>  
>  	for (i = 0; i < cstate->num_mixers; i++) {
> -		ctl = mixer[i].hw_ctl;
> +		ctl = mixer[i].lm_ctl;
>  		lm = mixer[i].hw_lm;
>  
>  		lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
> @@ -553,14 +553,14 @@ static void _dpu_crtc_setup_mixer_for_encoder(
>  		if (!dpu_rm_get_hw(rm, &ctl_iter)) {
>  			DPU_DEBUG("no ctl assigned to lm %d, using previous\n",
>  					mixer->hw_lm->idx - LM_0);
> -			mixer->hw_ctl = last_valid_ctl;
> +			mixer->lm_ctl = last_valid_ctl;
>  		} else {
> -			mixer->hw_ctl = (struct dpu_hw_ctl *)ctl_iter.hw;
> -			last_valid_ctl = mixer->hw_ctl;
> +			mixer->lm_ctl = (struct dpu_hw_ctl *)ctl_iter.hw;
> +			last_valid_ctl = mixer->lm_ctl;
>  		}
>  
>  		/* Shouldn't happen, mixers are always >= ctls */
> -		if (!mixer->hw_ctl) {
> +		if (!mixer->lm_ctl) {
>  			DPU_ERROR("no valid ctls found for lm %d\n",
>  					mixer->hw_lm->idx - LM_0);
>  			return;
> @@ -572,7 +572,7 @@ static void _dpu_crtc_setup_mixer_for_encoder(
>  		DPU_DEBUG("setup mixer %d: lm %d\n",
>  				i, mixer->hw_lm->idx - LM_0);
>  		DPU_DEBUG("setup mixer %d: ctl %d\n",
> -				i, mixer->hw_ctl->idx - CTL_0);
> +				i, mixer->lm_ctl->idx - CTL_0);
>  	}
>  }
>  
> @@ -1567,11 +1567,11 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
>  		m = &cstate->mixers[i];
>  		if (!m->hw_lm)
>  			seq_printf(s, "\tmixer[%d] has no lm\n", i);
> -		else if (!m->hw_ctl)
> +		else if (!m->lm_ctl)
>  			seq_printf(s, "\tmixer[%d] has no ctl\n", i);
>  		else
>  			seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n",
> -				m->hw_lm->idx - LM_0, m->hw_ctl->idx - CTL_0,
> +				m->hw_lm->idx - LM_0, m->lm_ctl->idx - CTL_0,
>  				out_width, mode->vdisplay);
>  	}
>  
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> index 7aa772f..9b1056c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> @@ -83,14 +83,14 @@ struct dpu_crtc_smmu_state_data {
>  /**
>   * struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC
>   * @hw_lm:	LM HW Driver context
> - * @hw_ctl:	CTL Path HW driver context
> + * @lm_ctl:	CTL Path HW driver context
>   * @encoder:	Encoder attached to this lm & ctl
>   * @mixer_op_mode:	mixer blending operation mode
>   * @flush_mask:	mixer flush mask for ctl, mixer and pipe
>   */
>  struct dpu_crtc_mixer {
>  	struct dpu_hw_mixer *hw_lm;
> -	struct dpu_hw_ctl *hw_ctl;
> +	struct dpu_hw_ctl *lm_ctl;
>  	struct drm_encoder *encoder;
>  	u32 mixer_op_mode;
>  	u32 flush_mask;
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH 12/14] drm/msm/dpu: remove topology name

[Sean Paul]

On Tue, Aug 28, 2018 at 05:40:01PM -0700, Jeykumar Sankaran wrote:
> Strip down the support for topology enums. It
> can be replaced with simple hw count checks.
> 

Changes in v4:
...

> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        |  3 --
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h        |  1 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |  9 ++++--
>  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  7 +++--
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c             | 36 ++++++----------------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h             | 24 ---------------
>  6 files changed, 19 insertions(+), 61 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index dbf669e..56ef349 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -1013,7 +1013,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
>  	struct drm_connector *conn = NULL, *conn_iter;
>  	struct dpu_rm_hw_iter pp_iter, ctl_iter;
>  	struct msm_display_topology topology;
> -	enum dpu_rm_topology_name topology_name;
>  	struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL };
>  	int i = 0, ret;
>  
> @@ -1069,7 +1068,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
>  		hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw;
>  	}
>  
> -	topology_name = dpu_rm_get_topology_name(topology);
>  	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
>  		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
>  
> @@ -1089,7 +1087,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
>  			phys->hw_ctl = hw_ctl[i];
>  
>  			phys->connector = conn->state->connector;
> -			phys->topology_name = topology_name;
>  			if (phys->ops.mode_set)
>  				phys->ops.mode_set(phys, mode, adj_mode);
>  		}
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> index 60f809f..c5600e6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> @@ -35,7 +35,6 @@
>   * @needs_cdm:	Encoder requests a CDM based on pixel format conversion needs
>   * @display_num_of_h_tiles: Number of horizontal tiles in case of split
>   *                          interface
> - * @topology:   Topology of the display
>   */
>  struct dpu_encoder_hw_resources {
>  	enum dpu_intf_mode intfs[INTF_MAX];
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> index b3917e0..b5fc65c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> @@ -24,6 +24,7 @@
>  #include "dpu_hw_top.h"
>  #include "dpu_hw_cdm.h"
>  #include "dpu_encoder.h"
> +#include "dpu_crtc.h"
>  
>  #define DPU_ENCODER_NAME_MAX	16
>  
> @@ -213,7 +214,6 @@ struct dpu_encoder_irq {
>   * @split_role:		Role to play in a split-panel configuration
>   * @intf_mode:		Interface mode
>   * @intf_idx:		Interface index on dpu hardware
> - * @topology_name:	topology selected for the display
>   * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
>   * @enable_state:	Enable state tracking
>   * @vblank_refcount:	Reference count of vblank request
> @@ -243,7 +243,6 @@ struct dpu_encoder_phys {
>  	enum dpu_enc_split_role split_role;
>  	enum dpu_intf_mode intf_mode;
>  	enum dpu_intf intf_idx;
> -	enum dpu_rm_topology_name topology_name;
>  	spinlock_t *enc_spinlock;
>  	enum dpu_enc_enable_state enable_state;
>  	atomic_t vblank_refcount;
> @@ -361,11 +360,15 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
>  static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
>  		struct dpu_encoder_phys *phys_enc)
>  {
> +	struct dpu_crtc_state *dpu_cstate;
> +
>  	if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
>  		return BLEND_3D_NONE;
>  
> +	dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
> +
>  	if (phys_enc->split_role == ENC_ROLE_SOLO &&
> -	    phys_enc->topology_name == DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE)
> +	    (dpu_cstate->num_mixers == 2))

I guess this should be CRTC_DUAL_MIXERS? Perhaps you should add a helper called
dpu_crtc_state_is_stereo() instead of littering these checks everywhere.

>  		return BLEND_3D_H_ROW_INT;
>  
>  	return BLEND_3D_NONE;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index 6de13f4..1643e2f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -355,13 +355,14 @@ static void dpu_encoder_phys_vid_underrun_irq(void *arg, int irq_idx)
>  
>  static bool _dpu_encoder_phys_is_dual_ctl(struct dpu_encoder_phys *phys_enc)
>  {
> +	struct dpu_crtc_state *dpu_cstate;
> +
>  	if (!phys_enc)
>  		return false;
>  
> -	if (phys_enc->topology_name == DPU_RM_TOPOLOGY_DUALPIPE)
> -		return true;
> +	dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
>  
> -	return false;
> +	return (dpu_cstate->num_ctls > 1);

Unnecessary parens

>  }
>  
>  static bool dpu_encoder_phys_vid_needs_single_flush(
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 13c0a36..fbd489f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -33,7 +33,6 @@
>  				(t).num_intf == (r).num_intf)
>  
>  struct dpu_rm_topology_def {
> -	enum dpu_rm_topology_name top_name;
>  	int num_lm;
>  	int num_comp_enc;
>  	int num_intf;
> @@ -42,10 +41,10 @@ struct dpu_rm_topology_def {
>  };
>  
>  static const struct dpu_rm_topology_def g_top_table[] = {
> -	{   DPU_RM_TOPOLOGY_NONE,                 0, 0, 0, 0, false },
> -	{   DPU_RM_TOPOLOGY_SINGLEPIPE,           1, 0, 1, 1, false },
> -	{   DPU_RM_TOPOLOGY_DUALPIPE,             2, 0, 2, 2, true  },
> -	{   DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,     2, 0, 1, 1, false },
> +	{   0, 0, 0, 0, false },
> +	{   1, 0, 1, 1, false },
> +	{   2, 0, 2, 2, true  },
> +	{   2, 0, 1, 1, false },

You don't need this. The data it provides can be deduced already:
num_ctl == num_intf
needs_split_display == (num_intf > 1)

>  };
>  
>  /**
> @@ -72,13 +71,11 @@ struct dpu_rm_requirements {
>   * @enc_id:	Reservations are tracked by Encoder DRM object ID.
>   *		CRTCs may be connected to multiple Encoders.
>   *		An encoder or connector id identifies the display path.
> - * @topology	DRM<->HW topology use case
>   */
>  struct dpu_rm_rsvp {
>  	struct list_head list;
>  	uint32_t seq;
>  	uint32_t enc_id;
> -	enum dpu_rm_topology_name topology;
>  };
>  
>  /**
> @@ -122,8 +119,8 @@ static void _dpu_rm_print_rsvps(
>  	DPU_DEBUG("%d\n", stage);
>  
>  	list_for_each_entry(rsvp, &rm->rsvps, list) {
> -		DRM_DEBUG_KMS("%d rsvp[s%ue%u] topology %d\n", stage, rsvp->seq,
> -			      rsvp->enc_id, rsvp->topology);
> +		DRM_DEBUG_KMS("%d rsvp[s%ue%u]\n", stage, rsvp->seq,
> +			      rsvp->enc_id);
>  	}
>  
>  	for (type = 0; type < DPU_HW_BLK_MAX; type++) {
> @@ -146,18 +143,6 @@ struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm *rm)
>  	return rm->hw_mdp;
>  }
>  
> -enum dpu_rm_topology_name
> -dpu_rm_get_topology_name(struct msm_display_topology topology)
> -{
> -	int i;
> -
> -	for (i = 0; i < DPU_RM_TOPOLOGY_MAX; i++)
> -		if (RM_IS_TOPOLOGY_MATCH(g_top_table[i], topology))
> -			return g_top_table[i].top_name;
> -
> -	return DPU_RM_TOPOLOGY_NONE;
> -}
> -
>  void dpu_rm_init_hw_iter(
>  		struct dpu_rm_hw_iter *iter,
>  		uint32_t enc_id,
> @@ -760,7 +745,6 @@ static int _dpu_rm_make_next_rsvp(
>  	/* Create reservation info, tag reserved blocks with it as we go */
>  	rsvp->seq = ++rm->rsvp_next_seq;
>  	rsvp->enc_id = enc->base.id;
> -	rsvp->topology = reqs->topology->top_name;
>  	list_add_tail(&rsvp->list, &rm->rsvps);
>  
>  	ret = _dpu_rm_reserve_lms(rm, rsvp, reqs);
> @@ -807,7 +791,7 @@ static int _dpu_rm_populate_requirements(
>  
>  	dpu_encoder_get_hw_resources(enc, &reqs->hw_res, conn_state);
>  
> -	for (i = 0; i < DPU_RM_TOPOLOGY_MAX; i++) {
> +	for (i = 0; i < ARRAY_SIZE(g_top_table); i++) {
>  		if (RM_IS_TOPOLOGY_MATCH(g_top_table[i],
>  					req_topology)) {
>  			reqs->topology = &g_top_table[i];

Since you can get rid of g_top_table, you can get rid of reqs->topology too.

> @@ -831,9 +815,8 @@ static int _dpu_rm_populate_requirements(
>  
>  	DRM_DEBUG_KMS("top_ctrl: 0x%llX num_h_tiles: %d\n", reqs->top_ctrl,
>  		      reqs->hw_res.display_num_of_h_tiles);
> -	DRM_DEBUG_KMS("num_lm: %d num_ctl: %d topology: %d split_display: %d\n",
> +	DRM_DEBUG_KMS("num_lm: %d num_ctl: %d split_display: %d\n",
>  		      reqs->topology->num_lm, reqs->topology->num_ctl,
> -		      reqs->topology->top_name,
>  		      reqs->topology->needs_split_display);
>  
>  	return 0;
> @@ -969,8 +952,7 @@ static int _dpu_rm_commit_rsvp(
>  	}
>  
>  	if (!ret)
> -		DRM_DEBUG_KMS("rsrv enc %d topology %d\n", rsvp->enc_id,
> -			      rsvp->topology);
> +		DRM_DEBUG_KMS("rsrv enc %d\n", rsvp->enc_id);

This debug message doesn't provide any value any longer.

>  
>  	return ret;
>  }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> index ffd1841..6fd9e7b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> @@ -21,21 +21,6 @@
>  #include "dpu_hw_top.h"
>  
>  /**
> - * enum dpu_rm_topology_name - HW resource use case in use by connector
> - * @DPU_RM_TOPOLOGY_NONE:                 No topology in use currently
> - * @DPU_RM_TOPOLOGY_SINGLEPIPE:           1 LM, 1 PP, 1 INTF/WB
> - * @DPU_RM_TOPOLOGY_DUALPIPE:             2 LM, 2 PP, 2 INTF/WB
> - * @DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE:     2 LM, 2 PP, 3DMux, 1 INTF/WB
> - */
> -enum dpu_rm_topology_name {
> -	DPU_RM_TOPOLOGY_NONE = 0,
> -	DPU_RM_TOPOLOGY_SINGLEPIPE,
> -	DPU_RM_TOPOLOGY_DUALPIPE,
> -	DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,
> -	DPU_RM_TOPOLOGY_MAX,
> -};
> -
> -/**
>   * enum dpu_rm_topology_control - HW resource use case in use by connector
>   * @DPU_RM_TOPCTL_RESERVE_LOCK: If set, in AtomicTest phase, after a successful
>   *                              test, reserve the resources for this display.
> @@ -187,13 +172,4 @@ void dpu_rm_init_hw_iter(
>   */
>  int dpu_rm_check_property_topctl(uint64_t val);
>  
> -/**
> - * dpu_rm_get_topology_name - returns the name of the the given topology
> - *                            definition
> - * @topology: topology definition
> - * @Return: name of the topology
> - */
> -enum dpu_rm_topology_name
> -dpu_rm_get_topology_name(struct msm_display_topology topology);
> -
>  #endif /* __DPU_RM_H__ */
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno

Re: [PATCH 13/14] drm/msm/dpu: remove display H_TILE from encoder

[Sean Paul]

On Tue, Aug 28, 2018 at 05:40:02PM -0700, Jeykumar Sankaran wrote:
> Encoder H_TILE values are not used for allocating the hw blocks.
> no. of hw_intf blocks provides the info.
> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 5 -----
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 3 ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c      | 3 +--
>  3 files changed, 1 insertion(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 56ef349..bfc082d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -175,8 +175,6 @@ struct dpu_encoder_virt {
>  	spinlock_t enc_spinlock;
>  	uint32_t bus_scaling_client;
>  
> -	uint32_t display_num_of_h_tiles;
> -
>  	unsigned int num_phys_encs;
>  	struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
>  	struct dpu_encoder_phys *cur_master;
> @@ -455,7 +453,6 @@ void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc,
>  
>  	/* Query resources used by phys encs, expected to be without overlap */
>  	memset(hw_res, 0, sizeof(*hw_res));
> -	hw_res->display_num_of_h_tiles = dpu_enc->display_num_of_h_tiles;
>  
>  	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
>  		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
> @@ -2103,8 +2100,6 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
>  
>  	WARN_ON(disp_info->num_of_h_tiles < 1);
>  
> -	dpu_enc->display_num_of_h_tiles = disp_info->num_of_h_tiles;
> -
>  	DPU_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
>  
>  	if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> index c5600e6..e453271 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> @@ -33,13 +33,10 @@
>   * Encoder functions and data types
>   * @intfs:	Interfaces this encoder is using, INTF_MODE_NONE if unused
>   * @needs_cdm:	Encoder requests a CDM based on pixel format conversion needs
> - * @display_num_of_h_tiles: Number of horizontal tiles in case of split
> - *                          interface
>   */
>  struct dpu_encoder_hw_resources {
>  	enum dpu_intf_mode intfs[INTF_MAX];
>  	bool needs_cdm;
> -	u32 display_num_of_h_tiles;
>  };
>  
>  /**
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index fbd489f..388ae65 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -813,8 +813,7 @@ static int _dpu_rm_populate_requirements(
>  		conn_state->connector->connector_type == DRM_MODE_CONNECTOR_DSI)
>  		reqs->top_ctrl |= BIT(DPU_RM_TOPCTL_DS);
>  
> -	DRM_DEBUG_KMS("top_ctrl: 0x%llX num_h_tiles: %d\n", reqs->top_ctrl,
> -		      reqs->hw_res.display_num_of_h_tiles);
> +	DRM_DEBUG_KMS("top_ctrl: 0x%llX\n", reqs->top_ctrl);
>  	DRM_DEBUG_KMS("num_lm: %d num_ctl: %d split_display: %d\n",
>  		      reqs->topology->num_lm, reqs->topology->num_ctl,
>  		      reqs->topology->needs_split_display);
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH 14/14] drm/msm/dpu: remove cdm block support from resource manager

[Sean Paul]

On Tue, Aug 28, 2018 at 05:40:03PM -0700, Jeykumar Sankaran wrote:
> Support for CDM block is not present in DPU. Remove CDM
> handlers from resource manager.

I think there's some leftovers that can be cleaned up...

$ ack -i cdm
disp/dpu1/dpu_hw_mdss.h
103:    DPU_HW_BLK_CDM,
192:enum dpu_cdm {
193:    CDM_0 = 1,
194:    CDM_1,
195:    CDM_MAX
454:#define DPU_DBG_MASK_CDM      (1 << 1)

disp/dpu1/dpu_hw_catalog.h
533: * struct dpu_cdm_cfg - information of chroma down blocks
537: * @intf_connect       Bitmask of INTF IDs this CDM can connect to
539:struct dpu_cdm_cfg   {
737:    u32 cdm_count;
738:    struct dpu_cdm_cfg *cdm;
776:#define BLK_CDM(s) ((s)->cdm)

disp/dpu1/dpu_hw_catalog.c
324: * CDM sub blocks config
326:static struct dpu_cdm_cfg sdm845_cdm[] = {
328:    .name = "cdm_0", .id = CDM_0,
461:            .cdm_count = ARRAY_SIZE(sdm845_cdm),
462:            .cdm = sdm845_cdm,



> 
> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/Makefile                     |   1 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h      |   2 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h |   5 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c       | 323 -----------------------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h       | 139 ----------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c       |  14 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h       |   4 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c       |  18 --
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h       |  17 --
>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c           |  68 +----
>  drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h        |   4 -
>  11 files changed, 2 insertions(+), 593 deletions(-)
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
>  delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h
> 
> diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
> index 261fa79..19ab521 100644
> --- a/drivers/gpu/drm/msm/Makefile
> +++ b/drivers/gpu/drm/msm/Makefile
> @@ -58,7 +58,6 @@ msm-y := \
>  	disp/dpu1/dpu_formats.o \
>  	disp/dpu1/dpu_hw_blk.o \
>  	disp/dpu1/dpu_hw_catalog.o \
> -	disp/dpu1/dpu_hw_cdm.o \
>  	disp/dpu1/dpu_hw_ctl.o \
>  	disp/dpu1/dpu_hw_interrupts.o \
>  	disp/dpu1/dpu_hw_intf.o \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> index e453271..e844afa 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> @@ -32,11 +32,9 @@
>  /**
>   * Encoder functions and data types
>   * @intfs:	Interfaces this encoder is using, INTF_MODE_NONE if unused
> - * @needs_cdm:	Encoder requests a CDM based on pixel format conversion needs
>   */
>  struct dpu_encoder_hw_resources {
>  	enum dpu_intf_mode intfs[INTF_MAX];
> -	bool needs_cdm;
>  };
>  
>  /**
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> index b5fc65c..f796683 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> @@ -22,7 +22,6 @@
>  #include "dpu_hw_pingpong.h"
>  #include "dpu_hw_ctl.h"
>  #include "dpu_hw_top.h"
> -#include "dpu_hw_cdm.h"
>  #include "dpu_encoder.h"
>  #include "dpu_crtc.h"
>  
> @@ -205,8 +204,6 @@ struct dpu_encoder_irq {
>   * @parent_ops:		Callbacks exposed by the parent to the phys_enc
>   * @hw_mdptop:		Hardware interface to the top registers
>   * @hw_ctl:		Hardware interface to the ctl registers
> - * @hw_cdm:		Hardware interface to the cdm registers
> - * @cdm_cfg:		Chroma-down hardware configuration
>   * @hw_pp:		Hardware interface to the ping pong registers
>   * @dpu_kms:		Pointer to the dpu_kms top level
>   * @cached_mode:	DRM mode cached at mode_set time, acted on in enable
> @@ -235,8 +232,6 @@ struct dpu_encoder_phys {
>  	const struct dpu_encoder_virt_ops *parent_ops;
>  	struct dpu_hw_mdp *hw_mdptop;
>  	struct dpu_hw_ctl *hw_ctl;
> -	struct dpu_hw_cdm *hw_cdm;
> -	struct dpu_hw_cdm_cfg cdm_cfg;
>  	struct dpu_hw_pingpong *hw_pp;
>  	struct dpu_kms *dpu_kms;
>  	struct drm_display_mode cached_mode;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
> deleted file mode 100644
> index 554874b..0000000
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
> +++ /dev/null
> @@ -1,323 +0,0 @@
> -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 and
> - * only version 2 as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> - * GNU General Public License for more details.
> - */
> -
> -#include "dpu_hw_mdss.h"
> -#include "dpu_hwio.h"
> -#include "dpu_hw_catalog.h"
> -#include "dpu_hw_cdm.h"
> -#include "dpu_dbg.h"
> -#include "dpu_kms.h"
> -
> -#define CDM_CSC_10_OPMODE                  0x000
> -#define CDM_CSC_10_BASE                    0x004
> -
> -#define CDM_CDWN2_OP_MODE                  0x100
> -#define CDM_CDWN2_CLAMP_OUT                0x104
> -#define CDM_CDWN2_PARAMS_3D_0              0x108
> -#define CDM_CDWN2_PARAMS_3D_1              0x10C
> -#define CDM_CDWN2_COEFF_COSITE_H_0         0x110
> -#define CDM_CDWN2_COEFF_COSITE_H_1         0x114
> -#define CDM_CDWN2_COEFF_COSITE_H_2         0x118
> -#define CDM_CDWN2_COEFF_OFFSITE_H_0        0x11C
> -#define CDM_CDWN2_COEFF_OFFSITE_H_1        0x120
> -#define CDM_CDWN2_COEFF_OFFSITE_H_2        0x124
> -#define CDM_CDWN2_COEFF_COSITE_V           0x128
> -#define CDM_CDWN2_COEFF_OFFSITE_V          0x12C
> -#define CDM_CDWN2_OUT_SIZE                 0x130
> -
> -#define CDM_HDMI_PACK_OP_MODE              0x200
> -#define CDM_CSC_10_MATRIX_COEFF_0          0x004
> -
> -/**
> - * Horizontal coefficients for cosite chroma downscale
> - * s13 representation of coefficients
> - */
> -static u32 cosite_h_coeff[] = {0x00000016, 0x000001cc, 0x0100009e};
> -
> -/**
> - * Horizontal coefficients for offsite chroma downscale
> - */
> -static u32 offsite_h_coeff[] = {0x000b0005, 0x01db01eb, 0x00e40046};
> -
> -/**
> - * Vertical coefficients for cosite chroma downscale
> - */
> -static u32 cosite_v_coeff[] = {0x00080004};
> -/**
> - * Vertical coefficients for offsite chroma downscale
> - */
> -static u32 offsite_v_coeff[] = {0x00060002};
> -
> -/* Limited Range rgb2yuv coeff with clamp and bias values for CSC 10 module */
> -static struct dpu_csc_cfg rgb2yuv_cfg = {
> -	{
> -		0x0083, 0x0102, 0x0032,
> -		0x1fb5, 0x1f6c, 0x00e1,
> -		0x00e1, 0x1f45, 0x1fdc
> -	},
> -	{ 0x00, 0x00, 0x00 },
> -	{ 0x0040, 0x0200, 0x0200 },
> -	{ 0x000, 0x3ff, 0x000, 0x3ff, 0x000, 0x3ff },
> -	{ 0x040, 0x3ac, 0x040, 0x3c0, 0x040, 0x3c0 },
> -};
> -
> -static struct dpu_cdm_cfg *_cdm_offset(enum dpu_cdm cdm,
> -		struct dpu_mdss_cfg *m,
> -		void __iomem *addr,
> -		struct dpu_hw_blk_reg_map *b)
> -{
> -	int i;
> -
> -	for (i = 0; i < m->cdm_count; i++) {
> -		if (cdm == m->cdm[i].id) {
> -			b->base_off = addr;
> -			b->blk_off = m->cdm[i].base;
> -			b->length = m->cdm[i].len;
> -			b->hwversion = m->hwversion;
> -			b->log_mask = DPU_DBG_MASK_CDM;
> -			return &m->cdm[i];
> -		}
> -	}
> -
> -	return ERR_PTR(-EINVAL);
> -}
> -
> -static int dpu_hw_cdm_setup_csc_10bit(struct dpu_hw_cdm *ctx,
> -		struct dpu_csc_cfg *data)
> -{
> -	dpu_hw_csc_setup(&ctx->hw, CDM_CSC_10_MATRIX_COEFF_0, data, true);
> -
> -	return 0;
> -}
> -
> -static int dpu_hw_cdm_setup_cdwn(struct dpu_hw_cdm *ctx,
> -		struct dpu_hw_cdm_cfg *cfg)
> -{
> -	struct dpu_hw_blk_reg_map *c = &ctx->hw;
> -	u32 opmode = 0;
> -	u32 out_size = 0;
> -
> -	if (cfg->output_bit_depth == CDM_CDWN_OUTPUT_10BIT)
> -		opmode &= ~BIT(7);
> -	else
> -		opmode |= BIT(7);
> -
> -	/* ENABLE DWNS_H bit */
> -	opmode |= BIT(1);
> -
> -	switch (cfg->h_cdwn_type) {
> -	case CDM_CDWN_DISABLE:
> -		/* CLEAR METHOD_H field */
> -		opmode &= ~(0x18);
> -		/* CLEAR DWNS_H bit */
> -		opmode &= ~BIT(1);
> -		break;
> -	case CDM_CDWN_PIXEL_DROP:
> -		/* Clear METHOD_H field (pixel drop is 0) */
> -		opmode &= ~(0x18);
> -		break;
> -	case CDM_CDWN_AVG:
> -		/* Clear METHOD_H field (Average is 0x1) */
> -		opmode &= ~(0x18);
> -		opmode |= (0x1 << 0x3);
> -		break;
> -	case CDM_CDWN_COSITE:
> -		/* Clear METHOD_H field (Average is 0x2) */
> -		opmode &= ~(0x18);
> -		opmode |= (0x2 << 0x3);
> -		/* Co-site horizontal coefficients */
> -		DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_0,
> -				cosite_h_coeff[0]);
> -		DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_1,
> -				cosite_h_coeff[1]);
> -		DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_2,
> -				cosite_h_coeff[2]);
> -		break;
> -	case CDM_CDWN_OFFSITE:
> -		/* Clear METHOD_H field (Average is 0x3) */
> -		opmode &= ~(0x18);
> -		opmode |= (0x3 << 0x3);
> -
> -		/* Off-site horizontal coefficients */
> -		DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_0,
> -				offsite_h_coeff[0]);
> -		DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_1,
> -				offsite_h_coeff[1]);
> -		DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_2,
> -				offsite_h_coeff[2]);
> -		break;
> -	default:
> -		pr_err("%s invalid horz down sampling type\n", __func__);
> -		return -EINVAL;
> -	}
> -
> -	/* ENABLE DWNS_V bit */
> -	opmode |= BIT(2);
> -
> -	switch (cfg->v_cdwn_type) {
> -	case CDM_CDWN_DISABLE:
> -		/* CLEAR METHOD_V field */
> -		opmode &= ~(0x60);
> -		/* CLEAR DWNS_V bit */
> -		opmode &= ~BIT(2);
> -		break;
> -	case CDM_CDWN_PIXEL_DROP:
> -		/* Clear METHOD_V field (pixel drop is 0) */
> -		opmode &= ~(0x60);
> -		break;
> -	case CDM_CDWN_AVG:
> -		/* Clear METHOD_V field (Average is 0x1) */
> -		opmode &= ~(0x60);
> -		opmode |= (0x1 << 0x5);
> -		break;
> -	case CDM_CDWN_COSITE:
> -		/* Clear METHOD_V field (Average is 0x2) */
> -		opmode &= ~(0x60);
> -		opmode |= (0x2 << 0x5);
> -		/* Co-site vertical coefficients */
> -		DPU_REG_WRITE(c,
> -				CDM_CDWN2_COEFF_COSITE_V,
> -				cosite_v_coeff[0]);
> -		break;
> -	case CDM_CDWN_OFFSITE:
> -		/* Clear METHOD_V field (Average is 0x3) */
> -		opmode &= ~(0x60);
> -		opmode |= (0x3 << 0x5);
> -
> -		/* Off-site vertical coefficients */
> -		DPU_REG_WRITE(c,
> -				CDM_CDWN2_COEFF_OFFSITE_V,
> -				offsite_v_coeff[0]);
> -		break;
> -	default:
> -		return -EINVAL;
> -	}
> -
> -	if (cfg->v_cdwn_type || cfg->h_cdwn_type)
> -		opmode |= BIT(0); /* EN CDWN module */
> -	else
> -		opmode &= ~BIT(0);
> -
> -	out_size = (cfg->output_width & 0xFFFF) |
> -		((cfg->output_height & 0xFFFF) << 16);
> -	DPU_REG_WRITE(c, CDM_CDWN2_OUT_SIZE, out_size);
> -	DPU_REG_WRITE(c, CDM_CDWN2_OP_MODE, opmode);
> -	DPU_REG_WRITE(c, CDM_CDWN2_CLAMP_OUT,
> -			((0x3FF << 16) | 0x0));
> -
> -	return 0;
> -}
> -
> -static int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx,
> -		struct dpu_hw_cdm_cfg *cdm)
> -{
> -	struct dpu_hw_blk_reg_map *c = &ctx->hw;
> -	const struct dpu_format *fmt = cdm->output_fmt;
> -	struct cdm_output_cfg cdm_cfg = { 0 };
> -	u32 opmode = 0;
> -	u32 csc = 0;
> -
> -	if (!DPU_FORMAT_IS_YUV(fmt))
> -		return -EINVAL;
> -
> -	if (cdm->output_type == CDM_CDWN_OUTPUT_HDMI) {
> -		if (fmt->chroma_sample != DPU_CHROMA_H1V2)
> -			return -EINVAL; /*unsupported format */
> -		opmode = BIT(0);
> -		opmode |= (fmt->chroma_sample << 1);
> -		cdm_cfg.intf_en = true;
> -	}
> -
> -	csc |= BIT(2);
> -	csc &= ~BIT(1);
> -	csc |= BIT(0);
> -
> -	if (ctx->hw_mdp && ctx->hw_mdp->ops.setup_cdm_output)
> -		ctx->hw_mdp->ops.setup_cdm_output(ctx->hw_mdp, &cdm_cfg);
> -
> -	DPU_REG_WRITE(c, CDM_CSC_10_OPMODE, csc);
> -	DPU_REG_WRITE(c, CDM_HDMI_PACK_OP_MODE, opmode);
> -	return 0;
> -}
> -
> -static void dpu_hw_cdm_disable(struct dpu_hw_cdm *ctx)
> -{
> -	struct cdm_output_cfg cdm_cfg = { 0 };
> -
> -	if (ctx->hw_mdp && ctx->hw_mdp->ops.setup_cdm_output)
> -		ctx->hw_mdp->ops.setup_cdm_output(ctx->hw_mdp, &cdm_cfg);
> -}
> -
> -static void _setup_cdm_ops(struct dpu_hw_cdm_ops *ops,
> -	unsigned long features)
> -{
> -	ops->setup_csc_data = dpu_hw_cdm_setup_csc_10bit;
> -	ops->setup_cdwn = dpu_hw_cdm_setup_cdwn;
> -	ops->enable = dpu_hw_cdm_enable;
> -	ops->disable = dpu_hw_cdm_disable;
> -}
> -
> -static struct dpu_hw_blk_ops dpu_hw_ops = {
> -	.start = NULL,
> -	.stop = NULL,
> -};
> -
> -struct dpu_hw_cdm *dpu_hw_cdm_init(enum dpu_cdm idx,
> -		void __iomem *addr,
> -		struct dpu_mdss_cfg *m,
> -		struct dpu_hw_mdp *hw_mdp)
> -{
> -	struct dpu_hw_cdm *c;
> -	struct dpu_cdm_cfg *cfg;
> -	int rc;
> -
> -	c = kzalloc(sizeof(*c), GFP_KERNEL);
> -	if (!c)
> -		return ERR_PTR(-ENOMEM);
> -
> -	cfg = _cdm_offset(idx, m, addr, &c->hw);
> -	if (IS_ERR_OR_NULL(cfg)) {
> -		kfree(c);
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	c->idx = idx;
> -	c->caps = cfg;
> -	_setup_cdm_ops(&c->ops, c->caps->features);
> -	c->hw_mdp = hw_mdp;
> -
> -	rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_CDM, idx, &dpu_hw_ops);
> -	if (rc) {
> -		DPU_ERROR("failed to init hw blk %d\n", rc);
> -		goto blk_init_error;
> -	}
> -
> -	/*
> -	 * Perform any default initialization for the chroma down module
> -	 * @setup default csc coefficients
> -	 */
> -	dpu_hw_cdm_setup_csc_10bit(c, &rgb2yuv_cfg);
> -
> -	return c;
> -
> -blk_init_error:
> -	kzfree(c);
> -
> -	return ERR_PTR(rc);
> -}
> -
> -void dpu_hw_cdm_destroy(struct dpu_hw_cdm *cdm)
> -{
> -	if (cdm)
> -		dpu_hw_blk_destroy(&cdm->base);
> -	kfree(cdm);
> -}
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h
> deleted file mode 100644
> index 5cceb1e..0000000
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h
> +++ /dev/null
> @@ -1,139 +0,0 @@
> -/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 and
> - * only version 2 as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> - * GNU General Public License for more details.
> - */
> -
> -#ifndef _DPU_HW_CDM_H
> -#define _DPU_HW_CDM_H
> -
> -#include "dpu_hw_mdss.h"
> -#include "dpu_hw_top.h"
> -#include "dpu_hw_blk.h"
> -
> -struct dpu_hw_cdm;
> -
> -struct dpu_hw_cdm_cfg {
> -	u32 output_width;
> -	u32 output_height;
> -	u32 output_bit_depth;
> -	u32 h_cdwn_type;
> -	u32 v_cdwn_type;
> -	const struct dpu_format *output_fmt;
> -	u32 output_type;
> -	int flags;
> -};
> -
> -enum dpu_hw_cdwn_type {
> -	CDM_CDWN_DISABLE,
> -	CDM_CDWN_PIXEL_DROP,
> -	CDM_CDWN_AVG,
> -	CDM_CDWN_COSITE,
> -	CDM_CDWN_OFFSITE,
> -};
> -
> -enum dpu_hw_cdwn_output_type {
> -	CDM_CDWN_OUTPUT_HDMI,
> -	CDM_CDWN_OUTPUT_WB,
> -};
> -
> -enum dpu_hw_cdwn_output_bit_depth {
> -	CDM_CDWN_OUTPUT_8BIT,
> -	CDM_CDWN_OUTPUT_10BIT,
> -};
> -
> -/**
> - * struct dpu_hw_cdm_ops : Interface to the chroma down Hw driver functions
> - *                         Assumption is these functions will be called after
> - *                         clocks are enabled
> - *  @setup_csc:            Programs the csc matrix
> - *  @setup_cdwn:           Sets up the chroma down sub module
> - *  @enable:               Enables the output to interface and programs the
> - *                         output packer
> - *  @disable:              Puts the cdm in bypass mode
> - */
> -struct dpu_hw_cdm_ops {
> -	/**
> -	 * Programs the CSC matrix for conversion from RGB space to YUV space,
> -	 * it is optional to call this function as this matrix is automatically
> -	 * set during initialization, user should call this if it wants
> -	 * to program a different matrix than default matrix.
> -	 * @cdm:          Pointer to the chroma down context structure
> -	 * @data          Pointer to CSC configuration data
> -	 * return:        0 if success; error code otherwise
> -	 */
> -	int (*setup_csc_data)(struct dpu_hw_cdm *cdm,
> -			struct dpu_csc_cfg *data);
> -
> -	/**
> -	 * Programs the Chroma downsample part.
> -	 * @cdm         Pointer to chroma down context
> -	 */
> -	int (*setup_cdwn)(struct dpu_hw_cdm *cdm,
> -	struct dpu_hw_cdm_cfg *cfg);
> -
> -	/**
> -	 * Enable the CDM module
> -	 * @cdm         Pointer to chroma down context
> -	 */
> -	int (*enable)(struct dpu_hw_cdm *cdm,
> -	struct dpu_hw_cdm_cfg *cfg);
> -
> -	/**
> -	 * Disable the CDM module
> -	 * @cdm         Pointer to chroma down context
> -	 */
> -	void (*disable)(struct dpu_hw_cdm *cdm);
> -};
> -
> -struct dpu_hw_cdm {
> -	struct dpu_hw_blk base;
> -	struct dpu_hw_blk_reg_map hw;
> -
> -	/* chroma down */
> -	const struct dpu_cdm_cfg *caps;
> -	enum  dpu_cdm  idx;
> -
> -	/* mdp top hw driver */
> -	struct dpu_hw_mdp *hw_mdp;
> -
> -	/* ops */
> -	struct dpu_hw_cdm_ops ops;
> -};
> -
> -/**
> - * dpu_hw_cdm - convert base object dpu_hw_base to container
> - * @hw: Pointer to base hardware block
> - * return: Pointer to hardware block container
> - */
> -static inline struct dpu_hw_cdm *to_dpu_hw_cdm(struct dpu_hw_blk *hw)
> -{
> -	return container_of(hw, struct dpu_hw_cdm, base);
> -}
> -
> -/**
> - * dpu_hw_cdm_init - initializes the cdm hw driver object.
> - * should be called once before accessing every cdm.
> - * @idx:  cdm index for which driver object is required
> - * @addr: mapped register io address of MDP
> - * @m :   pointer to mdss catalog data
> - * @hw_mdp:  pointer to mdp top hw driver object
> - */
> -struct dpu_hw_cdm *dpu_hw_cdm_init(enum dpu_cdm idx,
> -		void __iomem *addr,
> -		struct dpu_mdss_cfg *m,
> -		struct dpu_hw_mdp *hw_mdp);
> -
> -/**
> - * dpu_hw_cdm_destroy - destroys CDM driver context
> - * @cdm:   pointer to CDM driver context
> - */
> -void dpu_hw_cdm_destroy(struct dpu_hw_cdm *cdm);
> -
> -#endif /*_DPU_HW_CDM_H */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 06be7cf..b394a18 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -224,19 +224,6 @@ static inline int dpu_hw_ctl_get_bitmask_intf(struct dpu_hw_ctl *ctx,
>  	return 0;
>  }
>  
> -static inline int dpu_hw_ctl_get_bitmask_cdm(struct dpu_hw_ctl *ctx,
> -		u32 *flushbits, enum dpu_cdm cdm)
> -{
> -	switch (cdm) {
> -	case CDM_0:
> -		*flushbits |= BIT(26);
> -		break;
> -	default:
> -		return -EINVAL;
> -	}
> -	return 0;
> -}
> -
>  static u32 dpu_hw_ctl_poll_reset_status(struct dpu_hw_ctl *ctx, u32 timeout_us)
>  {
>  	struct dpu_hw_blk_reg_map *c = &ctx->hw;
> @@ -485,7 +472,6 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
>  	ops->get_bitmask_sspp = dpu_hw_ctl_get_bitmask_sspp;
>  	ops->get_bitmask_mixer = dpu_hw_ctl_get_bitmask_mixer;
>  	ops->get_bitmask_intf = dpu_hw_ctl_get_bitmask_intf;
> -	ops->get_bitmask_cdm = dpu_hw_ctl_get_bitmask_cdm;
>  };
>  
>  static struct dpu_hw_blk_ops dpu_hw_ops = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> index c66a71f..6f313fa 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> @@ -142,10 +142,6 @@ struct dpu_hw_ctl_ops {
>  		u32 *flushbits,
>  		enum dpu_intf blk);
>  
> -	int (*get_bitmask_cdm)(struct dpu_hw_ctl *ctx,
> -		u32 *flushbits,
> -		enum dpu_cdm blk);
> -
>  	/**
>  	 * Set all blend stages to disabled
>  	 * @ctx       : ctl path ctx pointer
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> index db2798e..b878125 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> @@ -98,23 +98,6 @@ static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp,
>  	DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1);
>  }
>  
> -static void dpu_hw_setup_cdm_output(struct dpu_hw_mdp *mdp,
> -		struct cdm_output_cfg *cfg)
> -{
> -	struct dpu_hw_blk_reg_map *c;
> -	u32 out_ctl = 0;
> -
> -	if (!mdp || !cfg)
> -		return;
> -
> -	c = &mdp->hw;
> -
> -	if (cfg->intf_en)
> -		out_ctl |= BIT(19);
> -
> -	DPU_REG_WRITE(c, MDP_OUT_CTL_0, out_ctl);
> -}
> -
>  static bool dpu_hw_setup_clk_force_ctrl(struct dpu_hw_mdp *mdp,
>  		enum dpu_clk_ctrl_type clk_ctrl, bool enable)
>  {
> @@ -307,7 +290,6 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
>  		unsigned long cap)
>  {
>  	ops->setup_split_pipe = dpu_hw_setup_split_pipe;
> -	ops->setup_cdm_output = dpu_hw_setup_cdm_output;
>  	ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl;
>  	ops->get_danger_status = dpu_hw_get_danger_status;
>  	ops->setup_vsync_source = dpu_hw_setup_vsync_source;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
> index 899925a..192e338 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
> @@ -52,14 +52,6 @@ struct split_pipe_cfg {
>  };
>  
>  /**
> - * struct cdm_output_cfg: output configuration for cdm
> - * @intf_en   : enable/disable interface output
> - */
> -struct cdm_output_cfg {
> -	bool intf_en;
> -};
> -
> -/**
>   * struct dpu_danger_safe_status: danger and safe status signals
>   * @mdp: top level status
>   * @sspp: source pipe status
> @@ -89,7 +81,6 @@ struct dpu_vsync_source_cfg {
>   * Assumption is these functions will be called after clocks are enabled.
>   * @setup_split_pipe : Programs the pipe control registers
>   * @setup_pp_split : Programs the pp split control registers
> - * @setup_cdm_output : programs cdm control
>   * @setup_traffic_shaper : programs traffic shaper control
>   */
>  struct dpu_hw_mdp_ops {
> @@ -102,14 +93,6 @@ struct dpu_hw_mdp_ops {
>  			struct split_pipe_cfg *p);
>  
>  	/**
> -	 * setup_cdm_output() : Setup selection control of the cdm data path
> -	 * @mdp  : mdp top context driver
> -	 * @cfg  : cdm output configuration
> -	 */
> -	void (*setup_cdm_output)(struct dpu_hw_mdp *mdp,
> -			struct cdm_output_cfg *cfg);
> -
> -	/**
>  	 * setup_traffic_shaper() : Setup traffic shaper control
>  	 * @mdp  : mdp top context driver
>  	 * @cfg  : traffic shaper configuration
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 388ae65..e08b3bd 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -16,7 +16,6 @@
>  #include "dpu_kms.h"
>  #include "dpu_hw_lm.h"
>  #include "dpu_hw_ctl.h"
> -#include "dpu_hw_cdm.h"
>  #include "dpu_hw_pingpong.h"
>  #include "dpu_hw_intf.h"
>  #include "dpu_encoder.h"
> @@ -214,9 +213,6 @@ static void _dpu_rm_hw_destroy(enum dpu_hw_blk_type type, void *hw)
>  	case DPU_HW_BLK_CTL:
>  		dpu_hw_ctl_destroy(hw);
>  		break;
> -	case DPU_HW_BLK_CDM:
> -		dpu_hw_cdm_destroy(hw);
> -		break;
>  	case DPU_HW_BLK_PINGPONG:
>  		dpu_hw_pingpong_destroy(hw);
>  		break;
> @@ -290,9 +286,6 @@ static int _dpu_rm_hw_blk_create(
>  	case DPU_HW_BLK_CTL:
>  		hw = dpu_hw_ctl_init(id, mmio, cat);
>  		break;
> -	case DPU_HW_BLK_CDM:
> -		hw = dpu_hw_cdm_init(id, mmio, cat, hw_mdp);
> -		break;
>  	case DPU_HW_BLK_PINGPONG:
>  		hw = dpu_hw_pingpong_init(id, mmio, cat);
>  		break;
> @@ -423,15 +416,6 @@ int dpu_rm_init(struct dpu_rm *rm,
>  		}
>  	}
>  
> -	for (i = 0; i < cat->cdm_count; i++) {
> -		rc = _dpu_rm_hw_blk_create(rm, cat, mmio, DPU_HW_BLK_CDM,
> -				cat->cdm[i].id, &cat->cdm[i]);
> -		if (rc) {
> -			DPU_ERROR("failed: cdm hw not available\n");
> -			goto fail;
> -		}
> -	}
> -
>  	return 0;
>  
>  fail:
> @@ -628,55 +612,11 @@ static int _dpu_rm_reserve_ctls(
>  	return 0;
>  }
>  
> -static int _dpu_rm_reserve_cdm(
> -		struct dpu_rm *rm,
> -		struct dpu_rm_rsvp *rsvp,
> -		uint32_t id,
> -		enum dpu_hw_blk_type type)
> -{
> -	struct dpu_rm_hw_iter iter;
> -
> -	DRM_DEBUG_KMS("type %d id %d\n", type, id);
> -
> -	dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_CDM);
> -	while (_dpu_rm_get_hw_locked(rm, &iter)) {
> -		const struct dpu_hw_cdm *cdm = to_dpu_hw_cdm(iter.blk->hw);
> -		const struct dpu_cdm_cfg *caps = cdm->caps;
> -		bool match = false;
> -
> -		if (RESERVED_BY_OTHER(iter.blk, rsvp))
> -			continue;
> -
> -		if (type == DPU_HW_BLK_INTF && id != INTF_MAX)
> -			match = test_bit(id, &caps->intf_connect);
> -
> -		DRM_DEBUG_KMS("iter: type:%d id:%d enc:%d cdm:%lu match:%d\n",
> -			      iter.blk->type, iter.blk->id, rsvp->enc_id,
> -			      caps->intf_connect, match);
> -
> -		if (!match)
> -			continue;
> -
> -		trace_dpu_rm_reserve_cdm(iter.blk->id, iter.blk->type,
> -					 rsvp->enc_id);
> -		iter.blk->rsvp_nxt = rsvp;
> -		break;
> -	}
> -
> -	if (!iter.hw) {
> -		DPU_ERROR("couldn't reserve cdm for type %d id %d\n", type, id);
> -		return -ENAVAIL;
> -	}
> -
> -	return 0;
> -}
> -
>  static int _dpu_rm_reserve_intf(
>  		struct dpu_rm *rm,
>  		struct dpu_rm_rsvp *rsvp,
>  		uint32_t id,
> -		enum dpu_hw_blk_type type,
> -		bool needs_cdm)
> +		enum dpu_hw_blk_type type)
>  {
>  	struct dpu_rm_hw_iter iter;
>  	int ret = 0;
> @@ -704,9 +644,6 @@ static int _dpu_rm_reserve_intf(
>  		return -EINVAL;
>  	}
>  
> -	if (needs_cdm)
> -		ret = _dpu_rm_reserve_cdm(rm, rsvp, id, type);
> -
>  	return ret;
>  }
>  
> @@ -723,7 +660,7 @@ static int _dpu_rm_reserve_intf_related_hw(
>  			continue;
>  		id = i + INTF_0;
>  		ret = _dpu_rm_reserve_intf(rm, rsvp, id,
> -				DPU_HW_BLK_INTF, hw_res->needs_cdm);
> +				DPU_HW_BLK_INTF);
>  		if (ret)
>  			return ret;
>  	}
> @@ -769,7 +706,6 @@ static int _dpu_rm_make_next_rsvp(
>  		return ret;
>  	}
>  
> -	/* Assign INTFs and blks whose usage is tied to them: CTL & CDM */
>  	ret = _dpu_rm_reserve_intf_related_hw(rm, rsvp, &reqs->hw_res);
>  	if (ret)
>  		return ret;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> index ae0ca50..0be51db 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
> @@ -868,10 +868,6 @@
>  	TP_printk("id:%d type:%d enc_id:%u", __entry->id, __entry->type,
>  		  __entry->enc_id)
>  );
> -DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_cdm,
> -	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id),
> -	TP_ARGS(id, type, enc_id)
> -);
>  DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_intf,
>  	TP_PROTO(uint32_t id, enum dpu_hw_blk_type type, uint32_t enc_id),
>  	TP_ARGS(id, type, enc_id)
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno

Re: [PATCH 05/14] drm/msm/dpu: enable master-slave encoders explicitly

[Jeykumar Sankaran]

On 2018-08-30 09:24, Sean Paul wrote:
> On Tue, Aug 28, 2018 at 05:39:54PM -0700, Jeykumar Sankaran wrote:
>> Identify slave-master encoders during initialization and enable
>> the encoders explicitly as the current logic has redundant and
>> ambiguous loops.
> 
> Please include a "Changes in vX" section so I don't need to figure it 
> out
> myself.
> 
Since I split these clean up changes into a new series, I was not sure
how to handle the versioning. With "changes in v4" log, Should I also
change the prefix labeling to [PATCH v4 05/14]? A couple of changes
are also introduced in this series.

Thanks,
Jeykumar S.

>> 
>> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
>> ---
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 46
> ++++++++++-------------------
>>  1 file changed, 15 insertions(+), 31 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> index 991b22c..b223bd2 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> @@ -180,6 +180,7 @@ struct dpu_encoder_virt {
>>  	unsigned int num_phys_encs;
>>  	struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
>>  	struct dpu_encoder_phys *cur_master;
>> +	struct dpu_encoder_phys *cur_slave;
>>  	struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
>> 
>>  	bool intfs_swapped;
>> @@ -1141,7 +1142,8 @@ void dpu_encoder_virt_restore(struct drm_encoder
> *drm_enc)
>>  static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
>>  {
>>  	struct dpu_encoder_virt *dpu_enc = NULL;
>> -	int i, ret = 0;
>> +	struct dpu_encoder_phys *phys  = NULL;
>> +	int ret = 0;
>>  	struct drm_display_mode *cur_mode = NULL;
>> 
>>  	if (!drm_enc) {
>> @@ -1154,21 +1156,14 @@ static void dpu_encoder_virt_enable(struct
> drm_encoder *drm_enc)
>>  	trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
>>  			     cur_mode->vdisplay);
>> 
>> -	dpu_enc->cur_master = NULL;
>> -	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
>> -		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
>> +	/* always enable slave encoder before master */
>> +	phys = dpu_enc->cur_slave;
> 
> I think this variable makes things less readable. It made sense in the
> loop since
> you're indented an extra level and they're obfuscated anyways, but 
> since
> they're
> explicit now, could you please just use dpu_enc->cur_slave/master
> directly?
> 
> With this nit and the added changelog in the commit addressed,
> 
> Reviewed-by: Sean Paul <seanpaul@chromium.org>
> 
> 
>> +	if (phys && phys->ops.enable)
>> +		phys->ops.enable(phys);
>> 
>> -		if (phys && phys->ops.is_master &&
> phys->ops.is_master(phys)) {
>> -			DPU_DEBUG_ENC(dpu_enc, "master is now idx %d\n",
> i);
>> -			dpu_enc->cur_master = phys;
>> -			break;
>> -		}
>> -	}
>> -
>> -	if (!dpu_enc->cur_master) {
>> -		DPU_ERROR("virt encoder has no master! num_phys %d\n", i);
>> -		return;
>> -	}
>> +	phys = dpu_enc->cur_master;
>> +	if (phys && phys->ops.enable)
>> +		phys->ops.enable(phys);
>> 
>>  	ret = dpu_encoder_resource_control(drm_enc,
> DPU_ENC_RC_EVENT_KICKOFF);
>>  	if (ret) {
>> @@ -1177,21 +1172,6 @@ static void dpu_encoder_virt_enable(struct
> drm_encoder *drm_enc)
>>  		return;
>>  	}
>> 
>> -	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
>> -		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
>> -
>> -		if (!phys)
>> -			continue;
>> -
>> -		if (phys != dpu_enc->cur_master) {
>> -			if (phys->ops.enable)
>> -				phys->ops.enable(phys);
>> -		}
>> -	}
>> -
>> -	if (dpu_enc->cur_master->ops.enable)
>> -		dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
>> -
>>  	_dpu_encoder_virt_enable_helper(drm_enc);
>>  }
>> 
>> @@ -2062,6 +2042,11 @@ static int dpu_encoder_virt_add_phys_encs(
>>  		++dpu_enc->num_phys_encs;
>>  	}
>> 
>> +	if (params->split_role == ENC_ROLE_SLAVE)
>> +		dpu_enc->cur_slave = enc;
>> +	else
>> +		dpu_enc->cur_master = enc;
>> +
>>  	return 0;
>>  }
>> 
>> @@ -2228,7 +2213,6 @@ int dpu_encoder_setup(struct drm_device *dev,
> struct drm_encoder *enc,
>>  	if (ret)
>>  		goto fail;
>> 
>> -	dpu_enc->cur_master = NULL;
>>  	spin_lock_init(&dpu_enc->enc_spinlock);
>> 
>>  	atomic_set(&dpu_enc->frame_done_timeout, 0);
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
> Forum,
>> a Linux Foundation Collaborative Project
>> 

-- 
Jeykumar S
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Re: [PATCH 10/14] drm/msm/dpu: move hw resource tracking to crtc state

[Jeykumar Sankaran]

On 2018-08-31 07:56, Sean Paul wrote:
> On Tue, Aug 28, 2018 at 05:39:59PM -0700, Jeykumar Sankaran wrote:
>> Prep changes for state based resource management.
>> 
>> Moves all the hw block tracking for the crtc to the state
>> object.
> 
> Changes in v4...
> 
>> 
>> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
>> ---
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 60
> ++++++++++++++++++--------------
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 22 ++++++------
>>  2 files changed, 44 insertions(+), 38 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> index e061847..7ab320d 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> @@ -163,9 +163,9 @@ static void _dpu_crtc_program_lm_output_roi(struct
> drm_crtc *crtc)
>>  	crtc_state = to_dpu_crtc_state(crtc->state);
>> 
>>  	lm_horiz_position = 0;
>> -	for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
>> +	for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) {
>>  		const struct drm_rect *lm_roi =
> &crtc_state->lm_bounds[lm_idx];
>> -		struct dpu_hw_mixer *hw_lm =
> dpu_crtc->mixers[lm_idx].hw_lm;
>> +		struct dpu_hw_mixer *hw_lm =
> crtc_state->mixers[lm_idx].hw_lm;
>>  		struct dpu_hw_mixer_cfg cfg;
>> 
>>  		if (!lm_roi || !drm_rect_visible(lm_roi))
>> @@ -246,7 +246,7 @@ static void _dpu_crtc_blend_setup_mixer(struct
> drm_crtc *crtc,
>>  					   fb ? fb->modifier : 0);
>> 
>>  		/* blend config update */
>> -		for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++)
> {
>> +		for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
>>  			_dpu_crtc_setup_blend_cfg(mixer + lm_idx,
>>  						pstate, format);
>> 
>> @@ -270,7 +270,7 @@ static void _dpu_crtc_blend_setup_mixer(struct
> drm_crtc *crtc,
>>  static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
>>  {
>>  	struct dpu_crtc *dpu_crtc;
>> -	struct dpu_crtc_state *dpu_crtc_state;
>> +	struct dpu_crtc_state *cstate;
>>  	struct dpu_crtc_mixer *mixer;
>>  	struct dpu_hw_ctl *ctl;
>>  	struct dpu_hw_mixer *lm;
>> @@ -281,17 +281,17 @@ static void _dpu_crtc_blend_setup(struct 
>> drm_crtc
> *crtc)
>>  		return;
>> 
>>  	dpu_crtc = to_dpu_crtc(crtc);
>> -	dpu_crtc_state = to_dpu_crtc_state(crtc->state);
>> -	mixer = dpu_crtc->mixers;
>> +	cstate = to_dpu_crtc_state(crtc->state);
>> +	mixer = cstate->mixers;
>> 
>>  	DPU_DEBUG("%s\n", dpu_crtc->name);
>> 
>> -	if (dpu_crtc->num_mixers > CRTC_DUAL_MIXERS) {
>> -		DPU_ERROR("invalid number mixers: %d\n",
> dpu_crtc->num_mixers);
>> +	if (cstate->num_mixers > CRTC_DUAL_MIXERS) {
> 
> This is not possible.
> 
>> +		DPU_ERROR("invalid number mixers: %d\n",
> cstate->num_mixers);
>>  		return;
>>  	}
>> 
>> -	for (i = 0; i < dpu_crtc->num_mixers; i++) {
>> +	for (i = 0; i < cstate->num_mixers; i++) {
>>  		if (!mixer[i].hw_lm || !mixer[i].hw_ctl) {
>>  			DPU_ERROR("invalid lm or ctl assigned to
> mixer\n");
>>  			return;
>> @@ -308,7 +308,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc
> *crtc)
>> 
>>  	_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer);
>> 
>> -	for (i = 0; i < dpu_crtc->num_mixers; i++) {
>> +	for (i = 0; i < cstate->num_mixers; i++) {
>>  		ctl = mixer[i].hw_ctl;
>>  		lm = mixer[i].hw_lm;
>> 
>> @@ -530,7 +530,7 @@ static void _dpu_crtc_setup_mixer_for_encoder(
>>  		struct drm_crtc *crtc,
>>  		struct drm_encoder *enc)
>>  {
>> -	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
>> +	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
>>  	struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
>>  	struct dpu_rm *rm = &dpu_kms->rm;
>>  	struct dpu_crtc_mixer *mixer;
>> @@ -542,8 +542,8 @@ static void _dpu_crtc_setup_mixer_for_encoder(
>>  	dpu_rm_init_hw_iter(&ctl_iter, enc->base.id, DPU_HW_BLK_CTL);
>> 
>>  	/* Set up all the mixers and ctls reserved by this encoder */
>> -	for (i = dpu_crtc->num_mixers; i < ARRAY_SIZE(dpu_crtc->mixers);
> i++) {
>> -		mixer = &dpu_crtc->mixers[i];
>> +	for (i = cstate->num_mixers; i < ARRAY_SIZE(cstate->mixers); i++)
> {
>> +		mixer = &cstate->mixers[i];
>> 
>>  		if (!dpu_rm_get_hw(rm, &lm_iter))
>>  			break;
>> @@ -568,7 +568,7 @@ static void _dpu_crtc_setup_mixer_for_encoder(
>> 
>>  		mixer->encoder = enc;
>> 
>> -		dpu_crtc->num_mixers++;
>> +		cstate->num_mixers++;
>>  		DPU_DEBUG("setup mixer %d: lm %d\n",
>>  				i, mixer->hw_lm->idx - LM_0);
>>  		DPU_DEBUG("setup mixer %d: ctl %d\n",
>> @@ -579,11 +579,11 @@ static void _dpu_crtc_setup_mixer_for_encoder(
>>  static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
>>  {
>>  	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
>> +	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
>>  	struct drm_encoder *enc;
>> 
>> -	dpu_crtc->num_mixers = 0;
>> -	dpu_crtc->mixers_swapped = false;
>> -	memset(dpu_crtc->mixers, 0, sizeof(dpu_crtc->mixers));
>> +	cstate->num_mixers = 0;
>> +	memset(cstate->mixers, 0, sizeof(cstate->mixers));
> 
> Why is this necessary?
> 
>> 
>>  	mutex_lock(&dpu_crtc->crtc_lock);
>>  	/* Check for mixers on all encoders attached to this crtc */
>> @@ -618,7 +618,7 @@ static void _dpu_crtc_setup_lm_bounds(struct
> drm_crtc *crtc,
>>  	crtc_split_width = _dpu_crtc_get_mixer_width(dpu_crtc, cstate,
>>  						    adj_mode);
>> 
>> -	for (i = 0; i < dpu_crtc->num_mixers; i++) {
>> +	for (i = 0; i < cstate->num_mixers; i++) {
>>  		struct drm_rect *r = &cstate->lm_bounds[i];
>>  		r->x1 = crtc_split_width * i;
>>  		r->y1 = 0;
>> @@ -635,6 +635,7 @@ static void dpu_crtc_atomic_begin(struct drm_crtc
> *crtc,
>>  		struct drm_crtc_state *old_state)
>>  {
>>  	struct dpu_crtc *dpu_crtc;
>> +	struct dpu_crtc_state *cstate;
>>  	struct drm_encoder *encoder;
>>  	struct drm_device *dev;
>>  	unsigned long flags;
>> @@ -654,10 +655,11 @@ static void dpu_crtc_atomic_begin(struct 
>> drm_crtc
> *crtc,
>>  	DPU_DEBUG("crtc%d\n", crtc->base.id);
>> 
>>  	dpu_crtc = to_dpu_crtc(crtc);
>> +	cstate = to_dpu_crtc_state(crtc->state);
>>  	dev = crtc->dev;
>>  	smmu_state = &dpu_crtc->smmu_state;
>> 
>> -	if (!dpu_crtc->num_mixers) {
>> +	if (!cstate->num_mixers) {
>>  		_dpu_crtc_setup_mixers(crtc);
>>  		_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
>>  	}
>> @@ -684,7 +686,7 @@ static void dpu_crtc_atomic_begin(struct drm_crtc
> *crtc,
>>  	 * it means we are trying to flush a CRTC whose state is disabled:
>>  	 * nothing else needs to be done.
>>  	 */
>> -	if (unlikely(!dpu_crtc->num_mixers))
>> +	if (unlikely(!cstate->num_mixers))
>>  		return;
>> 
>>  	_dpu_crtc_blend_setup(crtc);
>> @@ -748,7 +750,7 @@ static void dpu_crtc_atomic_flush(struct drm_crtc
> *crtc,
>>  	 * it means we are trying to flush a CRTC whose state is disabled:
>>  	 * nothing else needs to be done.
>>  	 */
>> -	if (unlikely(!dpu_crtc->num_mixers))
>> +	if (unlikely(!cstate->num_mixers))
>>  		return;
>> 
>>  	/*
>> @@ -863,7 +865,7 @@ void dpu_crtc_commit_kickoff(struct drm_crtc 
>> *crtc)
>>  	 * it means we are trying to start a CRTC whose state is disabled:
>>  	 * nothing else needs to be done.
>>  	 */
>> -	if (unlikely(!dpu_crtc->num_mixers))
>> +	if (unlikely(!cstate->num_mixers))
>>  		return;
>> 
>>  	DPU_ATRACE_BEGIN("crtc_commit");
>> @@ -1097,12 +1099,14 @@ static void dpu_crtc_handle_power_event(u32
> event_type, void *arg)
>>  	struct drm_crtc *crtc = arg;
>>  	struct dpu_crtc *dpu_crtc;
>>  	struct drm_encoder *encoder;
>> +	struct dpu_crtc_state *cstate;
>> 
>>  	if (!crtc) {
>>  		DPU_ERROR("invalid crtc\n");
>>  		return;
>>  	}
>>  	dpu_crtc = to_dpu_crtc(crtc);
>> +	cstate = to_dpu_crtc_state(dpu_crtc->base.state);
>> 
>>  	mutex_lock(&dpu_crtc->crtc_lock);
>> 
>> @@ -1197,9 +1201,8 @@ static void dpu_crtc_disable(struct drm_crtc
> *crtc)
>>  		dpu_power_handle_unregister_event(dpu_crtc->phandle,
>>  				dpu_crtc->power_event);
>> 
>> -	memset(dpu_crtc->mixers, 0, sizeof(dpu_crtc->mixers));
>> -	dpu_crtc->num_mixers = 0;
>> -	dpu_crtc->mixers_swapped = false;
>> +	memset(cstate->mixers, 0, sizeof(cstate->mixers));
> 
> Same question here, why is this necessary?
> 
>> +	cstate->num_mixers = 0;
>> 
>>  	/* disable clk & bw control until clk & bw properties are set */
>>  	cstate->bw_control = false;
>> @@ -1547,6 +1550,8 @@ static int _dpu_debugfs_status_show(struct
> seq_file *s, void *data)
>> 
>>  	dpu_crtc = s->private;
>>  	crtc = &dpu_crtc->base;
>> +
>> +	drm_modeset_lock(&crtc->mutex, NULL);
> 
> When I suggested this, I was hoping you'd put it in a separate patch.
> Additionally, you'll probably want modeset_lock_all instead.

crtc state retrieval is introduced in this patch. So I thought it would 
make
sense to add the locking as well a part of this patch.

> 
>>  	cstate = to_dpu_crtc_state(crtc->state);
>> 
>>  	mutex_lock(&dpu_crtc->crtc_lock);
>> @@ -1558,8 +1563,8 @@ static int _dpu_debugfs_status_show(struct
> seq_file *s, void *data)
>> 
>>  	seq_puts(s, "\n");
>> 
>> -	for (i = 0; i < dpu_crtc->num_mixers; ++i) {
>> -		m = &dpu_crtc->mixers[i];
>> +	for (i = 0; i < cstate->num_mixers; ++i) {
>> +		m = &cstate->mixers[i];
>>  		if (!m->hw_lm)
>>  			seq_printf(s, "\tmixer[%d] has no lm\n", i);
>>  		else if (!m->hw_ctl)
>> @@ -1639,6 +1644,7 @@ static int _dpu_debugfs_status_show(struct
> seq_file *s, void *data)
>>  	seq_printf(s, "vblank_enable:%d\n", dpu_crtc->vblank_requested);
>> 
>>  	mutex_unlock(&dpu_crtc->crtc_lock);
>> +	drm_modeset_unlock(&crtc->mutex);
>> 
>>  	return 0;
>>  }
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> index 5e4dc5c..7aa772f 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> @@ -121,11 +121,6 @@ struct dpu_crtc_frame_event {
>>   * struct dpu_crtc - virtualized CRTC data structure
>>   * @base          : Base drm crtc structure
>>   * @name          : ASCII description of this crtc
>> - * @num_ctls      : Number of ctl paths in use
>> - * @num_mixers    : Number of mixers in use
>> - * @mixers_swapped: Whether the mixers have been swapped for 
>> left/right
> update
>> - *                  especially in the case of DSC Merge.
>> - * @mixers        : List of active mixers
>>   * @event         : Pointer to last received drm vblank event. If 
>> there
> is a
>>   *                  pending vblank event, this will be non-null.
>>   * @vsync_count   : Running count of received vsync events
>> @@ -164,12 +159,6 @@ struct dpu_crtc {
>>  	struct drm_crtc base;
>>  	char name[DPU_CRTC_NAME_SIZE];
>> 
>> -	/* HW Resources reserved for the crtc */
>> -	u32 num_ctls;
>> -	u32 num_mixers;
>> -	bool mixers_swapped;
>> -	struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
>> -
>>  	struct drm_pending_vblank_event *event;
>>  	u32 vsync_count;
>> 
>> @@ -221,6 +210,10 @@ struct dpu_crtc {
>>   * @property_values: Current crtc property values
>>   * @input_fence_timeout_ns : Cached input fence timeout, in ns
>>   * @new_perf: new performance state being requested
>> + * @num_mixers    : Number of mixers in use
>> + * @mixers        : List of active mixers
>> + * @num_ctls      : Number of ctl paths in use
>> + * @hw_ctls       : List of active ctl paths
>>   */
>>  struct dpu_crtc_state {
>>  	struct drm_crtc_state base;
>> @@ -232,6 +225,13 @@ struct dpu_crtc_state {
>>  	uint64_t input_fence_timeout_ns;
>> 
>>  	struct dpu_core_perf_params new_perf;
>> +
>> +	/* HW Resources reserved for the crtc */
>> +	u32 num_mixers;
>> +	struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
>> +
>> +	u32 num_ctls;
>> +	struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS];
>>  };
>> 
>>  #define to_dpu_crtc_state(x) \
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
> Forum,
>> a Linux Foundation Collaborative Project
>> 

-- 
Jeykumar S
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Re: [PATCH 05/14] drm/msm/dpu: enable master-slave encoders explicitly

[Sean Paul]

On Fri, Aug 31, 2018 at 12:16:46PM -0700, Jeykumar Sankaran wrote:
> On 2018-08-30 09:24, Sean Paul wrote:
> > On Tue, Aug 28, 2018 at 05:39:54PM -0700, Jeykumar Sankaran wrote:
> > > Identify slave-master encoders during initialization and enable
> > > the encoders explicitly as the current logic has redundant and
> > > ambiguous loops.
> > 
> > Please include a "Changes in vX" section so I don't need to figure it
> > out
> > myself.
> > 
> Since I split these clean up changes into a new series, I was not sure
> how to handle the versioning. With "changes in v4" log, Should I also
> change the prefix labeling to [PATCH v4 05/14]? A couple of changes
> are also introduced in this series.

Yeah, sometimes it's best just to choose an arbitrarily high version if multiple
series' are coming together. In this case it's more simple since we're just
adding patches to the series, so v4 would have worked. As far as the new patches,
just add:

Changed in v4:
 - Introduced patch (split from "blah blah")
or
Changed in v4:
 - Introduced patch (suggested by Sean)

Sean

> 
> Thanks,
> Jeykumar S.
> 
> > > 
> > > Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> > > ---
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 46
> > ++++++++++-------------------
> > >  1 file changed, 15 insertions(+), 31 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > index 991b22c..b223bd2 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > @@ -180,6 +180,7 @@ struct dpu_encoder_virt {
> > >  	unsigned int num_phys_encs;
> > >  	struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
> > >  	struct dpu_encoder_phys *cur_master;
> > > +	struct dpu_encoder_phys *cur_slave;
> > >  	struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> > > 
> > >  	bool intfs_swapped;
> > > @@ -1141,7 +1142,8 @@ void dpu_encoder_virt_restore(struct drm_encoder
> > *drm_enc)
> > >  static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
> > >  {
> > >  	struct dpu_encoder_virt *dpu_enc = NULL;
> > > -	int i, ret = 0;
> > > +	struct dpu_encoder_phys *phys  = NULL;
> > > +	int ret = 0;
> > >  	struct drm_display_mode *cur_mode = NULL;
> > > 
> > >  	if (!drm_enc) {
> > > @@ -1154,21 +1156,14 @@ static void dpu_encoder_virt_enable(struct
> > drm_encoder *drm_enc)
> > >  	trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
> > >  			     cur_mode->vdisplay);
> > > 
> > > -	dpu_enc->cur_master = NULL;
> > > -	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
> > > -		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
> > > +	/* always enable slave encoder before master */
> > > +	phys = dpu_enc->cur_slave;
> > 
> > I think this variable makes things less readable. It made sense in the
> > loop since
> > you're indented an extra level and they're obfuscated anyways, but since
> > they're
> > explicit now, could you please just use dpu_enc->cur_slave/master
> > directly?
> > 
> > With this nit and the added changelog in the commit addressed,
> > 
> > Reviewed-by: Sean Paul <seanpaul@chromium.org>
> > 
> > 
> > > +	if (phys && phys->ops.enable)
> > > +		phys->ops.enable(phys);
> > > 
> > > -		if (phys && phys->ops.is_master &&
> > phys->ops.is_master(phys)) {
> > > -			DPU_DEBUG_ENC(dpu_enc, "master is now idx %d\n",
> > i);
> > > -			dpu_enc->cur_master = phys;
> > > -			break;
> > > -		}
> > > -	}
> > > -
> > > -	if (!dpu_enc->cur_master) {
> > > -		DPU_ERROR("virt encoder has no master! num_phys %d\n", i);
> > > -		return;
> > > -	}
> > > +	phys = dpu_enc->cur_master;
> > > +	if (phys && phys->ops.enable)
> > > +		phys->ops.enable(phys);
> > > 
> > >  	ret = dpu_encoder_resource_control(drm_enc,
> > DPU_ENC_RC_EVENT_KICKOFF);
> > >  	if (ret) {
> > > @@ -1177,21 +1172,6 @@ static void dpu_encoder_virt_enable(struct
> > drm_encoder *drm_enc)
> > >  		return;
> > >  	}
> > > 
> > > -	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
> > > -		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
> > > -
> > > -		if (!phys)
> > > -			continue;
> > > -
> > > -		if (phys != dpu_enc->cur_master) {
> > > -			if (phys->ops.enable)
> > > -				phys->ops.enable(phys);
> > > -		}
> > > -	}
> > > -
> > > -	if (dpu_enc->cur_master->ops.enable)
> > > -		dpu_enc->cur_master->ops.enable(dpu_enc->cur_master);
> > > -
> > >  	_dpu_encoder_virt_enable_helper(drm_enc);
> > >  }
> > > 
> > > @@ -2062,6 +2042,11 @@ static int dpu_encoder_virt_add_phys_encs(
> > >  		++dpu_enc->num_phys_encs;
> > >  	}
> > > 
> > > +	if (params->split_role == ENC_ROLE_SLAVE)
> > > +		dpu_enc->cur_slave = enc;
> > > +	else
> > > +		dpu_enc->cur_master = enc;
> > > +
> > >  	return 0;
> > >  }
> > > 
> > > @@ -2228,7 +2213,6 @@ int dpu_encoder_setup(struct drm_device *dev,
> > struct drm_encoder *enc,
> > >  	if (ret)
> > >  		goto fail;
> > > 
> > > -	dpu_enc->cur_master = NULL;
> > >  	spin_lock_init(&dpu_enc->enc_spinlock);
> > > 
> > >  	atomic_set(&dpu_enc->frame_done_timeout, 0);
> > > --
> > > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
> > Forum,
> > > a Linux Foundation Collaborative Project
> > > 
> 
> -- 
> Jeykumar S

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [PATCH 10/14] drm/msm/dpu: move hw resource tracking to crtc state

[Sean Paul]

On Fri, Aug 31, 2018 at 12:22:04PM -0700, Jeykumar Sankaran wrote:
> On 2018-08-31 07:56, Sean Paul wrote:
> > On Tue, Aug 28, 2018 at 05:39:59PM -0700, Jeykumar Sankaran wrote:
> > > Prep changes for state based resource management.
> > > 
> > > Moves all the hw block tracking for the crtc to the state
> > > object.
> > 
> > Changes in v4...
> > 
> > > 
> > > Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> > > ---
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 60
> > ++++++++++++++++++--------------
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 22 ++++++------
> > >  2 files changed, 44 insertions(+), 38 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > > index e061847..7ab320d 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > > @@ -163,9 +163,9 @@ static void _dpu_crtc_program_lm_output_roi(struct
> > drm_crtc *crtc)
> > >  	crtc_state = to_dpu_crtc_state(crtc->state);
> > > 
> > >  	lm_horiz_position = 0;
> > > -	for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
> > > +	for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) {
> > >  		const struct drm_rect *lm_roi =
> > &crtc_state->lm_bounds[lm_idx];
> > > -		struct dpu_hw_mixer *hw_lm =
> > dpu_crtc->mixers[lm_idx].hw_lm;
> > > +		struct dpu_hw_mixer *hw_lm =
> > crtc_state->mixers[lm_idx].hw_lm;
> > >  		struct dpu_hw_mixer_cfg cfg;
> > > 
> > >  		if (!lm_roi || !drm_rect_visible(lm_roi))
> > > @@ -246,7 +246,7 @@ static void _dpu_crtc_blend_setup_mixer(struct
> > drm_crtc *crtc,
> > >  					   fb ? fb->modifier : 0);
> > > 
> > >  		/* blend config update */
> > > -		for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++)
> > {
> > > +		for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
> > >  			_dpu_crtc_setup_blend_cfg(mixer + lm_idx,
> > >  						pstate, format);
> > > 
> > > @@ -270,7 +270,7 @@ static void _dpu_crtc_blend_setup_mixer(struct
> > drm_crtc *crtc,
> > >  static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
> > >  {
> > >  	struct dpu_crtc *dpu_crtc;
> > > -	struct dpu_crtc_state *dpu_crtc_state;
> > > +	struct dpu_crtc_state *cstate;
> > >  	struct dpu_crtc_mixer *mixer;
> > >  	struct dpu_hw_ctl *ctl;
> > >  	struct dpu_hw_mixer *lm;
> > > @@ -281,17 +281,17 @@ static void _dpu_crtc_blend_setup(struct
> > > drm_crtc
> > *crtc)
> > >  		return;
> > > 
> > >  	dpu_crtc = to_dpu_crtc(crtc);
> > > -	dpu_crtc_state = to_dpu_crtc_state(crtc->state);
> > > -	mixer = dpu_crtc->mixers;
> > > +	cstate = to_dpu_crtc_state(crtc->state);
> > > +	mixer = cstate->mixers;
> > > 
> > >  	DPU_DEBUG("%s\n", dpu_crtc->name);
> > > 
> > > -	if (dpu_crtc->num_mixers > CRTC_DUAL_MIXERS) {
> > > -		DPU_ERROR("invalid number mixers: %d\n",
> > dpu_crtc->num_mixers);
> > > +	if (cstate->num_mixers > CRTC_DUAL_MIXERS) {
> > 
> > This is not possible.
> > 
> > > +		DPU_ERROR("invalid number mixers: %d\n",
> > cstate->num_mixers);
> > >  		return;
> > >  	}
> > > 
> > > -	for (i = 0; i < dpu_crtc->num_mixers; i++) {
> > > +	for (i = 0; i < cstate->num_mixers; i++) {
> > >  		if (!mixer[i].hw_lm || !mixer[i].hw_ctl) {
> > >  			DPU_ERROR("invalid lm or ctl assigned to
> > mixer\n");
> > >  			return;
> > > @@ -308,7 +308,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc
> > *crtc)
> > > 
> > >  	_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer);
> > > 
> > > -	for (i = 0; i < dpu_crtc->num_mixers; i++) {
> > > +	for (i = 0; i < cstate->num_mixers; i++) {
> > >  		ctl = mixer[i].hw_ctl;
> > >  		lm = mixer[i].hw_lm;
> > > 
> > > @@ -530,7 +530,7 @@ static void _dpu_crtc_setup_mixer_for_encoder(
> > >  		struct drm_crtc *crtc,
> > >  		struct drm_encoder *enc)
> > >  {
> > > -	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
> > > +	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
> > >  	struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
> > >  	struct dpu_rm *rm = &dpu_kms->rm;
> > >  	struct dpu_crtc_mixer *mixer;
> > > @@ -542,8 +542,8 @@ static void _dpu_crtc_setup_mixer_for_encoder(
> > >  	dpu_rm_init_hw_iter(&ctl_iter, enc->base.id, DPU_HW_BLK_CTL);
> > > 
> > >  	/* Set up all the mixers and ctls reserved by this encoder */
> > > -	for (i = dpu_crtc->num_mixers; i < ARRAY_SIZE(dpu_crtc->mixers);
> > i++) {
> > > -		mixer = &dpu_crtc->mixers[i];
> > > +	for (i = cstate->num_mixers; i < ARRAY_SIZE(cstate->mixers); i++)
> > {
> > > +		mixer = &cstate->mixers[i];
> > > 
> > >  		if (!dpu_rm_get_hw(rm, &lm_iter))
> > >  			break;
> > > @@ -568,7 +568,7 @@ static void _dpu_crtc_setup_mixer_for_encoder(
> > > 
> > >  		mixer->encoder = enc;
> > > 
> > > -		dpu_crtc->num_mixers++;
> > > +		cstate->num_mixers++;
> > >  		DPU_DEBUG("setup mixer %d: lm %d\n",
> > >  				i, mixer->hw_lm->idx - LM_0);
> > >  		DPU_DEBUG("setup mixer %d: ctl %d\n",
> > > @@ -579,11 +579,11 @@ static void _dpu_crtc_setup_mixer_for_encoder(
> > >  static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
> > >  {
> > >  	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
> > > +	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
> > >  	struct drm_encoder *enc;
> > > 
> > > -	dpu_crtc->num_mixers = 0;
> > > -	dpu_crtc->mixers_swapped = false;
> > > -	memset(dpu_crtc->mixers, 0, sizeof(dpu_crtc->mixers));
> > > +	cstate->num_mixers = 0;
> > > +	memset(cstate->mixers, 0, sizeof(cstate->mixers));
> > 
> > Why is this necessary?
> > 
> > > 
> > >  	mutex_lock(&dpu_crtc->crtc_lock);
> > >  	/* Check for mixers on all encoders attached to this crtc */
> > > @@ -618,7 +618,7 @@ static void _dpu_crtc_setup_lm_bounds(struct
> > drm_crtc *crtc,
> > >  	crtc_split_width = _dpu_crtc_get_mixer_width(dpu_crtc, cstate,
> > >  						    adj_mode);
> > > 
> > > -	for (i = 0; i < dpu_crtc->num_mixers; i++) {
> > > +	for (i = 0; i < cstate->num_mixers; i++) {
> > >  		struct drm_rect *r = &cstate->lm_bounds[i];
> > >  		r->x1 = crtc_split_width * i;
> > >  		r->y1 = 0;
> > > @@ -635,6 +635,7 @@ static void dpu_crtc_atomic_begin(struct drm_crtc
> > *crtc,
> > >  		struct drm_crtc_state *old_state)
> > >  {
> > >  	struct dpu_crtc *dpu_crtc;
> > > +	struct dpu_crtc_state *cstate;
> > >  	struct drm_encoder *encoder;
> > >  	struct drm_device *dev;
> > >  	unsigned long flags;
> > > @@ -654,10 +655,11 @@ static void dpu_crtc_atomic_begin(struct
> > > drm_crtc
> > *crtc,
> > >  	DPU_DEBUG("crtc%d\n", crtc->base.id);
> > > 
> > >  	dpu_crtc = to_dpu_crtc(crtc);
> > > +	cstate = to_dpu_crtc_state(crtc->state);
> > >  	dev = crtc->dev;
> > >  	smmu_state = &dpu_crtc->smmu_state;
> > > 
> > > -	if (!dpu_crtc->num_mixers) {
> > > +	if (!cstate->num_mixers) {
> > >  		_dpu_crtc_setup_mixers(crtc);
> > >  		_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
> > >  	}
> > > @@ -684,7 +686,7 @@ static void dpu_crtc_atomic_begin(struct drm_crtc
> > *crtc,
> > >  	 * it means we are trying to flush a CRTC whose state is disabled:
> > >  	 * nothing else needs to be done.
> > >  	 */
> > > -	if (unlikely(!dpu_crtc->num_mixers))
> > > +	if (unlikely(!cstate->num_mixers))
> > >  		return;
> > > 
> > >  	_dpu_crtc_blend_setup(crtc);
> > > @@ -748,7 +750,7 @@ static void dpu_crtc_atomic_flush(struct drm_crtc
> > *crtc,
> > >  	 * it means we are trying to flush a CRTC whose state is disabled:
> > >  	 * nothing else needs to be done.
> > >  	 */
> > > -	if (unlikely(!dpu_crtc->num_mixers))
> > > +	if (unlikely(!cstate->num_mixers))
> > >  		return;
> > > 
> > >  	/*
> > > @@ -863,7 +865,7 @@ void dpu_crtc_commit_kickoff(struct drm_crtc
> > > *crtc)
> > >  	 * it means we are trying to start a CRTC whose state is disabled:
> > >  	 * nothing else needs to be done.
> > >  	 */
> > > -	if (unlikely(!dpu_crtc->num_mixers))
> > > +	if (unlikely(!cstate->num_mixers))
> > >  		return;
> > > 
> > >  	DPU_ATRACE_BEGIN("crtc_commit");
> > > @@ -1097,12 +1099,14 @@ static void dpu_crtc_handle_power_event(u32
> > event_type, void *arg)
> > >  	struct drm_crtc *crtc = arg;
> > >  	struct dpu_crtc *dpu_crtc;
> > >  	struct drm_encoder *encoder;
> > > +	struct dpu_crtc_state *cstate;
> > > 
> > >  	if (!crtc) {
> > >  		DPU_ERROR("invalid crtc\n");
> > >  		return;
> > >  	}
> > >  	dpu_crtc = to_dpu_crtc(crtc);
> > > +	cstate = to_dpu_crtc_state(dpu_crtc->base.state);
> > > 
> > >  	mutex_lock(&dpu_crtc->crtc_lock);
> > > 
> > > @@ -1197,9 +1201,8 @@ static void dpu_crtc_disable(struct drm_crtc
> > *crtc)
> > >  		dpu_power_handle_unregister_event(dpu_crtc->phandle,
> > >  				dpu_crtc->power_event);
> > > 
> > > -	memset(dpu_crtc->mixers, 0, sizeof(dpu_crtc->mixers));
> > > -	dpu_crtc->num_mixers = 0;
> > > -	dpu_crtc->mixers_swapped = false;
> > > +	memset(cstate->mixers, 0, sizeof(cstate->mixers));
> > 
> > Same question here, why is this necessary?
> > 
> > > +	cstate->num_mixers = 0;
> > > 
> > >  	/* disable clk & bw control until clk & bw properties are set */
> > >  	cstate->bw_control = false;
> > > @@ -1547,6 +1550,8 @@ static int _dpu_debugfs_status_show(struct
> > seq_file *s, void *data)
> > > 
> > >  	dpu_crtc = s->private;
> > >  	crtc = &dpu_crtc->base;
> > > +
> > > +	drm_modeset_lock(&crtc->mutex, NULL);
> > 
> > When I suggested this, I was hoping you'd put it in a separate patch.
> > Additionally, you'll probably want modeset_lock_all instead.
> 
> crtc state retrieval is introduced in this patch. So I thought it would make
> sense to add the locking as well a part of this patch.
> 
> > 
> > >  	cstate = to_dpu_crtc_state(crtc->state);

From this line, it looks like crtc state retrieval already existed. Not a huge
deal either way as long as the locking is corrected.

Sean

> > > 
> > >  	mutex_lock(&dpu_crtc->crtc_lock);
> > > @@ -1558,8 +1563,8 @@ static int _dpu_debugfs_status_show(struct
> > seq_file *s, void *data)
> > > 
> > >  	seq_puts(s, "\n");
> > > 
> > > -	for (i = 0; i < dpu_crtc->num_mixers; ++i) {
> > > -		m = &dpu_crtc->mixers[i];
> > > +	for (i = 0; i < cstate->num_mixers; ++i) {
> > > +		m = &cstate->mixers[i];
> > >  		if (!m->hw_lm)
> > >  			seq_printf(s, "\tmixer[%d] has no lm\n", i);
> > >  		else if (!m->hw_ctl)
> > > @@ -1639,6 +1644,7 @@ static int _dpu_debugfs_status_show(struct
> > seq_file *s, void *data)
> > >  	seq_printf(s, "vblank_enable:%d\n", dpu_crtc->vblank_requested);
> > > 
> > >  	mutex_unlock(&dpu_crtc->crtc_lock);
> > > +	drm_modeset_unlock(&crtc->mutex);
> > > 
> > >  	return 0;
> > >  }
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> > > index 5e4dc5c..7aa772f 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> > > @@ -121,11 +121,6 @@ struct dpu_crtc_frame_event {
> > >   * struct dpu_crtc - virtualized CRTC data structure
> > >   * @base          : Base drm crtc structure
> > >   * @name          : ASCII description of this crtc
> > > - * @num_ctls      : Number of ctl paths in use
> > > - * @num_mixers    : Number of mixers in use
> > > - * @mixers_swapped: Whether the mixers have been swapped for
> > > left/right
> > update
> > > - *                  especially in the case of DSC Merge.
> > > - * @mixers        : List of active mixers
> > >   * @event         : Pointer to last received drm vblank event. If
> > > there
> > is a
> > >   *                  pending vblank event, this will be non-null.
> > >   * @vsync_count   : Running count of received vsync events
> > > @@ -164,12 +159,6 @@ struct dpu_crtc {
> > >  	struct drm_crtc base;
> > >  	char name[DPU_CRTC_NAME_SIZE];
> > > 
> > > -	/* HW Resources reserved for the crtc */
> > > -	u32 num_ctls;
> > > -	u32 num_mixers;
> > > -	bool mixers_swapped;
> > > -	struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
> > > -
> > >  	struct drm_pending_vblank_event *event;
> > >  	u32 vsync_count;
> > > 
> > > @@ -221,6 +210,10 @@ struct dpu_crtc {
> > >   * @property_values: Current crtc property values
> > >   * @input_fence_timeout_ns : Cached input fence timeout, in ns
> > >   * @new_perf: new performance state being requested
> > > + * @num_mixers    : Number of mixers in use
> > > + * @mixers        : List of active mixers
> > > + * @num_ctls      : Number of ctl paths in use
> > > + * @hw_ctls       : List of active ctl paths
> > >   */
> > >  struct dpu_crtc_state {
> > >  	struct drm_crtc_state base;
> > > @@ -232,6 +225,13 @@ struct dpu_crtc_state {
> > >  	uint64_t input_fence_timeout_ns;
> > > 
> > >  	struct dpu_core_perf_params new_perf;
> > > +
> > > +	/* HW Resources reserved for the crtc */
> > > +	u32 num_mixers;
> > > +	struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
> > > +
> > > +	u32 num_ctls;
> > > +	struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS];
> > >  };
> > > 
> > >  #define to_dpu_crtc_state(x) \
> > > --
> > > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
> > Forum,
> > > a Linux Foundation Collaborative Project
> > > 
> 
> -- 
> Jeykumar S

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [PATCH 10/14] drm/msm/dpu: move hw resource tracking to crtc state

[Jeykumar Sankaran]

On 2018-08-31 07:56, Sean Paul wrote:
> On Tue, Aug 28, 2018 at 05:39:59PM -0700, Jeykumar Sankaran wrote:
>> Prep changes for state based resource management.
>> 
>> Moves all the hw block tracking for the crtc to the state
>> object.
> 
> Changes in v4...
> 
>> 
>> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
>> ---
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 60
> ++++++++++++++++++--------------
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 22 ++++++------
>>  2 files changed, 44 insertions(+), 38 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> index e061847..7ab320d 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> @@ -163,9 +163,9 @@ static void _dpu_crtc_program_lm_output_roi(struct
> drm_crtc *crtc)
>>  	crtc_state = to_dpu_crtc_state(crtc->state);
>> 
>>  	lm_horiz_position = 0;
>> -	for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
>> +	for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) {
>>  		const struct drm_rect *lm_roi =
> &crtc_state->lm_bounds[lm_idx];
>> -		struct dpu_hw_mixer *hw_lm =
> dpu_crtc->mixers[lm_idx].hw_lm;
>> +		struct dpu_hw_mixer *hw_lm =
> crtc_state->mixers[lm_idx].hw_lm;
>>  		struct dpu_hw_mixer_cfg cfg;
>> 
>>  		if (!lm_roi || !drm_rect_visible(lm_roi))
>> @@ -246,7 +246,7 @@ static void _dpu_crtc_blend_setup_mixer(struct
> drm_crtc *crtc,
>>  					   fb ? fb->modifier : 0);
>> 
>>  		/* blend config update */
>> -		for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++)
> {
>> +		for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
>>  			_dpu_crtc_setup_blend_cfg(mixer + lm_idx,
>>  						pstate, format);
>> 
>> @@ -270,7 +270,7 @@ static void _dpu_crtc_blend_setup_mixer(struct
> drm_crtc *crtc,
>>  static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
>>  {
>>  	struct dpu_crtc *dpu_crtc;
>> -	struct dpu_crtc_state *dpu_crtc_state;
>> +	struct dpu_crtc_state *cstate;
>>  	struct dpu_crtc_mixer *mixer;
>>  	struct dpu_hw_ctl *ctl;
>>  	struct dpu_hw_mixer *lm;
>> @@ -281,17 +281,17 @@ static void _dpu_crtc_blend_setup(struct 
>> drm_crtc
> *crtc)
>>  		return;
>> 
>>  	dpu_crtc = to_dpu_crtc(crtc);
>> -	dpu_crtc_state = to_dpu_crtc_state(crtc->state);
>> -	mixer = dpu_crtc->mixers;
>> +	cstate = to_dpu_crtc_state(crtc->state);
>> +	mixer = cstate->mixers;
>> 
>>  	DPU_DEBUG("%s\n", dpu_crtc->name);
>> 
>> -	if (dpu_crtc->num_mixers > CRTC_DUAL_MIXERS) {
>> -		DPU_ERROR("invalid number mixers: %d\n",
> dpu_crtc->num_mixers);
>> +	if (cstate->num_mixers > CRTC_DUAL_MIXERS) {
> 
> This is not possible.
> 
>> +		DPU_ERROR("invalid number mixers: %d\n",
> cstate->num_mixers);
>>  		return;
>>  	}
>> 
>> -	for (i = 0; i < dpu_crtc->num_mixers; i++) {
>> +	for (i = 0; i < cstate->num_mixers; i++) {
>>  		if (!mixer[i].hw_lm || !mixer[i].hw_ctl) {
>>  			DPU_ERROR("invalid lm or ctl assigned to
> mixer\n");
>>  			return;
>> @@ -308,7 +308,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc
> *crtc)
>> 
>>  	_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer);
>> 
>> -	for (i = 0; i < dpu_crtc->num_mixers; i++) {
>> +	for (i = 0; i < cstate->num_mixers; i++) {
>>  		ctl = mixer[i].hw_ctl;
>>  		lm = mixer[i].hw_lm;
>> 
>> @@ -530,7 +530,7 @@ static void _dpu_crtc_setup_mixer_for_encoder(
>>  		struct drm_crtc *crtc,
>>  		struct drm_encoder *enc)
>>  {
>> -	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
>> +	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
>>  	struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
>>  	struct dpu_rm *rm = &dpu_kms->rm;
>>  	struct dpu_crtc_mixer *mixer;
>> @@ -542,8 +542,8 @@ static void _dpu_crtc_setup_mixer_for_encoder(
>>  	dpu_rm_init_hw_iter(&ctl_iter, enc->base.id, DPU_HW_BLK_CTL);
>> 
>>  	/* Set up all the mixers and ctls reserved by this encoder */
>> -	for (i = dpu_crtc->num_mixers; i < ARRAY_SIZE(dpu_crtc->mixers);
> i++) {
>> -		mixer = &dpu_crtc->mixers[i];
>> +	for (i = cstate->num_mixers; i < ARRAY_SIZE(cstate->mixers); i++)
> {
>> +		mixer = &cstate->mixers[i];
>> 
>>  		if (!dpu_rm_get_hw(rm, &lm_iter))
>>  			break;
>> @@ -568,7 +568,7 @@ static void _dpu_crtc_setup_mixer_for_encoder(
>> 
>>  		mixer->encoder = enc;
>> 
>> -		dpu_crtc->num_mixers++;
>> +		cstate->num_mixers++;
>>  		DPU_DEBUG("setup mixer %d: lm %d\n",
>>  				i, mixer->hw_lm->idx - LM_0);
>>  		DPU_DEBUG("setup mixer %d: ctl %d\n",
>> @@ -579,11 +579,11 @@ static void _dpu_crtc_setup_mixer_for_encoder(
>>  static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
>>  {
>>  	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
>> +	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
>>  	struct drm_encoder *enc;
>> 
>> -	dpu_crtc->num_mixers = 0;
>> -	dpu_crtc->mixers_swapped = false;
>> -	memset(dpu_crtc->mixers, 0, sizeof(dpu_crtc->mixers));
>> +	cstate->num_mixers = 0;
>> +	memset(cstate->mixers, 0, sizeof(cstate->mixers));
> 
> Why is this necessary?
> 
>> 
>>  	mutex_lock(&dpu_crtc->crtc_lock);
>>  	/* Check for mixers on all encoders attached to this crtc */
>> @@ -618,7 +618,7 @@ static void _dpu_crtc_setup_lm_bounds(struct
> drm_crtc *crtc,
>>  	crtc_split_width = _dpu_crtc_get_mixer_width(dpu_crtc, cstate,
>>  						    adj_mode);
>> 
>> -	for (i = 0; i < dpu_crtc->num_mixers; i++) {
>> +	for (i = 0; i < cstate->num_mixers; i++) {
>>  		struct drm_rect *r = &cstate->lm_bounds[i];
>>  		r->x1 = crtc_split_width * i;
>>  		r->y1 = 0;
>> @@ -635,6 +635,7 @@ static void dpu_crtc_atomic_begin(struct drm_crtc
> *crtc,
>>  		struct drm_crtc_state *old_state)
>>  {
>>  	struct dpu_crtc *dpu_crtc;
>> +	struct dpu_crtc_state *cstate;
>>  	struct drm_encoder *encoder;
>>  	struct drm_device *dev;
>>  	unsigned long flags;
>> @@ -654,10 +655,11 @@ static void dpu_crtc_atomic_begin(struct 
>> drm_crtc
> *crtc,
>>  	DPU_DEBUG("crtc%d\n", crtc->base.id);
>> 
>>  	dpu_crtc = to_dpu_crtc(crtc);
>> +	cstate = to_dpu_crtc_state(crtc->state);
>>  	dev = crtc->dev;
>>  	smmu_state = &dpu_crtc->smmu_state;
>> 
>> -	if (!dpu_crtc->num_mixers) {
>> +	if (!cstate->num_mixers) {
>>  		_dpu_crtc_setup_mixers(crtc);
>>  		_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
>>  	}
>> @@ -684,7 +686,7 @@ static void dpu_crtc_atomic_begin(struct drm_crtc
> *crtc,
>>  	 * it means we are trying to flush a CRTC whose state is disabled:
>>  	 * nothing else needs to be done.
>>  	 */
>> -	if (unlikely(!dpu_crtc->num_mixers))
>> +	if (unlikely(!cstate->num_mixers))
>>  		return;
>> 
>>  	_dpu_crtc_blend_setup(crtc);
>> @@ -748,7 +750,7 @@ static void dpu_crtc_atomic_flush(struct drm_crtc
> *crtc,
>>  	 * it means we are trying to flush a CRTC whose state is disabled:
>>  	 * nothing else needs to be done.
>>  	 */
>> -	if (unlikely(!dpu_crtc->num_mixers))
>> +	if (unlikely(!cstate->num_mixers))
>>  		return;
>> 
>>  	/*
>> @@ -863,7 +865,7 @@ void dpu_crtc_commit_kickoff(struct drm_crtc 
>> *crtc)
>>  	 * it means we are trying to start a CRTC whose state is disabled:
>>  	 * nothing else needs to be done.
>>  	 */
>> -	if (unlikely(!dpu_crtc->num_mixers))
>> +	if (unlikely(!cstate->num_mixers))
>>  		return;
>> 
>>  	DPU_ATRACE_BEGIN("crtc_commit");
>> @@ -1097,12 +1099,14 @@ static void dpu_crtc_handle_power_event(u32
> event_type, void *arg)
>>  	struct drm_crtc *crtc = arg;
>>  	struct dpu_crtc *dpu_crtc;
>>  	struct drm_encoder *encoder;
>> +	struct dpu_crtc_state *cstate;
>> 
>>  	if (!crtc) {
>>  		DPU_ERROR("invalid crtc\n");
>>  		return;
>>  	}
>>  	dpu_crtc = to_dpu_crtc(crtc);
>> +	cstate = to_dpu_crtc_state(dpu_crtc->base.state);
>> 
>>  	mutex_lock(&dpu_crtc->crtc_lock);
>> 
>> @@ -1197,9 +1201,8 @@ static void dpu_crtc_disable(struct drm_crtc
> *crtc)
>>  		dpu_power_handle_unregister_event(dpu_crtc->phandle,
>>  				dpu_crtc->power_event);
>> 
>> -	memset(dpu_crtc->mixers, 0, sizeof(dpu_crtc->mixers));
>> -	dpu_crtc->num_mixers = 0;
>> -	dpu_crtc->mixers_swapped = false;
>> +	memset(cstate->mixers, 0, sizeof(cstate->mixers));
> 
> Same question here, why is this necessary?

Analysing more on the need for this memset. After a crtc is disabled,
it can also be used with a mode where the needed no. of layer mixers
can be different than the current one. So isn't it always safe to
clear the stale pointers to hw blocks?

Thanks and Regards,
Jeykumar S.

> 
>> +	cstate->num_mixers = 0;
>> 
>>  	/* disable clk & bw control until clk & bw properties are set */
>>  	cstate->bw_control = false;
>> @@ -1547,6 +1550,8 @@ static int _dpu_debugfs_status_show(struct
> seq_file *s, void *data)
>> 
>>  	dpu_crtc = s->private;
>>  	crtc = &dpu_crtc->base;
>> +
>> +	drm_modeset_lock(&crtc->mutex, NULL);
> 
> When I suggested this, I was hoping you'd put it in a separate patch.
> Additionally, you'll probably want modeset_lock_all instead.
> 
>>  	cstate = to_dpu_crtc_state(crtc->state);
>> 
>>  	mutex_lock(&dpu_crtc->crtc_lock);
>> @@ -1558,8 +1563,8 @@ static int _dpu_debugfs_status_show(struct
> seq_file *s, void *data)
>> 
>>  	seq_puts(s, "\n");
>> 
>> -	for (i = 0; i < dpu_crtc->num_mixers; ++i) {
>> -		m = &dpu_crtc->mixers[i];
>> +	for (i = 0; i < cstate->num_mixers; ++i) {
>> +		m = &cstate->mixers[i];
>>  		if (!m->hw_lm)
>>  			seq_printf(s, "\tmixer[%d] has no lm\n", i);
>>  		else if (!m->hw_ctl)
>> @@ -1639,6 +1644,7 @@ static int _dpu_debugfs_status_show(struct
> seq_file *s, void *data)
>>  	seq_printf(s, "vblank_enable:%d\n", dpu_crtc->vblank_requested);
>> 
>>  	mutex_unlock(&dpu_crtc->crtc_lock);
>> +	drm_modeset_unlock(&crtc->mutex);
>> 
>>  	return 0;
>>  }
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> index 5e4dc5c..7aa772f 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
>> @@ -121,11 +121,6 @@ struct dpu_crtc_frame_event {
>>   * struct dpu_crtc - virtualized CRTC data structure
>>   * @base          : Base drm crtc structure
>>   * @name          : ASCII description of this crtc
>> - * @num_ctls      : Number of ctl paths in use
>> - * @num_mixers    : Number of mixers in use
>> - * @mixers_swapped: Whether the mixers have been swapped for 
>> left/right
> update
>> - *                  especially in the case of DSC Merge.
>> - * @mixers        : List of active mixers
>>   * @event         : Pointer to last received drm vblank event. If 
>> there
> is a
>>   *                  pending vblank event, this will be non-null.
>>   * @vsync_count   : Running count of received vsync events
>> @@ -164,12 +159,6 @@ struct dpu_crtc {
>>  	struct drm_crtc base;
>>  	char name[DPU_CRTC_NAME_SIZE];
>> 
>> -	/* HW Resources reserved for the crtc */
>> -	u32 num_ctls;
>> -	u32 num_mixers;
>> -	bool mixers_swapped;
>> -	struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
>> -
>>  	struct drm_pending_vblank_event *event;
>>  	u32 vsync_count;
>> 
>> @@ -221,6 +210,10 @@ struct dpu_crtc {
>>   * @property_values: Current crtc property values
>>   * @input_fence_timeout_ns : Cached input fence timeout, in ns
>>   * @new_perf: new performance state being requested
>> + * @num_mixers    : Number of mixers in use
>> + * @mixers        : List of active mixers
>> + * @num_ctls      : Number of ctl paths in use
>> + * @hw_ctls       : List of active ctl paths
>>   */
>>  struct dpu_crtc_state {
>>  	struct drm_crtc_state base;
>> @@ -232,6 +225,13 @@ struct dpu_crtc_state {
>>  	uint64_t input_fence_timeout_ns;
>> 
>>  	struct dpu_core_perf_params new_perf;
>> +
>> +	/* HW Resources reserved for the crtc */
>> +	u32 num_mixers;
>> +	struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
>> +
>> +	u32 num_ctls;
>> +	struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS];
>>  };
>> 
>>  #define to_dpu_crtc_state(x) \
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
> Forum,
>> a Linux Foundation Collaborative Project
>> 

-- 
Jeykumar S
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Re: [PATCH 12/14] drm/msm/dpu: remove topology name

[Jeykumar Sankaran]

On 2018-08-31 09:08, Sean Paul wrote:
> On Tue, Aug 28, 2018 at 05:40:01PM -0700, Jeykumar Sankaran wrote:
>> Strip down the support for topology enums. It
>> can be replaced with simple hw count checks.
>> 
> 
> Changes in v4:
> ...
> 
>> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
>> ---
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        |  3 --
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h        |  1 -
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |  9 ++++--
>>  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  7 +++--
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c             | 36
> ++++++----------------
>>  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h             | 24 
>> ---------------
>>  6 files changed, 19 insertions(+), 61 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> index dbf669e..56ef349 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> @@ -1013,7 +1013,6 @@ static void dpu_encoder_virt_mode_set(struct
> drm_encoder *drm_enc,
>>  	struct drm_connector *conn = NULL, *conn_iter;
>>  	struct dpu_rm_hw_iter pp_iter, ctl_iter;
>>  	struct msm_display_topology topology;
>> -	enum dpu_rm_topology_name topology_name;
>>  	struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL };
>>  	int i = 0, ret;
>> 
>> @@ -1069,7 +1068,6 @@ static void dpu_encoder_virt_mode_set(struct
> drm_encoder *drm_enc,
>>  		hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw;
>>  	}
>> 
>> -	topology_name = dpu_rm_get_topology_name(topology);
>>  	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
>>  		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
>> 
>> @@ -1089,7 +1087,6 @@ static void dpu_encoder_virt_mode_set(struct
> drm_encoder *drm_enc,
>>  			phys->hw_ctl = hw_ctl[i];
>> 
>>  			phys->connector = conn->state->connector;
>> -			phys->topology_name = topology_name;
>>  			if (phys->ops.mode_set)
>>  				phys->ops.mode_set(phys, mode, adj_mode);
>>  		}
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>> index 60f809f..c5600e6 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>> @@ -35,7 +35,6 @@
>>   * @needs_cdm:	Encoder requests a CDM based on pixel format
> conversion needs
>>   * @display_num_of_h_tiles: Number of horizontal tiles in case of 
>> split
>>   *                          interface
>> - * @topology:   Topology of the display
>>   */
>>  struct dpu_encoder_hw_resources {
>>  	enum dpu_intf_mode intfs[INTF_MAX];
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
>> index b3917e0..b5fc65c 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
>> @@ -24,6 +24,7 @@
>>  #include "dpu_hw_top.h"
>>  #include "dpu_hw_cdm.h"
>>  #include "dpu_encoder.h"
>> +#include "dpu_crtc.h"
>> 
>>  #define DPU_ENCODER_NAME_MAX	16
>> 
>> @@ -213,7 +214,6 @@ struct dpu_encoder_irq {
>>   * @split_role:		Role to play in a split-panel
> configuration
>>   * @intf_mode:		Interface mode
>>   * @intf_idx:		Interface index on dpu hardware
>> - * @topology_name:	topology selected for the display
>>   * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
>>   * @enable_state:	Enable state tracking
>>   * @vblank_refcount:	Reference count of vblank request
>> @@ -243,7 +243,6 @@ struct dpu_encoder_phys {
>>  	enum dpu_enc_split_role split_role;
>>  	enum dpu_intf_mode intf_mode;
>>  	enum dpu_intf intf_idx;
>> -	enum dpu_rm_topology_name topology_name;
>>  	spinlock_t *enc_spinlock;
>>  	enum dpu_enc_enable_state enable_state;
>>  	atomic_t vblank_refcount;
>> @@ -361,11 +360,15 @@ struct dpu_encoder_phys
> *dpu_encoder_phys_cmd_init(
>>  static inline enum dpu_3d_blend_mode
> dpu_encoder_helper_get_3d_blend_mode(
>>  		struct dpu_encoder_phys *phys_enc)
>>  {
>> +	struct dpu_crtc_state *dpu_cstate;
>> +
>>  	if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
>>  		return BLEND_3D_NONE;
>> 
>> +	dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
>> +
>>  	if (phys_enc->split_role == ENC_ROLE_SOLO &&
>> -	    phys_enc->topology_name == DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE)
>> +	    (dpu_cstate->num_mixers == 2))
> 
> I guess this should be CRTC_DUAL_MIXERS? Perhaps you should add a 
> helper
> called
> dpu_crtc_state_is_stereo() instead of littering these checks 
> everywhere.
> 
>>  		return BLEND_3D_H_ROW_INT;
>> 
>>  	return BLEND_3D_NONE;
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>> index 6de13f4..1643e2f 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>> @@ -355,13 +355,14 @@ static void 
>> dpu_encoder_phys_vid_underrun_irq(void
> *arg, int irq_idx)
>> 
>>  static bool _dpu_encoder_phys_is_dual_ctl(struct dpu_encoder_phys
> *phys_enc)
>>  {
>> +	struct dpu_crtc_state *dpu_cstate;
>> +
>>  	if (!phys_enc)
>>  		return false;
>> 
>> -	if (phys_enc->topology_name == DPU_RM_TOPOLOGY_DUALPIPE)
>> -		return true;
>> +	dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
>> 
>> -	return false;
>> +	return (dpu_cstate->num_ctls > 1);
> 
> Unnecessary parens
> 
>>  }
>> 
>>  static bool dpu_encoder_phys_vid_needs_single_flush(
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> index 13c0a36..fbd489f 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> @@ -33,7 +33,6 @@
>>  				(t).num_intf == (r).num_intf)
>> 
>>  struct dpu_rm_topology_def {
>> -	enum dpu_rm_topology_name top_name;
>>  	int num_lm;
>>  	int num_comp_enc;
>>  	int num_intf;
>> @@ -42,10 +41,10 @@ struct dpu_rm_topology_def {
>>  };
>> 
>>  static const struct dpu_rm_topology_def g_top_table[] = {
>> -	{   DPU_RM_TOPOLOGY_NONE,                 0, 0, 0, 0, false },
>> -	{   DPU_RM_TOPOLOGY_SINGLEPIPE,           1, 0, 1, 1, false },
>> -	{   DPU_RM_TOPOLOGY_DUALPIPE,             2, 0, 2, 2, true  },
>> -	{   DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,     2, 0, 1, 1, false },
>> +	{   0, 0, 0, 0, false },
>> +	{   1, 0, 1, 1, false },
>> +	{   2, 0, 2, 2, true  },
>> +	{   2, 0, 1, 1, false },
> 
> You don't need this. The data it provides can be deduced already:
> num_ctl == num_intf
> needs_split_display == (num_intf > 1)
> 
>>  };
>> 
>>  /**
>> @@ -72,13 +71,11 @@ struct dpu_rm_requirements {
>>   * @enc_id:	Reservations are tracked by Encoder DRM object ID.
>>   *		CRTCs may be connected to multiple Encoders.
>>   *		An encoder or connector id identifies the display path.
>> - * @topology	DRM<->HW topology use case
>>   */
>>  struct dpu_rm_rsvp {
>>  	struct list_head list;
>>  	uint32_t seq;
>>  	uint32_t enc_id;
>> -	enum dpu_rm_topology_name topology;
>>  };
>> 
>>  /**
>> @@ -122,8 +119,8 @@ static void _dpu_rm_print_rsvps(
>>  	DPU_DEBUG("%d\n", stage);
>> 
>>  	list_for_each_entry(rsvp, &rm->rsvps, list) {
>> -		DRM_DEBUG_KMS("%d rsvp[s%ue%u] topology %d\n", stage,
> rsvp->seq,
>> -			      rsvp->enc_id, rsvp->topology);
>> +		DRM_DEBUG_KMS("%d rsvp[s%ue%u]\n", stage, rsvp->seq,
>> +			      rsvp->enc_id);
>>  	}
>> 
>>  	for (type = 0; type < DPU_HW_BLK_MAX; type++) {
>> @@ -146,18 +143,6 @@ struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm
> *rm)
>>  	return rm->hw_mdp;
>>  }
>> 
>> -enum dpu_rm_topology_name
>> -dpu_rm_get_topology_name(struct msm_display_topology topology)
>> -{
>> -	int i;
>> -
>> -	for (i = 0; i < DPU_RM_TOPOLOGY_MAX; i++)
>> -		if (RM_IS_TOPOLOGY_MATCH(g_top_table[i], topology))
>> -			return g_top_table[i].top_name;
>> -
>> -	return DPU_RM_TOPOLOGY_NONE;
>> -}
>> -
>>  void dpu_rm_init_hw_iter(
>>  		struct dpu_rm_hw_iter *iter,
>>  		uint32_t enc_id,
>> @@ -760,7 +745,6 @@ static int _dpu_rm_make_next_rsvp(
>>  	/* Create reservation info, tag reserved blocks with it as we go
> */
>>  	rsvp->seq = ++rm->rsvp_next_seq;
>>  	rsvp->enc_id = enc->base.id;
>> -	rsvp->topology = reqs->topology->top_name;
>>  	list_add_tail(&rsvp->list, &rm->rsvps);
>> 
>>  	ret = _dpu_rm_reserve_lms(rm, rsvp, reqs);
>> @@ -807,7 +791,7 @@ static int _dpu_rm_populate_requirements(
>> 
>>  	dpu_encoder_get_hw_resources(enc, &reqs->hw_res, conn_state);
>> 
>> -	for (i = 0; i < DPU_RM_TOPOLOGY_MAX; i++) {
>> +	for (i = 0; i < ARRAY_SIZE(g_top_table); i++) {
>>  		if (RM_IS_TOPOLOGY_MATCH(g_top_table[i],
>>  					req_topology)) {
>>  			reqs->topology = &g_top_table[i];
> 
> Since you can get rid of g_top_table, you can get rid of reqs->topology
> too.
> 
DPU RM is using reqs->topology (ie. struct dpu_rm_topology_def) to 
represent
the hw_block requirements for a display. Removing the structure
might require changes in rest of RM alloc functions.

If you can hold off on this, I am planning to address your comment in 
the
RM refactor series.

Jeykumar S.

>> @@ -831,9 +815,8 @@ static int _dpu_rm_populate_requirements(
>> 
>>  	DRM_DEBUG_KMS("top_ctrl: 0x%llX num_h_tiles: %d\n",
> reqs->top_ctrl,
>>  		      reqs->hw_res.display_num_of_h_tiles);
>> -	DRM_DEBUG_KMS("num_lm: %d num_ctl: %d topology: %d split_display:
> %d\n",
>> +	DRM_DEBUG_KMS("num_lm: %d num_ctl: %d split_display: %d\n",
>>  		      reqs->topology->num_lm, reqs->topology->num_ctl,
>> -		      reqs->topology->top_name,
>>  		      reqs->topology->needs_split_display);
>> 
>>  	return 0;
>> @@ -969,8 +952,7 @@ static int _dpu_rm_commit_rsvp(
>>  	}
>> 
>>  	if (!ret)
>> -		DRM_DEBUG_KMS("rsrv enc %d topology %d\n", rsvp->enc_id,
>> -			      rsvp->topology);
>> +		DRM_DEBUG_KMS("rsrv enc %d\n", rsvp->enc_id);
> 
> This debug message doesn't provide any value any longer.
> 
>> 
>>  	return ret;
>>  }
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> index ffd1841..6fd9e7b 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> @@ -21,21 +21,6 @@
>>  #include "dpu_hw_top.h"
>> 
>>  /**
>> - * enum dpu_rm_topology_name - HW resource use case in use by 
>> connector
>> - * @DPU_RM_TOPOLOGY_NONE:                 No topology in use 
>> currently
>> - * @DPU_RM_TOPOLOGY_SINGLEPIPE:           1 LM, 1 PP, 1 INTF/WB
>> - * @DPU_RM_TOPOLOGY_DUALPIPE:             2 LM, 2 PP, 2 INTF/WB
>> - * @DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE:     2 LM, 2 PP, 3DMux, 1 
>> INTF/WB
>> - */
>> -enum dpu_rm_topology_name {
>> -	DPU_RM_TOPOLOGY_NONE = 0,
>> -	DPU_RM_TOPOLOGY_SINGLEPIPE,
>> -	DPU_RM_TOPOLOGY_DUALPIPE,
>> -	DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,
>> -	DPU_RM_TOPOLOGY_MAX,
>> -};
>> -
>> -/**
>>   * enum dpu_rm_topology_control - HW resource use case in use by
> connector
>>   * @DPU_RM_TOPCTL_RESERVE_LOCK: If set, in AtomicTest phase, after a
> successful
>>   *                              test, reserve the resources for this
> display.
>> @@ -187,13 +172,4 @@ void dpu_rm_init_hw_iter(
>>   */
>>  int dpu_rm_check_property_topctl(uint64_t val);
>> 
>> -/**
>> - * dpu_rm_get_topology_name - returns the name of the the given
> topology
>> - *                            definition
>> - * @topology: topology definition
>> - * @Return: name of the topology
>> - */
>> -enum dpu_rm_topology_name
>> -dpu_rm_get_topology_name(struct msm_display_topology topology);
>> -
>>  #endif /* __DPU_RM_H__ */
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
> Forum,
>> a Linux Foundation Collaborative Project
>> 

-- 
Jeykumar S
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Freedreno mailing list
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Re: [PATCH 12/14] drm/msm/dpu: remove topology name

[Sean Paul]

On Tue, Sep 04, 2018 at 04:03:25PM -0700, Jeykumar Sankaran wrote:
> On 2018-08-31 09:08, Sean Paul wrote:
> > On Tue, Aug 28, 2018 at 05:40:01PM -0700, Jeykumar Sankaran wrote:
> > > Strip down the support for topology enums. It
> > > can be replaced with simple hw count checks.
> > > 
> > 
> > Changes in v4:
> > ...
> > 
> > > Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
> > > ---
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c        |  3 --
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h        |  1 -
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |  9 ++++--
> > >  .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  7 +++--
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c             | 36
> > ++++++----------------
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h             | 24
> > > ---------------
> > >  6 files changed, 19 insertions(+), 61 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > index dbf669e..56ef349 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > @@ -1013,7 +1013,6 @@ static void dpu_encoder_virt_mode_set(struct
> > drm_encoder *drm_enc,
> > >  	struct drm_connector *conn = NULL, *conn_iter;
> > >  	struct dpu_rm_hw_iter pp_iter, ctl_iter;
> > >  	struct msm_display_topology topology;
> > > -	enum dpu_rm_topology_name topology_name;
> > >  	struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL };
> > >  	int i = 0, ret;
> > > 
> > > @@ -1069,7 +1068,6 @@ static void dpu_encoder_virt_mode_set(struct
> > drm_encoder *drm_enc,
> > >  		hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw;
> > >  	}
> > > 
> > > -	topology_name = dpu_rm_get_topology_name(topology);
> > >  	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
> > >  		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
> > > 
> > > @@ -1089,7 +1087,6 @@ static void dpu_encoder_virt_mode_set(struct
> > drm_encoder *drm_enc,
> > >  			phys->hw_ctl = hw_ctl[i];
> > > 
> > >  			phys->connector = conn->state->connector;
> > > -			phys->topology_name = topology_name;
> > >  			if (phys->ops.mode_set)
> > >  				phys->ops.mode_set(phys, mode, adj_mode);
> > >  		}
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> > > index 60f809f..c5600e6 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> > > @@ -35,7 +35,6 @@
> > >   * @needs_cdm:	Encoder requests a CDM based on pixel format
> > conversion needs
> > >   * @display_num_of_h_tiles: Number of horizontal tiles in case of
> > > split
> > >   *                          interface
> > > - * @topology:   Topology of the display
> > >   */
> > >  struct dpu_encoder_hw_resources {
> > >  	enum dpu_intf_mode intfs[INTF_MAX];
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> > > index b3917e0..b5fc65c 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> > > @@ -24,6 +24,7 @@
> > >  #include "dpu_hw_top.h"
> > >  #include "dpu_hw_cdm.h"
> > >  #include "dpu_encoder.h"
> > > +#include "dpu_crtc.h"
> > > 
> > >  #define DPU_ENCODER_NAME_MAX	16
> > > 
> > > @@ -213,7 +214,6 @@ struct dpu_encoder_irq {
> > >   * @split_role:		Role to play in a split-panel
> > configuration
> > >   * @intf_mode:		Interface mode
> > >   * @intf_idx:		Interface index on dpu hardware
> > > - * @topology_name:	topology selected for the display
> > >   * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
> > >   * @enable_state:	Enable state tracking
> > >   * @vblank_refcount:	Reference count of vblank request
> > > @@ -243,7 +243,6 @@ struct dpu_encoder_phys {
> > >  	enum dpu_enc_split_role split_role;
> > >  	enum dpu_intf_mode intf_mode;
> > >  	enum dpu_intf intf_idx;
> > > -	enum dpu_rm_topology_name topology_name;
> > >  	spinlock_t *enc_spinlock;
> > >  	enum dpu_enc_enable_state enable_state;
> > >  	atomic_t vblank_refcount;
> > > @@ -361,11 +360,15 @@ struct dpu_encoder_phys
> > *dpu_encoder_phys_cmd_init(
> > >  static inline enum dpu_3d_blend_mode
> > dpu_encoder_helper_get_3d_blend_mode(
> > >  		struct dpu_encoder_phys *phys_enc)
> > >  {
> > > +	struct dpu_crtc_state *dpu_cstate;
> > > +
> > >  	if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
> > >  		return BLEND_3D_NONE;
> > > 
> > > +	dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
> > > +
> > >  	if (phys_enc->split_role == ENC_ROLE_SOLO &&
> > > -	    phys_enc->topology_name == DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE)
> > > +	    (dpu_cstate->num_mixers == 2))
> > 
> > I guess this should be CRTC_DUAL_MIXERS? Perhaps you should add a helper
> > called
> > dpu_crtc_state_is_stereo() instead of littering these checks everywhere.
> > 
> > >  		return BLEND_3D_H_ROW_INT;
> > > 
> > >  	return BLEND_3D_NONE;
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> > > index 6de13f4..1643e2f 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> > > @@ -355,13 +355,14 @@ static void
> > > dpu_encoder_phys_vid_underrun_irq(void
> > *arg, int irq_idx)
> > > 
> > >  static bool _dpu_encoder_phys_is_dual_ctl(struct dpu_encoder_phys
> > *phys_enc)
> > >  {
> > > +	struct dpu_crtc_state *dpu_cstate;
> > > +
> > >  	if (!phys_enc)
> > >  		return false;
> > > 
> > > -	if (phys_enc->topology_name == DPU_RM_TOPOLOGY_DUALPIPE)
> > > -		return true;
> > > +	dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
> > > 
> > > -	return false;
> > > +	return (dpu_cstate->num_ctls > 1);
> > 
> > Unnecessary parens
> > 
> > >  }
> > > 
> > >  static bool dpu_encoder_phys_vid_needs_single_flush(
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > > index 13c0a36..fbd489f 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > > @@ -33,7 +33,6 @@
> > >  				(t).num_intf == (r).num_intf)
> > > 
> > >  struct dpu_rm_topology_def {
> > > -	enum dpu_rm_topology_name top_name;
> > >  	int num_lm;
> > >  	int num_comp_enc;
> > >  	int num_intf;
> > > @@ -42,10 +41,10 @@ struct dpu_rm_topology_def {
> > >  };
> > > 
> > >  static const struct dpu_rm_topology_def g_top_table[] = {
> > > -	{   DPU_RM_TOPOLOGY_NONE,                 0, 0, 0, 0, false },
> > > -	{   DPU_RM_TOPOLOGY_SINGLEPIPE,           1, 0, 1, 1, false },
> > > -	{   DPU_RM_TOPOLOGY_DUALPIPE,             2, 0, 2, 2, true  },
> > > -	{   DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,     2, 0, 1, 1, false },
> > > +	{   0, 0, 0, 0, false },
> > > +	{   1, 0, 1, 1, false },
> > > +	{   2, 0, 2, 2, true  },
> > > +	{   2, 0, 1, 1, false },
> > 
> > You don't need this. The data it provides can be deduced already:
> > num_ctl == num_intf
> > needs_split_display == (num_intf > 1)
> > 
> > >  };
> > > 
> > >  /**
> > > @@ -72,13 +71,11 @@ struct dpu_rm_requirements {
> > >   * @enc_id:	Reservations are tracked by Encoder DRM object ID.
> > >   *		CRTCs may be connected to multiple Encoders.
> > >   *		An encoder or connector id identifies the display path.
> > > - * @topology	DRM<->HW topology use case
> > >   */
> > >  struct dpu_rm_rsvp {
> > >  	struct list_head list;
> > >  	uint32_t seq;
> > >  	uint32_t enc_id;
> > > -	enum dpu_rm_topology_name topology;
> > >  };
> > > 
> > >  /**
> > > @@ -122,8 +119,8 @@ static void _dpu_rm_print_rsvps(
> > >  	DPU_DEBUG("%d\n", stage);
> > > 
> > >  	list_for_each_entry(rsvp, &rm->rsvps, list) {
> > > -		DRM_DEBUG_KMS("%d rsvp[s%ue%u] topology %d\n", stage,
> > rsvp->seq,
> > > -			      rsvp->enc_id, rsvp->topology);
> > > +		DRM_DEBUG_KMS("%d rsvp[s%ue%u]\n", stage, rsvp->seq,
> > > +			      rsvp->enc_id);
> > >  	}
> > > 
> > >  	for (type = 0; type < DPU_HW_BLK_MAX; type++) {
> > > @@ -146,18 +143,6 @@ struct dpu_hw_mdp *dpu_rm_get_mdp(struct dpu_rm
> > *rm)
> > >  	return rm->hw_mdp;
> > >  }
> > > 
> > > -enum dpu_rm_topology_name
> > > -dpu_rm_get_topology_name(struct msm_display_topology topology)
> > > -{
> > > -	int i;
> > > -
> > > -	for (i = 0; i < DPU_RM_TOPOLOGY_MAX; i++)
> > > -		if (RM_IS_TOPOLOGY_MATCH(g_top_table[i], topology))
> > > -			return g_top_table[i].top_name;
> > > -
> > > -	return DPU_RM_TOPOLOGY_NONE;
> > > -}
> > > -
> > >  void dpu_rm_init_hw_iter(
> > >  		struct dpu_rm_hw_iter *iter,
> > >  		uint32_t enc_id,
> > > @@ -760,7 +745,6 @@ static int _dpu_rm_make_next_rsvp(
> > >  	/* Create reservation info, tag reserved blocks with it as we go
> > */
> > >  	rsvp->seq = ++rm->rsvp_next_seq;
> > >  	rsvp->enc_id = enc->base.id;
> > > -	rsvp->topology = reqs->topology->top_name;
> > >  	list_add_tail(&rsvp->list, &rm->rsvps);
> > > 
> > >  	ret = _dpu_rm_reserve_lms(rm, rsvp, reqs);
> > > @@ -807,7 +791,7 @@ static int _dpu_rm_populate_requirements(
> > > 
> > >  	dpu_encoder_get_hw_resources(enc, &reqs->hw_res, conn_state);
> > > 
> > > -	for (i = 0; i < DPU_RM_TOPOLOGY_MAX; i++) {
> > > +	for (i = 0; i < ARRAY_SIZE(g_top_table); i++) {
> > >  		if (RM_IS_TOPOLOGY_MATCH(g_top_table[i],
> > >  					req_topology)) {
> > >  			reqs->topology = &g_top_table[i];
> > 
> > Since you can get rid of g_top_table, you can get rid of reqs->topology
> > too.
> > 
> DPU RM is using reqs->topology (ie. struct dpu_rm_topology_def) to represent
> the hw_block requirements for a display. Removing the structure
> might require changes in rest of RM alloc functions.
> 
> If you can hold off on this, I am planning to address your comment in the
> RM refactor series.

I'd rather it be introduced when it's used. That way it can evalutated on its
own merits when we have the full picture. There's a bunch of unused or
duplicated code surrounding the RM, and I think it'd be best to clean it up
while we all have full context in our heads.

Sean

> 
> Jeykumar S.
> 
> > > @@ -831,9 +815,8 @@ static int _dpu_rm_populate_requirements(
> > > 
> > >  	DRM_DEBUG_KMS("top_ctrl: 0x%llX num_h_tiles: %d\n",
> > reqs->top_ctrl,
> > >  		      reqs->hw_res.display_num_of_h_tiles);
> > > -	DRM_DEBUG_KMS("num_lm: %d num_ctl: %d topology: %d split_display:
> > %d\n",
> > > +	DRM_DEBUG_KMS("num_lm: %d num_ctl: %d split_display: %d\n",
> > >  		      reqs->topology->num_lm, reqs->topology->num_ctl,
> > > -		      reqs->topology->top_name,
> > >  		      reqs->topology->needs_split_display);
> > > 
> > >  	return 0;
> > > @@ -969,8 +952,7 @@ static int _dpu_rm_commit_rsvp(
> > >  	}
> > > 
> > >  	if (!ret)
> > > -		DRM_DEBUG_KMS("rsrv enc %d topology %d\n", rsvp->enc_id,
> > > -			      rsvp->topology);
> > > +		DRM_DEBUG_KMS("rsrv enc %d\n", rsvp->enc_id);
> > 
> > This debug message doesn't provide any value any longer.
> > 
> > > 
> > >  	return ret;
> > >  }
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> > > index ffd1841..6fd9e7b 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> > > @@ -21,21 +21,6 @@
> > >  #include "dpu_hw_top.h"
> > > 
> > >  /**
> > > - * enum dpu_rm_topology_name - HW resource use case in use by
> > > connector
> > > - * @DPU_RM_TOPOLOGY_NONE:                 No topology in use
> > > currently
> > > - * @DPU_RM_TOPOLOGY_SINGLEPIPE:           1 LM, 1 PP, 1 INTF/WB
> > > - * @DPU_RM_TOPOLOGY_DUALPIPE:             2 LM, 2 PP, 2 INTF/WB
> > > - * @DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE:     2 LM, 2 PP, 3DMux, 1
> > > INTF/WB
> > > - */
> > > -enum dpu_rm_topology_name {
> > > -	DPU_RM_TOPOLOGY_NONE = 0,
> > > -	DPU_RM_TOPOLOGY_SINGLEPIPE,
> > > -	DPU_RM_TOPOLOGY_DUALPIPE,
> > > -	DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,
> > > -	DPU_RM_TOPOLOGY_MAX,
> > > -};
> > > -
> > > -/**
> > >   * enum dpu_rm_topology_control - HW resource use case in use by
> > connector
> > >   * @DPU_RM_TOPCTL_RESERVE_LOCK: If set, in AtomicTest phase, after a
> > successful
> > >   *                              test, reserve the resources for this
> > display.
> > > @@ -187,13 +172,4 @@ void dpu_rm_init_hw_iter(
> > >   */
> > >  int dpu_rm_check_property_topctl(uint64_t val);
> > > 
> > > -/**
> > > - * dpu_rm_get_topology_name - returns the name of the the given
> > topology
> > > - *                            definition
> > > - * @topology: topology definition
> > > - * @Return: name of the topology
> > > - */
> > > -enum dpu_rm_topology_name
> > > -dpu_rm_get_topology_name(struct msm_display_topology topology);
> > > -
> > >  #endif /* __DPU_RM_H__ */
> > > --
> > > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
> > Forum,
> > > a Linux Foundation Collaborative Project
> > > 
> 
> -- 
> Jeykumar S

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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