From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90F4AC433F5 for ; Fri, 31 Aug 2018 21:54:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3FD0720658 for ; Fri, 31 Aug 2018 21:54:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3FD0720658 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727480AbeIACD0 (ORCPT ); Fri, 31 Aug 2018 22:03:26 -0400 Received: from mga17.intel.com ([192.55.52.151]:36530 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727232AbeIACDZ (ORCPT ); Fri, 31 Aug 2018 22:03:25 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Aug 2018 14:53:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,313,1531810800"; d="scan'208";a="81989050" Received: from 2b52.sc.intel.com ([143.183.136.52]) by fmsmga002.fm.intel.com with ESMTP; 31 Aug 2018 14:53:57 -0700 Message-ID: <1535752180.31230.4.camel@intel.com> Subject: Re: [RFC PATCH v3 19/24] x86/cet/shstk: Introduce WRUSS instruction From: Yu-cheng Yu To: Andy Lutomirski , Jann Horn Cc: the arch/x86 maintainers , "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , kernel list , linux-doc@vger.kernel.org, Linux-MM , linux-arch , Linux API , Arnd Bergmann , Balbir Singh , Cyrill Gorcunov , Dave Hansen , Florian Weimer , "H. J. Lu" , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , "Ravi V. Shankar" , "Shanbhogue, Vedvyas" Date: Fri, 31 Aug 2018 14:49:40 -0700 In-Reply-To: <1535646146.26689.11.camel@intel.com> References: <20180830143904.3168-1-yu-cheng.yu@intel.com> <20180830143904.3168-20-yu-cheng.yu@intel.com> <1535646146.26689.11.camel@intel.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.18.5.2-0ubuntu3.2 Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2018-08-30 at 09:22 -0700, Yu-cheng Yu wrote: > On Thu, 2018-08-30 at 08:55 -0700, Andy Lutomirski wrote: > > > > On Thu, Aug 30, 2018 at 8:39 AM, Jann Horn > > wrote: > > > > > > > > > On Thu, Aug 30, 2018 at 4:44 PM Yu-cheng Yu > > om > > > > > > > > wrote: > > > > > > > > > > > > WRUSS is a new kernel-mode instruction but writes directly > > > > to user shadow stack memory.  This is used to construct > > > > a return address on the shadow stack for the signal > > > > handler. > > > > > > > > This instruction can fault if the user shadow stack is > > > > invalid shadow stack memory.  In that case, the kernel does > > > > fixup. > > > > > > > > Signed-off-by: Yu-cheng Yu > > > [...] > > > > > > > > > > > > +static inline int write_user_shstk_64(unsigned long addr, > > > > unsigned long val) > > > > +{ > > > > +       int err = 0; > > > > + > > > > +       asm volatile("1: wrussq %1, (%0)\n" > > > > +                    "2:\n" > > > > +                    _ASM_EXTABLE_HANDLE(1b, 2b, > > > > ex_handler_wruss) > > > > +                    : > > > > +                    : "r" (addr), "r" (val)); > > > > + > > > > +       return err; > > > > +} > > > What's up with "err"? You set it to zero, and then you return > > > it, > > > but > > > nothing can ever set it to non-zero, right? > > > > > > > > > > > > > > > +__visible bool ex_handler_wruss(const struct > > > > exception_table_entry *fixup, > > > > +                               struct pt_regs *regs, int > > > > trapnr) > > > > +{ > > > > +       regs->ip = ex_fixup_addr(fixup); > > > > +       regs->ax = -1; > > > > +       return true; > > > > +} > > > And here you just write into regs->ax, but your "asm volatile" > > > doesn't > > > reserve that register. This looks wrong to me. > > > > > > I think you probably want to add something like an explicit > > > `"+&a"(err)` output to the asm statements. > > We require asm goto support these days.  How about using > > that?  You > > won't even need a special exception handler. Maybe something like this?  It looks simple now. static inline int write_user_shstk_64(unsigned long addr, unsigned long val) { asm_volatile_goto("wrussq %1, (%0)\n"      "jmp %l[ok]\n"      ".section .fixup,\"ax\"n"      "jmp %l[fail]\n"      ".previous\n"      :: "r" (addr), "r" (val)      :: ok, fail); ok: return 0; fail: return -1; } From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yu-cheng Yu Subject: Re: [RFC PATCH v3 19/24] x86/cet/shstk: Introduce WRUSS instruction Date: Fri, 31 Aug 2018 14:49:40 -0700 Message-ID: <1535752180.31230.4.camel@intel.com> References: <20180830143904.3168-1-yu-cheng.yu@intel.com> <20180830143904.3168-20-yu-cheng.yu@intel.com> <1535646146.26689.11.camel@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <1535646146.26689.11.camel@intel.com> Sender: linux-kernel-owner@vger.kernel.org To: Andy Lutomirski , Jann Horn Cc: the arch/x86 maintainers , "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , kernel list , linux-doc@vger.kernel.org, Linux-MM , linux-arch , Linux API , Arnd Bergmann , Balbir Singh , Cyrill Gorcunov , Dave Hansen , Florian Weimer , "H. J. Lu" , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek List-Id: linux-api@vger.kernel.org On Thu, 2018-08-30 at 09:22 -0700, Yu-cheng Yu wrote: > On Thu, 2018-08-30 at 08:55 -0700, Andy Lutomirski wrote: > > > > On Thu, Aug 30, 2018 at 8:39 AM, Jann Horn > > wrote: > > > > > > > > > On Thu, Aug 30, 2018 at 4:44 PM Yu-cheng Yu > > om > > > > > > > > wrote: > > > > > > > > > > > > WRUSS is a new kernel-mode instruction but writes directly > > > > to user shadow stack memory.  This is used to construct > > > > a return address on the shadow stack for the signal > > > > handler. > > > > > > > > This instruction can fault if the user shadow stack is > > > > invalid shadow stack memory.  In that case, the kernel does > > > > fixup. > > > > > > > > Signed-off-by: Yu-cheng Yu > > > [...] > > > > > > > > > > > > +static inline int write_user_shstk_64(unsigned long addr, > > > > unsigned long val) > > > > +{ > > > > +       int err = 0; > > > > + > > > > +       asm volatile("1: wrussq %1, (%0)\n" > > > > +                    "2:\n" > > > > +                    _ASM_EXTABLE_HANDLE(1b, 2b, > > > > ex_handler_wruss) > > > > +                    : > > > > +                    : "r" (addr), "r" (val)); > > > > + > > > > +       return err; > > > > +} > > > What's up with "err"? You set it to zero, and then you return > > > it, > > > but > > > nothing can ever set it to non-zero, right? > > > > > > > > > > > > > > > +__visible bool ex_handler_wruss(const struct > > > > exception_table_entry *fixup, > > > > +                               struct pt_regs *regs, int > > > > trapnr) > > > > +{ > > > > +       regs->ip = ex_fixup_addr(fixup); > > > > +       regs->ax = -1; > > > > +       return true; > > > > +} > > > And here you just write into regs->ax, but your "asm volatile" > > > doesn't > > > reserve that register. This looks wrong to me. > > > > > > I think you probably want to add something like an explicit > > > `"+&a"(err)` output to the asm statements. > > We require asm goto support these days.  How about using > > that?  You > > won't even need a special exception handler. Maybe something like this?  It looks simple now. static inline int write_user_shstk_64(unsigned long addr, unsigned long val) { asm_volatile_goto("wrussq %1, (%0)\n"      "jmp %l[ok]\n"      ".section .fixup,\"ax\"n"      "jmp %l[fail]\n"      ".previous\n"      :: "r" (addr), "r" (val)      :: ok, fail); ok: return 0; fail: return -1; } From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-f197.google.com (mail-pf1-f197.google.com [209.85.210.197]) by kanga.kvack.org (Postfix) with ESMTP id 9D1016B5927 for ; Fri, 31 Aug 2018 17:54:01 -0400 (EDT) Received: by mail-pf1-f197.google.com with SMTP id h65-v6so7457563pfk.18 for ; Fri, 31 Aug 2018 14:54:01 -0700 (PDT) Received: from mga03.intel.com (mga03.intel.com. [134.134.136.65]) by mx.google.com with ESMTPS id n6-v6si8364825plk.255.2018.08.31.14.54.00 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 31 Aug 2018 14:54:00 -0700 (PDT) Message-ID: <1535752180.31230.4.camel@intel.com> Subject: Re: [RFC PATCH v3 19/24] x86/cet/shstk: Introduce WRUSS instruction From: Yu-cheng Yu Date: Fri, 31 Aug 2018 14:49:40 -0700 In-Reply-To: <1535646146.26689.11.camel@intel.com> References: <20180830143904.3168-1-yu-cheng.yu@intel.com> <20180830143904.3168-20-yu-cheng.yu@intel.com> <1535646146.26689.11.camel@intel.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: owner-linux-mm@kvack.org List-ID: To: Andy Lutomirski , Jann Horn Cc: the arch/x86 maintainers , "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , kernel list , linux-doc@vger.kernel.org, Linux-MM , linux-arch , Linux API , Arnd Bergmann , Balbir Singh , Cyrill Gorcunov , Dave Hansen , Florian Weimer , "H. J. Lu" , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , "Ravi V. Shankar" , "Shanbhogue, Vedvyas" On Thu, 2018-08-30 at 09:22 -0700, Yu-cheng Yu wrote: > On Thu, 2018-08-30 at 08:55 -0700, Andy Lutomirski wrote: > > > > On Thu, Aug 30, 2018 at 8:39 AM, Jann Horn > > wrote: > > > > > > > > > On Thu, Aug 30, 2018 at 4:44 PM Yu-cheng Yu > > om > > > > > > > > wrote: > > > > > > > > > > > > WRUSS is a new kernel-mode instruction but writes directly > > > > to user shadow stack memory.A A This is used to construct > > > > a return address on the shadow stack for the signal > > > > handler. > > > > > > > > This instruction can fault if the user shadow stack is > > > > invalid shadow stack memory.A A In that case, the kernel does > > > > fixup. > > > > > > > > Signed-off-by: Yu-cheng Yu > > > [...] > > > > > > > > > > > > +static inline int write_user_shstk_64(unsigned long addr, > > > > unsigned long val) > > > > +{ > > > > +A A A A A A A int err = 0; > > > > + > > > > +A A A A A A A asm volatile("1: wrussq %1, (%0)\n" > > > > +A A A A A A A A A A A A A A A A A A A A "2:\n" > > > > +A A A A A A A A A A A A A A A A A A A A _ASM_EXTABLE_HANDLE(1b, 2b, > > > > ex_handler_wruss) > > > > +A A A A A A A A A A A A A A A A A A A A : > > > > +A A A A A A A A A A A A A A A A A A A A : "r" (addr), "r" (val)); > > > > + > > > > +A A A A A A A return err; > > > > +} > > > What's up with "err"? You set it to zero, and then you return > > > it, > > > but > > > nothing can ever set it to non-zero, right? > > > > > > > > > > > > > > > +__visible bool ex_handler_wruss(const struct > > > > exception_table_entry *fixup, > > > > +A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A struct pt_regs *regs, int > > > > trapnr) > > > > +{ > > > > +A A A A A A A regs->ip = ex_fixup_addr(fixup); > > > > +A A A A A A A regs->ax = -1; > > > > +A A A A A A A return true; > > > > +} > > > And here you just write into regs->ax, but your "asm volatile" > > > doesn't > > > reserve that register. This looks wrong to me. > > > > > > I think you probably want to add something like an explicit > > > `"+&a"(err)` output to the asm statements. > > We require asm goto support these days.A A How about using > > that?A A You > > won't even need a special exception handler. Maybe something like this? A It looks simple now. static inline int write_user_shstk_64(unsigned long addr, unsigned long val) { asm_volatile_goto("wrussq %1, (%0)\n" A A A A A "jmp %l[ok]\n" A A A A A ".section .fixup,\"ax\"n" A A A A A "jmp %l[fail]\n" A A A A A ".previous\n" A A A A A :: "r" (addr), "r" (val) A A A A A :: ok, fail); ok: return 0; fail: return -1; }