From mboxrd@z Thu Jan 1 00:00:00 1970 From: Anoob Joseph Subject: [PATCH v2 06/33] crypto/octeontx: add hardware init routine Date: Tue, 4 Sep 2018 09:28:53 +0530 Message-ID: <1536033560-21541-7-git-send-email-ajoseph@caviumnetworks.com> References: <1528476325-15585-1-git-send-email-anoob.joseph@caviumnetworks.com> <1536033560-21541-1-git-send-email-ajoseph@caviumnetworks.com> Mime-Version: 1.0 Content-Type: text/plain Cc: Anoob Joseph , Jerin Jacob , Narayana Prasad , dev@dpdk.org, Ankur Dwivedi , Murthy NSSR , Nithin Dabilpuram , Ragothaman Jayaraman , Srisivasubramanian S , Tejasree Kondoj To: Akhil Goyal , Pablo de Lara , Thomas Monjalon Return-path: Received: from NAM02-CY1-obe.outbound.protection.outlook.com (mail-cys01nam02on0060.outbound.protection.outlook.com [104.47.37.60]) by dpdk.org (Postfix) with ESMTP id 4CC442BF3 for ; Tue, 4 Sep 2018 06:03:07 +0200 (CEST) In-Reply-To: <1536033560-21541-1-git-send-email-ajoseph@caviumnetworks.com> List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Anoob Joseph Adding hardware init routine for OcteonTX crypto device. A place holder is added for misc polling routine. That will be added in the further patches. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Murthy NSSR Signed-off-by: Nithin Dabilpuram Signed-off-by: Ragothaman Jayaraman Signed-off-by: Srisivasubramanian S Signed-off-by: Tejasree Kondoj --- drivers/crypto/octeontx/Makefile | 1 + drivers/crypto/octeontx/meson.build | 1 + drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 53 +++++++++++++ drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 92 +++++++++++++++++++++++ drivers/crypto/octeontx/otx_cryptodev_ops.c | 89 +++++++++++++++++++++- 5 files changed, 235 insertions(+), 1 deletion(-) create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.c diff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile index 12fec75..4582540 100644 --- a/drivers/crypto/octeontx/Makefile +++ b/drivers/crypto/octeontx/Makefile @@ -24,6 +24,7 @@ CFLAGS += -I$(RTE_SDK)/drivers/common/cpt # PMD code SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_hw_access.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_ops.c # export include files diff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build index 6564090..eca1cf1 100644 --- a/drivers/crypto/octeontx/meson.build +++ b/drivers/crypto/octeontx/meson.build @@ -8,6 +8,7 @@ deps += ['bus_pci'] name = 'octeontx_crypto' sources = files('otx_cryptodev.c', + 'otx_cryptodev_hw_access.c', 'otx_cryptodev_ops.c') cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX' diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c new file mode 100644 index 0000000..211b6ee --- /dev/null +++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018 Cavium, Inc + */ +#include + +#include + +#include "otx_cryptodev_hw_access.h" + +#include "cpt_pmd_logs.h" + +static int +otx_cpt_vf_init(struct cpt_vf *cptvf) +{ + int ret = 0; + + /* Mark as VF driver */ + cptvf->flags |= CPT_FLAG_VF_DRIVER; + + CPT_LOG_DP_DEBUG("%s: %s done", cptvf->dev_name, __func__); + + return ret; +} + +void +otx_cpt_poll_misc(struct cpt_vf *cptvf) +{ + RTE_SET_USED(cptvf); +} + +int +otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name) +{ + memset(cptvf, 0, sizeof(struct cpt_vf)); + + /* Bar0 base address */ + cptvf->reg_base = reg_base; + strncpy(cptvf->dev_name, name, 32); + + cptvf->nr_queues = 1; + cptvf->max_queues = 1; + cptvf->pdev = pdev; + + /* To clear if there are any pending mbox msgs */ + otx_cpt_poll_misc(cptvf); + + if (otx_cpt_vf_init(cptvf)) { + CPT_LOG_ERR("Failed to initialize CPT VF device"); + return -1; + } + + return 0; +} diff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h index 288ee41..40db69c 100644 --- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h +++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h @@ -5,6 +5,90 @@ #ifndef _OTX_CRYPTODEV_HW_ACCESS_H_ #define _OTX_CRYPTODEV_HW_ACCESS_H_ +#include + +#include + +#include "cpt_common.h" + +/* Flags to indicate the features supported */ +#define CPT_FLAG_VF_DRIVER (uint16_t)(1 << 3) + +#define CPT_INTR_POLL_INTERVAL_MS (50) + +/* Default command queue length */ +#define DEFAULT_CMD_QCHUNKS 2 + +struct command_chunk { + uint8_t *head; + /**< 128-byte aligned real_vaddr */ + phys_addr_t dma_addr; + /**< 128-byte aligned real_dma_addr */ +}; + +/** + * Command queue structure + */ +struct command_queue { + uint32_t idx; + /**< Command queue host write idx */ + uint32_t cchunk; + uint8_t *qhead; + /**< Command queue head; instructions are inserted here */ + struct command_chunk chead[DEFAULT_CMD_QCHUNKS]; + /**< Command chunk list head */ +}; + +/** + * CPT VF device structure + */ +struct cpt_vf { + struct cpt_instance instance; + + uint8_t *reg_base; + /**< Register start address */ + struct command_queue cqueue; + /**< Command queue information */ + struct pending_queue pqueue; + /**< Pending queue information */ + struct cptvf_meta_info meta_info; + /**< Meta information per vf */ + + /* Below fields are accessed only in control path */ + + void *pdev; + /**< Env specific pdev representing the pci dev */ + uint32_t qlen; + /**< Qsize * CPT_INST_SIZE + alignment size(CPT_INST_SIZE + + * next chunk pointer size (8) + */ + uint32_t qsize; + /**< Calculated queue size */ + uint32_t nr_queues; + uint32_t max_queues; + + uint32_t chip_id; + /**< CPT device ID */ + uint16_t flags; + /**< Flags to hold device status bits */ + uint8_t vfid; + /**< Device index (0...CPT_MAX_VQ_NUM)*/ + uint8_t vftype; + /**< VF type of cpt_vf_type_t (SE_TYPE(2) or AE_TYPE(1) */ + uint8_t vfgrp; + /**< VF group (0 - 8) */ + uint8_t node; + /**< Operating node: Bits (46:44) in BAR0 address */ + + /* VF-PF mailbox communication */ + + bool pf_acked; + bool pf_nacked; + + char dev_name[32]; + /**< Device name */ +} __rte_cache_aligned; + /* * CPT Registers map for 81xx */ @@ -44,4 +128,12 @@ ((a) & 0x1) + 0x100000ll * (b) + \ 8ll * ((c) & 0x1)) +/* VF HAL functions */ + +void +otx_cpt_poll_misc(struct cpt_vf *cptvf); + +int +otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name); + #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */ diff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c index 1b5f108..d25f9c1 100644 --- a/drivers/crypto/octeontx/otx_cryptodev_ops.c +++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c @@ -2,14 +2,101 @@ * Copyright(c) 2018 Cavium, Inc */ +#include +#include #include +#include + +#include "cpt_pmd_logs.h" #include "otx_cryptodev.h" +#include "otx_cryptodev_hw_access.h" #include "otx_cryptodev_ops.h" +/* Alarm routines */ + +static void +otx_cpt_alarm_cb(void *arg) +{ + struct cpt_vf *cptvf = arg; + otx_cpt_poll_misc(cptvf); + rte_eal_alarm_set(CPT_INTR_POLL_INTERVAL_MS * 1000, + otx_cpt_alarm_cb, cptvf); +} + +static int +otx_cpt_periodic_alarm_start(void *arg) +{ + return rte_eal_alarm_set(CPT_INTR_POLL_INTERVAL_MS * 1000, + otx_cpt_alarm_cb, arg); +} + int otx_cpt_dev_create(struct rte_cryptodev *c_dev) { - RTE_SET_USED(c_dev); + struct rte_pci_device *pdev = RTE_DEV_TO_PCI(c_dev->device); + struct cpt_vf *cptvf = NULL; + void *reg_base; + char dev_name[32]; + int ret; + + if (pdev->mem_resource[0].phys_addr == 0ULL) + return -EIO; + + /* for secondary processes, we don't initialise any further as primary + * has already done this work. + */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + cptvf = rte_zmalloc_socket("otx_cryptodev_private_mem", + sizeof(struct cpt_vf), RTE_CACHE_LINE_SIZE, + rte_socket_id()); + + if (cptvf == NULL) { + CPT_LOG_ERR("Cannot allocate memory for device private data"); + return -ENOMEM; + } + + snprintf(dev_name, 32, "%02x:%02x.%x", + pdev->addr.bus, pdev->addr.devid, pdev->addr.function); + + reg_base = pdev->mem_resource[0].addr; + if (!reg_base) { + CPT_LOG_ERR("Failed to map BAR0 of %s", dev_name); + ret = -ENODEV; + goto fail; + } + + ret = otx_cpt_hw_init(cptvf, pdev, reg_base, dev_name); + if (ret) { + CPT_LOG_ERR("Failed to init cptvf %s", dev_name); + ret = -EIO; + goto fail; + } + + /* Start off timer for mailbox interrupts */ + otx_cpt_periodic_alarm_start(cptvf); + + c_dev->dev_ops = NULL; + + c_dev->enqueue_burst = NULL; + c_dev->dequeue_burst = NULL; + + c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | + RTE_CRYPTODEV_FF_HW_ACCELERATED | + RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING; + + /* Save dev private data */ + c_dev->data->dev_private = cptvf; + return 0; + +fail: + if (cptvf) { + /* Free private data allocated */ + rte_free(cptvf); + } + + return ret; } -- 2.7.4