From mboxrd@z Thu Jan 1 00:00:00 1970 From: Venkata Narendra Kumar Gutta Subject: [PATCH v4 4/4] dt-bindings: msm: Update documentation of qcom,llcc Date: Tue, 4 Sep 2018 16:22:25 -0700 Message-ID: <1536103345-1919-5-git-send-email-vnkgutta@codeaurora.org> References: <1536103345-1919-1-git-send-email-vnkgutta@codeaurora.org> Return-path: In-Reply-To: <1536103345-1919-1-git-send-email-vnkgutta@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org To: Borislav Petkov , evgreen@chromium.org, robh@kernel.org, mchehab@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Gross , David Brown , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, tsoni@codeaurora.org, ckadabi@codeaurora.org, rishabhb@codeaurora.org, swboyd@chromium.org, bjorn.andersson@linaro.org Cc: Venkata Narendra Kumar Gutta List-Id: linux-arm-msm@vger.kernel.org Add reg-names and interrupts for LLCC documentation and the usage examples. llcc broadcast base is added in addition to llcc base, which is used for llcc broadcast writes. Signed-off-by: Venkata Narendra Kumar Gutta Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/msm/qcom,llcc.txt | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt index 5e85749..2e007dc 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt @@ -16,11 +16,26 @@ Properties: - reg: Usage: required Value Type: - Definition: Start address and the the size of the register region. + Definition: The first element specifies the llcc base start address and + the size of the register region. The second element specifies + the llcc broadcast base address and size of the register region. + +- reg-names: + Usage: required + Value Type: + Definition: Register region names. Must be "llcc_base", "llcc_bcast_base". + +- interrupts: + Usage: required + Definition: The interrupt is associated with the llcc edac device. + It's used for llcc cache single and double bit error detection + and reporting. Example: cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; - reg = <0x1100000 0x250000>; + reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; + reg-names = "llcc_base", "llcc_bcast_base"; + interrupts = ; }; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v4,4/4] dt-bindings: msm: Update documentation of qcom,llcc From: Venkata Narendra Kumar Gutta Message-Id: <1536103345-1919-5-git-send-email-vnkgutta@codeaurora.org> Date: Tue, 4 Sep 2018 16:22:25 -0700 To: Borislav Petkov , evgreen@chromium.org, robh@kernel.org, mchehab@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Gross , David Brown , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, tsoni@codeaurora.org, ckadabi@codeaurora.org, rishabhb@codeaurora.org, swboyd@chromium.org, bjorn.andersson@linaro.org Cc: Venkata Narendra Kumar Gutta List-ID: QWRkIHJlZy1uYW1lcyBhbmQgaW50ZXJydXB0cyBmb3IgTExDQyBkb2N1bWVudGF0aW9uIGFuZCB0 aGUgdXNhZ2UKZXhhbXBsZXMuIGxsY2MgYnJvYWRjYXN0IGJhc2UgaXMgYWRkZWQgaW4gYWRkaXRp b24gdG8gbGxjYyBiYXNlLAp3aGljaCBpcyB1c2VkIGZvciBsbGNjIGJyb2FkY2FzdCB3cml0ZXMu CgpTaWduZWQtb2ZmLWJ5OiBWZW5rYXRhIE5hcmVuZHJhIEt1bWFyIEd1dHRhIDx2bmtndXR0YUBj b2RlYXVyb3JhLm9yZz4KUmV2aWV3ZWQtYnk6IFJvYiBIZXJyaW5nIDxyb2JoQGtlcm5lbC5vcmc+ Ci0tLQogLi4uL2RldmljZXRyZWUvYmluZGluZ3MvYXJtL21zbS9xY29tLGxsY2MudHh0ICAgICAg ICAgfCAxOSArKysrKysrKysrKysrKysrKy0tCiAxIGZpbGUgY2hhbmdlZCwgMTcgaW5zZXJ0aW9u cygrKSwgMiBkZWxldGlvbnMoLSkKCmRpZmYgLS1naXQgYS9Eb2N1bWVudGF0aW9uL2RldmljZXRy ZWUvYmluZGluZ3MvYXJtL21zbS9xY29tLGxsY2MudHh0IGIvRG9jdW1lbnRhdGlvbi9kZXZpY2V0 cmVlL2JpbmRpbmdzL2FybS9tc20vcWNvbSxsbGNjLnR4dAppbmRleCA1ZTg1NzQ5Li4yZTAwN2Rj IDEwMDY0NAotLS0gYS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvYXJtL21zbS9x Y29tLGxsY2MudHh0CisrKyBiL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9hcm0v bXNtL3Fjb20sbGxjYy50eHQKQEAgLTE2LDExICsxNiwyNiBAQCBQcm9wZXJ0aWVzOgogLSByZWc6 CiAJVXNhZ2U6IHJlcXVpcmVkCiAJVmFsdWUgVHlwZTogPHByb3AtZW5jb2RlZC1hcnJheT4KLQlE ZWZpbml0aW9uOiBTdGFydCBhZGRyZXNzIGFuZCB0aGUgdGhlIHNpemUgb2YgdGhlIHJlZ2lzdGVy IHJlZ2lvbi4KKwlEZWZpbml0aW9uOiBUaGUgZmlyc3QgZWxlbWVudCBzcGVjaWZpZXMgdGhlIGxs Y2MgYmFzZSBzdGFydCBhZGRyZXNzIGFuZAorCQkgICAgdGhlIHNpemUgb2YgdGhlIHJlZ2lzdGVy IHJlZ2lvbi4gVGhlIHNlY29uZCBlbGVtZW50IHNwZWNpZmllcworCQkgICAgdGhlIGxsY2MgYnJv YWRjYXN0IGJhc2UgYWRkcmVzcyBhbmQgc2l6ZSBvZiB0aGUgcmVnaXN0ZXIgcmVnaW9uLgorCist IHJlZy1uYW1lczoKKyAgICAgICAgVXNhZ2U6IHJlcXVpcmVkCisgICAgICAgIFZhbHVlIFR5cGU6 IDxzdHJpbmdsaXN0PgorICAgICAgICBEZWZpbml0aW9uOiBSZWdpc3RlciByZWdpb24gbmFtZXMu IE11c3QgYmUgImxsY2NfYmFzZSIsICJsbGNjX2JjYXN0X2Jhc2UiLgorCistIGludGVycnVwdHM6 CisJVXNhZ2U6IHJlcXVpcmVkCisJRGVmaW5pdGlvbjogVGhlIGludGVycnVwdCBpcyBhc3NvY2lh dGVkIHdpdGggdGhlIGxsY2MgZWRhYyBkZXZpY2UuCisJCQlJdCdzIHVzZWQgZm9yIGxsY2MgY2Fj aGUgc2luZ2xlIGFuZCBkb3VibGUgYml0IGVycm9yIGRldGVjdGlvbgorCQkJYW5kIHJlcG9ydGlu Zy4KIAogRXhhbXBsZToKIAogCWNhY2hlLWNvbnRyb2xsZXJAMTEwMDAwMCB7CiAJCWNvbXBhdGli bGUgPSAicWNvbSxzZG04NDUtbGxjYyI7Ci0JCXJlZyA9IDwweDExMDAwMDAgMHgyNTAwMDA+Owor CQlyZWcgPSA8MHgxMTAwMDAwIDB4MjAwMDAwPiwgPDB4MTMwMDAwMCAweDUwMDAwPiA7CisJCXJl Zy1uYW1lcyA9ICJsbGNjX2Jhc2UiLCAibGxjY19iY2FzdF9iYXNlIjsKKwkJaW50ZXJydXB0cyA9 IDxHSUNfU1BJIDU4MiBJUlFfVFlQRV9MRVZFTF9ISUdIPjsKIAl9Owo=