From mboxrd@z Thu Jan 1 00:00:00 1970 From: Phil@dpdk.org, "Yang Cc: nd@arm.com, jerin.jacob@caviumnetworks.com, kkokkilagadda@caviumnetworks.com, Honnappa.Nagarahalli@arm.com, Gavin.Hu@arm.com, Phil Yang To: dev@dpdk.org Return-path: Received: from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by dpdk.org (Postfix) with ESMTP id 0886D255 for ; Wed, 19 Sep 2018 15:30:56 +0200 (CEST) List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Phil Yang Keep only single config option RTE_USE_C11_MEM_MODEL for C11 memory model, so all modules can leverage C11 atomic extension by enable this option. Fixes: 39368eb ("ring: introduce C11 memory model barrier option") Signed-off-by: Phil Yang Reviewed-by: Honnappa Nagarahalli Reviewed-by: Gavin Hu --- config/arm/meson.build | 2 +- config/common_armv8a_linuxapp | 2 +- config/common_base | 2 +- config/defconfig_arm64-thunderx-linuxapp-gcc | 2 +- lib/librte_ring/rte_ring.h | 4 ++-- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 94cca49..4b23b39 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -53,7 +53,7 @@ flags_cavium = [ ['RTE_MAX_NUMA_NODES', 2], ['RTE_MAX_LCORE', 96], ['RTE_MAX_VFIO_GROUPS', 128], - ['RTE_RING_USE_C11_MEM_MODEL', false]] + ['RTE_USE_C11_MEM_MODEL', false]] flags_dpaa = [ ['RTE_MACHINE', '"dpaa"'], ['RTE_CACHE_LINE_SIZE', 64], diff --git a/config/common_armv8a_linuxapp b/config/common_armv8a_linuxapp index 111c005..54e6987 100644 --- a/config/common_armv8a_linuxapp +++ b/config/common_armv8a_linuxapp @@ -29,7 +29,7 @@ CONFIG_RTE_ARCH_ARM64_MEMCPY=n #CONFIG_RTE_ARM64_MEMCPY_ALIGN_MASK=0xF #CONFIG_RTE_ARM64_MEMCPY_STRICT_ALIGN=n -CONFIG_RTE_RING_USE_C11_MEM_MODEL=y +CONFIG_RTE_USE_C11_MEM_MODEL=y CONFIG_RTE_LIBRTE_FM10K_PMD=n CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n diff --git a/config/common_base b/config/common_base index 155c7d4..ccd2670 100644 --- a/config/common_base +++ b/config/common_base @@ -661,7 +661,7 @@ CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=y # Compile librte_ring # CONFIG_RTE_LIBRTE_RING=y -CONFIG_RTE_RING_USE_C11_MEM_MODEL=n +CONFIG_RTE_USE_C11_MEM_MODEL=n # # Compile librte_mempool diff --git a/config/defconfig_arm64-thunderx-linuxapp-gcc b/config/defconfig_arm64-thunderx-linuxapp-gcc index 2bed66c..f11e758 100644 --- a/config/defconfig_arm64-thunderx-linuxapp-gcc +++ b/config/defconfig_arm64-thunderx-linuxapp-gcc @@ -10,7 +10,7 @@ CONFIG_RTE_CACHE_LINE_SIZE=128 CONFIG_RTE_MAX_NUMA_NODES=2 CONFIG_RTE_MAX_LCORE=96 CONFIG_RTE_MAX_VFIO_GROUPS=128 -CONFIG_RTE_RING_USE_C11_MEM_MODEL=n +CONFIG_RTE_USE_C11_MEM_MODEL=n # # Compile PMD for octeontx sso event device diff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h index 7a731d0..af5444a 100644 --- a/lib/librte_ring/rte_ring.h +++ b/lib/librte_ring/rte_ring.h @@ -303,11 +303,11 @@ void rte_ring_dump(FILE *f, const struct rte_ring *r); * There are 2 choices for the users * 1.use rmb() memory barrier * 2.use one-direcion load_acquire/store_release barrier,defined by - * CONFIG_RTE_RING_USE_C11_MEM_MODEL=y + * CONFIG_RTE_USE_C11_MEM_MODEL=y * It depends on performance test results. * By default, move common functions to rte_ring_generic.h */ -#ifdef RTE_RING_USE_C11_MEM_MODEL +#ifdef RTE_USE_C11_MEM_MODEL #include "rte_ring_c11_mem.h" #else #include "rte_ring_generic.h" -- 2.7.4