All of lore.kernel.org
 help / color / mirror / Atom feed
From: Xiaolin Zhang <xiaolin.zhang@intel.com>
To: intel-gvt-dev@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: zhenyu.z.wang@intel.com, hang.yuan@intel.com,
	joonas.lahtinen@intel.com, fei.jiang@intel.com,
	zhiyuan.lv@intel.com
Subject: [RFC 01/10] drm/i915/gvt: add module parameter enable_pvmmio
Date: Thu, 27 Sep 2018 12:37:46 -0400	[thread overview]
Message-ID: <1538066275-52932-2-git-send-email-xiaolin.zhang@intel.com> (raw)
In-Reply-To: <1538066275-52932-1-git-send-email-xiaolin.zhang@intel.com>

This int type module parameter is used to control the different
level pvmmio feature for MMIO emulation in GVT.

This parameter is default zero, no pvmmio feature enabled.

Its permission type is 0400 which means user could only change its
value through the cmdline, this is to prevent the dynamic modification
during runtime which would break the pvmmio internal logic.

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h    |  3 +++
 drivers/gpu/drm/i915/i915_params.c |  4 ++++
 drivers/gpu/drm/i915/i915_params.h |  3 ++-
 drivers/gpu/drm/i915/i915_pvinfo.h | 16 +++++++++++++++-
 drivers/gpu/drm/i915/i915_vgpu.c   | 12 +++++++++++-
 5 files changed, 35 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8624b4b..174d618 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3871,4 +3871,7 @@ static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
 		return I915_HWS_CSB_WRITE_INDEX;
 }
 
+#define PVMMIO_LEVEL_ENABLE(dev_priv, level)	\
+	(intel_vgpu_active(dev_priv) && i915_modparams.enable_pvmmio & level)
+
 #endif
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 295e981..5ee236ec 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -174,6 +174,10 @@ struct i915_params i915_modparams __read_mostly = {
 i915_param_named(enable_gvt, bool, 0400,
 	"Enable support for Intel GVT-g graphics virtualization host support(default:false)");
 
+i915_param_named(enable_pvmmio, int, 0400,
+	"Enable pv mmio feature, default TRUE. This parameter "
+	"could only set from host, guest value is set through vgt_if");
+
 static __always_inline void _print_param(struct drm_printer *p,
 					 const char *name,
 					 const char *type,
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 6c4d4a2..0f6a38b 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -68,7 +68,8 @@
 	param(bool, nuclear_pageflip, false) \
 	param(bool, enable_dp_mst, true) \
 	param(bool, enable_dpcd_backlight, false) \
-	param(bool, enable_gvt, false)
+	param(bool, enable_gvt, false) \
+	param(int, enable_pvmmio, 0)
 
 #define MEMBER(T, member, ...) T member;
 struct i915_params {
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index eeaa3d5..697e998 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -49,6 +49,8 @@ enum vgt_g2v_type {
 	VGT_G2V_MAX,
 };
 
+#define VGPU_PVMMIO(vgpu) vgpu_vreg_t(vgpu, vgtif_reg(enable_pvmmio))
+
 /*
  * VGT capabilities type
  */
@@ -56,6 +58,17 @@ enum vgt_g2v_type {
 #define VGT_CAPS_HWSP_EMULATION		BIT(3)
 #define VGT_CAPS_HUGE_GTT		BIT(4)
 
+/*
+ * define different levels of PVMMIO optimization
+ */
+enum pvmmio_levels {
+	PVMMIO_ELSP_SUBMIT = 0x1,
+	PVMMIO_PLANE_UPDATE = 0x2,
+	PVMMIO_PLANE_WM_UPDATE = 0x4,
+	PVMMIO_MASTER_IRQ = 0x8,
+	PVMMIO_PPGTT_UPDATE = 0x10,
+};
+
 struct vgt_if {
 	u64 magic;		/* VGT_MAGIC */
 	u16 version_major;
@@ -106,8 +119,9 @@ struct vgt_if {
 
 	u32 execlist_context_descriptor_lo;
 	u32 execlist_context_descriptor_hi;
+	u32 enable_pvmmio;
 
-	u32  rsv7[0x200 - 24];    /* pad to one page */
+	u32  rsv7[0x200 - 25];    /* pad to one page */
 } __packed;
 
 #define vgtif_reg(x) \
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 869cf4a..d22c5ca 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -77,8 +77,18 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 
 	dev_priv->vgpu.caps = __raw_i915_read32(dev_priv, vgtif_reg(vgt_caps));
 
+	/* If guest wants to enable pvmmio, it needs to enable it explicitly
+	 * through vgt_if interface, and then read back the enable state from
+	 * gvt layer.
+	 */
+	__raw_i915_write32(dev_priv, vgtif_reg(enable_pvmmio),
+			i915_modparams.enable_pvmmio);
+	i915_modparams.enable_pvmmio = __raw_i915_read32(dev_priv,
+			vgtif_reg(enable_pvmmio));
+
 	dev_priv->vgpu.active = true;
-	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
+	DRM_INFO("Virtual GPU for Intel GVT-g detected with pvmmio 0x%x\n",
+		i915_modparams.enable_pvmmio);
 }
 
 bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2018-09-27 16:37 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-27 16:37 [RFC 00/10] i915 pvmmio to improve GVTg performance Xiaolin Zhang
2018-09-27  7:20 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2018-09-27  7:24 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-09-27  7:43 ` ✓ Fi.CI.BAT: success " Patchwork
2018-09-27 10:25 ` ✓ Fi.CI.IGT: " Patchwork
2018-09-27 11:07 ` [RFC 00/10] " Joonas Lahtinen
2018-09-28  6:11   ` Zhang, Xiaolin
2018-09-27 16:37 ` Xiaolin Zhang [this message]
2018-09-27  7:16   ` [RFC 01/10] drm/i915/gvt: add module parameter enable_pvmmio Chris Wilson
2018-09-27 11:03   ` Joonas Lahtinen
2018-09-28  6:09     ` Zhang, Xiaolin
2018-10-09  2:26       ` Zhenyu Wang
2018-10-10  6:48         ` Zhang, Xiaolin
2018-09-27 16:37 ` [RFC 02/10] drm/i915/gvt: get ready of memory for pvmmio Xiaolin Zhang
2018-09-27  7:17   ` Chris Wilson
2018-09-28  7:31     ` Zhang, Xiaolin
2018-10-09  2:31   ` Zhenyu Wang
2018-09-27 16:37 ` [RFC 03/10] drm/i915/gvt: context submission pvmmio optimization Xiaolin Zhang
2018-09-27  7:19   ` Chris Wilson
2018-09-28  5:31     ` Zhang, Xiaolin
2018-09-27 11:13   ` Joonas Lahtinen
2018-09-27 16:37 ` [RFC 04/10] drm/i915/gvt: master irq " Xiaolin Zhang
2018-09-27 16:37 ` [RFC 05/10] drm/i915/gvt: ppgtt update " Xiaolin Zhang
2018-09-27 16:37 ` [RFC 06/10] drm/i915/gvt: GVTg handle enable_pvmmio PVINFO register Xiaolin Zhang
2018-09-27 16:37 ` [RFC 07/10] drm/i915/gvt: GVTg read_shared_page implementation Xiaolin Zhang
2018-09-27 16:37 ` [RFC 08/10] drm/i915/gvt: GVTg support context submission pvmmio optimization Xiaolin Zhang
2018-09-27 16:37 ` [RFC 09/10] drm/i915/gvt: GVTg support master irq " Xiaolin Zhang
2018-09-27 16:37 ` [RFC 10/10] drm/i915/gvt: GVTg support ppgtt " Xiaolin Zhang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1538066275-52932-2-git-send-email-xiaolin.zhang@intel.com \
    --to=xiaolin.zhang@intel.com \
    --cc=fei.jiang@intel.com \
    --cc=hang.yuan@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=intel-gvt-dev@lists.freedesktop.org \
    --cc=joonas.lahtinen@intel.com \
    --cc=zhenyu.z.wang@intel.com \
    --cc=zhiyuan.lv@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.