From: Jyoti Yadav <jyoti.r.yadav@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: rodrigo.vivi@intel.com
Subject: [PATCH] [intel-gfx] drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry.
Date: Tue, 2 Oct 2018 00:42:27 -0400 [thread overview]
Message-ID: <1538455347-9984-1-git-send-email-jyoti.r.yadav@intel.com> (raw)
DC5 and DC6 counter register tells about residency of DC5 and DC6.
These registers are same for SKL and ICL.
v2 : Remove csr_version check.
Added generic check regarding DC counters for Gen9 onwards. (Rodrigo)
Signed-off-by: Jyoti Yadav <jyoti.r.yadav@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 7 ++++---
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a5265c2..bcc1e86 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2880,11 +2880,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct intel_csr *csr;
+ int gen;
if (!HAS_CSR(dev_priv))
return -ENODEV;
csr = &dev_priv->csr;
+ gen = INTEL_GEN(dev_priv);
intel_runtime_pm_get(dev_priv);
@@ -2897,13 +2899,12 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
CSR_VERSION_MINOR(csr->version));
- if (IS_KABYLAKE(dev_priv) ||
- (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6))) {
+ if ((!IS_BROXTON(dev_priv)) && gen >= 9 && gen <= 11) {
seq_printf(m, "DC3 -> DC5 count: %d\n",
I915_READ(SKL_CSR_DC3_DC5_COUNT));
seq_printf(m, "DC5 -> DC6 count: %d\n",
I915_READ(SKL_CSR_DC5_DC6_COUNT));
- } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
+ } else if (IS_BROXTON(dev_priv)) {
seq_printf(m, "DC3 -> DC5 count: %d\n",
I915_READ(BXT_CSR_DC3_DC5_COUNT));
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8534f88..573d5f3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6985,6 +6985,7 @@ enum {
/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
#define CSR_MMIO_START_RANGE 0x80000
#define CSR_MMIO_END_RANGE 0x8FFFF
+/* DC3_DC5 count and DC5_DC6 count registers are same for SKL and ICL */
#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
--
1.9.1
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next reply other threads:[~2018-10-02 4:42 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-02 4:42 Jyoti Yadav [this message]
2018-10-02 5:20 ` ✓ Fi.CI.BAT: success for drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry. (rev2) Patchwork
2018-10-02 7:06 ` ✓ Fi.CI.IGT: " Patchwork
2018-10-02 7:20 ` [PATCH] [intel-gfx] drm/i915/csr Added DC5 and DC6 counter register for ICL in debugfs entry Chris Wilson
-- strict thread matches above, loose matches on Subject: below --
2018-10-05 18:08 Jyoti Yadav
2018-10-05 20:04 ` Ville Syrjälä
2018-10-05 20:45 ` Rodrigo Vivi
2018-10-05 4:02 Jyoti Yadav
2018-10-05 17:29 ` Rodrigo Vivi
2018-10-03 4:20 Jyoti Yadav
2018-10-03 5:06 ` Vivi, Rodrigo
2018-10-03 5:57 ` Yadav, Jyoti R
2018-10-03 14:51 ` Rodrigo Vivi
2018-10-03 15:18 ` Ville Syrjälä
2018-09-17 16:49 Jyoti Yadav
2018-09-17 17:02 ` Rodrigo Vivi
2018-09-17 17:48 ` kbuild test robot
2018-09-17 18:15 ` kbuild test robot
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