From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47674) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g8Ruz-0008AD-TR for qemu-devel@nongnu.org; Fri, 05 Oct 2018 11:21:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g8Ruo-0006Dx-L7 for qemu-devel@nongnu.org; Fri, 05 Oct 2018 11:21:21 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:43508 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g8Run-0006D3-93 for qemu-devel@nongnu.org; Fri, 05 Oct 2018 11:21:17 -0400 From: Aleksandar Markovic Date: Fri, 5 Oct 2018 17:19:52 +0200 Message-Id: <1538752793-6875-7-git-send-email-aleksandar.markovic@rt-rk.com> In-Reply-To: <1538752793-6875-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1538752793-6875-1-git-send-email-aleksandar.markovic@rt-rk.com> Subject: [Qemu-devel] [PATCH v2 6/7] target/mips: Add opcodes for nanoMIPS EVA instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net, richard.henderson@linaro.org, amarkovic@wavecomp.com, smarkovic@wavecomp.com, pjovanovic@wavecomp.com, laurent@vivier.eu, riku.voipio@iki.fi From: Dimitrije Nikolic Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE, LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE. Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index d64a1da..b0b2f40 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16499,6 +16499,22 @@ enum { NM_P_SC = 0x0b, }; +/* P.LS.E0 instruction pool */ +enum { + NM_LBE = 0x00, + NM_SBE = 0x01, + NM_LBUE = 0x02, + NM_P_PREFE = 0x03, + NM_LHE = 0x04, + NM_SHE = 0x05, + NM_LHUE = 0x06, + NM_CACHEE = 0x07, + NM_LWE = 0x08, + NM_SWE = 0x09, + NM_P_LLE = 0x0a, + NM_P_SCE = 0x0b, +}; + /* P.LS.WM instruction pool */ enum { NM_LWM = 0x00, -- 2.7.4