From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFFCAC6787D for ; Mon, 8 Oct 2018 03:25:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9AAB12077C for ; Mon, 8 Oct 2018 03:25:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9AAB12077C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727242AbeJHKf1 (ORCPT ); Mon, 8 Oct 2018 06:35:27 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:3113 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726065AbeJHKem (ORCPT ); Mon, 8 Oct 2018 06:34:42 -0400 X-UUID: 33c433665830414abd9efc77ac58e398-20181008 X-UUID: 33c433665830414abd9efc77ac58e398-20181008 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 934191888; Mon, 08 Oct 2018 11:25:02 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 8 Oct 2018 11:25:00 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 8 Oct 2018 11:25:00 +0800 From: To: , , , , , , CC: , , , , , , , , , Subject: [PATCH v6 2/9] PCI: mediatek: Fixup class ID for MT7622 as PCI_CLASS_BRIDGE_PCI Date: Mon, 8 Oct 2018 11:24:41 +0800 Message-ID: <1538969088-7136-3-git-send-email-honghui.zhang@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1538969088-7136-1-git-send-email-honghui.zhang@mediatek.com> References: <1538969088-7136-1-git-send-email-honghui.zhang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: CE1C697090A12BDC18CE687870DD7787375CFC91E4D571329D5D943C1CCA09912000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Honghui Zhang The PCIe controller of MT7622 has TYPE 1 configuration space type, but the HW default class type values is invalid. The commit 101c92dc80c8 ("PCI: mediatek: Set up vendor ID and class type for MT7622") have set the class ID for MT7622 as PCI_CLASS_BRIDGE_HOST, but it's not workable for MT7622: In __pci_bus_assign_resources, the framework only setup bridge's resource window only if class type is PCI_CLASS_BRIDGE_PCI. Or it will leave the subordinary PCIe device's MMIO window un-touched. Fixup the class type to PCI_CLASS_BRIDGE_PCI as most of the controller driver do. Signed-off-by: Honghui Zhang Acked-by: Ryder Lee --- drivers/pci/controller/pcie-mediatek.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c index 288b8e2..bcdac9b 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -432,7 +432,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) val = PCI_VENDOR_ID_MEDIATEK; writew(val, port->base + PCIE_CONF_VEND_ID); - val = PCI_CLASS_BRIDGE_HOST; + val = PCI_CLASS_BRIDGE_PCI; writew(val, port->base + PCIE_CONF_CLASS_ID); } -- 2.6.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Subject: [PATCH v6 2/9] PCI: mediatek: Fixup class ID for MT7622 as PCI_CLASS_BRIDGE_PCI Date: Mon, 8 Oct 2018 11:24:41 +0800 Message-ID: <1538969088-7136-3-git-send-email-honghui.zhang@mediatek.com> References: <1538969088-7136-1-git-send-email-honghui.zhang@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1538969088-7136-1-git-send-email-honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+glpam-linux-mediatek=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org, bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, ryder.lee-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org Cc: youlin.pei-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, marc.zyngier-5wv7dgnIgG8@public.gmane.org, sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, honghui.zhang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, eddie.huang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org List-Id: devicetree@vger.kernel.org From: Honghui Zhang The PCIe controller of MT7622 has TYPE 1 configuration space type, but the HW default class type values is invalid. The commit 101c92dc80c8 ("PCI: mediatek: Set up vendor ID and class type for MT7622") have set the class ID for MT7622 as PCI_CLASS_BRIDGE_HOST, but it's not workable for MT7622: In __pci_bus_assign_resources, the framework only setup bridge's resource window only if class type is PCI_CLASS_BRIDGE_PCI. Or it will leave the subordinary PCIe device's MMIO window un-touched. Fixup the class type to PCI_CLASS_BRIDGE_PCI as most of the controller driver do. Signed-off-by: Honghui Zhang Acked-by: Ryder Lee --- drivers/pci/controller/pcie-mediatek.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c index 288b8e2..bcdac9b 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -432,7 +432,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) val = PCI_VENDOR_ID_MEDIATEK; writew(val, port->base + PCIE_CONF_VEND_ID); - val = PCI_CLASS_BRIDGE_HOST; + val = PCI_CLASS_BRIDGE_PCI; writew(val, port->base + PCIE_CONF_CLASS_ID); } -- 2.6.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: honghui.zhang@mediatek.com (honghui.zhang at mediatek.com) Date: Mon, 8 Oct 2018 11:24:41 +0800 Subject: [PATCH v6 2/9] PCI: mediatek: Fixup class ID for MT7622 as PCI_CLASS_BRIDGE_PCI In-Reply-To: <1538969088-7136-1-git-send-email-honghui.zhang@mediatek.com> References: <1538969088-7136-1-git-send-email-honghui.zhang@mediatek.com> Message-ID: <1538969088-7136-3-git-send-email-honghui.zhang@mediatek.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: Honghui Zhang The PCIe controller of MT7622 has TYPE 1 configuration space type, but the HW default class type values is invalid. The commit 101c92dc80c8 ("PCI: mediatek: Set up vendor ID and class type for MT7622") have set the class ID for MT7622 as PCI_CLASS_BRIDGE_HOST, but it's not workable for MT7622: In __pci_bus_assign_resources, the framework only setup bridge's resource window only if class type is PCI_CLASS_BRIDGE_PCI. Or it will leave the subordinary PCIe device's MMIO window un-touched. Fixup the class type to PCI_CLASS_BRIDGE_PCI as most of the controller driver do. Signed-off-by: Honghui Zhang Acked-by: Ryder Lee --- drivers/pci/controller/pcie-mediatek.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c index 288b8e2..bcdac9b 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -432,7 +432,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) val = PCI_VENDOR_ID_MEDIATEK; writew(val, port->base + PCIE_CONF_VEND_ID); - val = PCI_CLASS_BRIDGE_HOST; + val = PCI_CLASS_BRIDGE_PCI; writew(val, port->base + PCIE_CONF_CLASS_ID); } -- 2.6.4