[v1 01/10] drm/i915: introduced pv capability for vgpu

[v1 01/10] drm/i915: introduced pv capability for vgpu

[Xiaolin Zhang]

This u32 pv_caps field is used to control the different
level pvmmio feature for MMIO emulation in GVT.

This field is default zero, no pvmmio feature enabled.

it also add VGT_CAPS_PVMMIO capability BIT for guest to check GVTg
can support PV feature or not.

v1: addressed RFC comment to remove enable_pvmmio module parameter
by pv capability check.
v0: RFC, introudced enable_pvmmio module parameter.

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h    | 11 +++++++++++
 drivers/gpu/drm/i915/i915_params.h |  2 +-
 drivers/gpu/drm/i915/i915_pvinfo.h | 17 ++++++++++++++++-
 drivers/gpu/drm/i915/i915_vgpu.c   | 19 +++++++++++++++++--
 4 files changed, 45 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 794a8a0..d22154a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -56,6 +56,7 @@
 
 #include "i915_params.h"
 #include "i915_reg.h"
+#include "i915_pvinfo.h"
 #include "i915_utils.h"
 
 #include "intel_bios.h"
@@ -1343,6 +1344,7 @@ struct i915_workarounds {
 struct i915_virtual_gpu {
 	bool active;
 	u32 caps;
+	u32 pv_caps;
 };
 
 /* used in computing the new watermarks state */
@@ -2853,6 +2855,11 @@ static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
 	return dev_priv->vgpu.active;
 }
 
+static inline bool intel_vgpu_has_pvmmio(struct drm_i915_private *dev_priv)
+{
+	return dev_priv->vgpu.caps & VGT_CAPS_PVMMIO;
+}
+
 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
 			      enum pipe pipe);
 void
@@ -3880,4 +3887,8 @@ static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
 		return I915_HWS_CSB_WRITE_INDEX;
 }
 
+#define PVMMIO_LEVEL_ENABLE(dev_priv, level)	\
+	(intel_vgpu_active(dev_priv) && intel_vgpu_has_pvmmio(dev_priv) \
+			&& (dev_priv->vgpu.pv_caps & level))
+
 #endif
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 7e56c51..cc2b2f5 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -67,7 +67,7 @@ struct drm_printer;
 	param(bool, nuclear_pageflip, false) \
 	param(bool, enable_dp_mst, true) \
 	param(bool, enable_dpcd_backlight, false) \
-	param(bool, enable_gvt, false)
+	param(bool, enable_gvt, false) \
 
 #define MEMBER(T, member, ...) T member;
 struct i915_params {
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index eeaa3d5..26709e8 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -49,12 +49,26 @@ enum vgt_g2v_type {
 	VGT_G2V_MAX,
 };
 
+#define VGPU_PVMMIO(vgpu) vgpu_vreg_t(vgpu, vgtif_reg(enable_pvmmio))
+
 /*
  * VGT capabilities type
  */
 #define VGT_CAPS_FULL_48BIT_PPGTT	BIT(2)
 #define VGT_CAPS_HWSP_EMULATION		BIT(3)
 #define VGT_CAPS_HUGE_GTT		BIT(4)
+#define VGT_CAPS_PVMMIO		BIT(5)
+
+/*
+ * define different levels of PVMMIO optimization
+ */
+enum pvmmio_levels {
+	PVMMIO_ELSP_SUBMIT = 0x1,
+	PVMMIO_PLANE_UPDATE = 0x2,
+	PVMMIO_PLANE_WM_UPDATE = 0x4,
+	PVMMIO_MASTER_IRQ = 0x8,
+	PVMMIO_PPGTT_UPDATE = 0x10,
+};
 
 struct vgt_if {
 	u64 magic;		/* VGT_MAGIC */
@@ -106,8 +120,9 @@ struct vgt_if {
 
 	u32 execlist_context_descriptor_lo;
 	u32 execlist_context_descriptor_hi;
+	u32 enable_pvmmio;
 
-	u32  rsv7[0x200 - 24];    /* pad to one page */
+	u32  rsv7[0x200 - 25];    /* pad to one page */
 } __packed;
 
 #define vgtif_reg(x) \
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 869cf4a..907bbd2 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -76,9 +76,24 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 	}
 
 	dev_priv->vgpu.caps = __raw_i915_read32(dev_priv, vgtif_reg(vgt_caps));
-
 	dev_priv->vgpu.active = true;
-	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
+
+	if (!intel_vgpu_has_pvmmio(dev_priv)) {
+		DRM_INFO("Virtual GPU for Intel GVT-g detected\n");
+		return;
+	}
+
+	/* If guest wants to enable pvmmio, it needs to enable it explicitly
+	 * through vgt_if interface, and then read back the enable state from
+	 * gvt layer.
+	 */
+	__raw_i915_write32(dev_priv, vgtif_reg(enable_pvmmio),
+			dev_priv->vgpu.pv_caps);
+	dev_priv->vgpu.pv_caps = __raw_i915_read32(dev_priv,
+			vgtif_reg(enable_pvmmio));
+
+	DRM_INFO("Virtual GPU for Intel GVT-g detected with pvmmio 0x%x\n",
+			dev_priv->vgpu.pv_caps);
 }
 
 bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
-- 
2.7.4

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[v1 02/10] drm/i915: get ready of memory for pvmmio

[Xiaolin Zhang]

To enable pvmmio feature, we need to prepare one 4K shared page
which will be accessed by both guest and backend i915 driver.

guest i915 allocate one page memory and then the guest physical address is
passed to backend i915 driver through PVINFO register so that backend i915
driver can access this shared page without hypeviser trap cost for shared
data exchagne via hyperviser read_gpa functionality.

v1: addressed RFC comment to move both shared_page_lock and shared_page
to i915_virtual_gpu structure
v0: RFC

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c    |  4 ++++
 drivers/gpu/drm/i915/i915_drv.h    |  2 ++
 drivers/gpu/drm/i915/i915_pvinfo.h | 24 +++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_vgpu.c   | 19 ++++++++++++++++++-
 4 files changed, 47 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 19302342..72669f4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -987,6 +987,8 @@ static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 
 	intel_teardown_mchbar(dev_priv);
 	pci_iounmap(pdev, dev_priv->regs);
+	if (intel_vgpu_active(dev_priv) && dev_priv->vgpu.shared_page)
+		free_page((unsigned long)dev_priv->vgpu.shared_page);
 }
 
 /**
@@ -1029,6 +1031,8 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 	return 0;
 
 err_uncore:
+	if (intel_vgpu_active(dev_priv) && dev_priv->vgpu.shared_page)
+		free_page((unsigned long)dev_priv->vgpu.shared_page);
 	intel_uncore_fini(dev_priv);
 err_bridge:
 	pci_dev_put(dev_priv->bridge_dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d22154a..2c131d4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1345,6 +1345,8 @@ struct i915_virtual_gpu {
 	bool active;
 	u32 caps;
 	u32 pv_caps;
+	spinlock_t shared_page_lock;
+	struct gvt_shared_page *shared_page;
 };
 
 /* used in computing the new watermarks state */
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index 26709e8..179d558 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -49,6 +49,24 @@ enum vgt_g2v_type {
 	VGT_G2V_MAX,
 };
 
+struct pv_ppgtt_update {
+	u64 pdp;
+	u64 start;
+	u64 length;
+	u32 cache_level;
+};
+
+/*
+ * shared page(4KB) between gvt and VM, could be allocated by guest driver
+ * or a fixed location in PCI bar 0 region
+ */
+struct gvt_shared_page {
+	u32 elsp_data[4];
+	u32 reg_addr;
+	u32 disable_irq;
+	struct pv_ppgtt_update pv_ppgtt;
+};
+
 #define VGPU_PVMMIO(vgpu) vgpu_vreg_t(vgpu, vgtif_reg(enable_pvmmio))
 
 /*
@@ -121,8 +139,12 @@ struct vgt_if {
 	u32 execlist_context_descriptor_lo;
 	u32 execlist_context_descriptor_hi;
 	u32 enable_pvmmio;
+	struct {
+		u32 lo;
+		u32 hi;
+	} shared_page_gpa;
 
-	u32  rsv7[0x200 - 25];    /* pad to one page */
+	u32  rsv7[0x200 - 27];    /* pad to one page */
 } __packed;
 
 #define vgtif_reg(x) \
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 907bbd2..609eefe 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -62,6 +62,7 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 {
 	u64 magic;
 	u16 version_major;
+	u64 shared_page_gpa;
 
 	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
 
@@ -91,7 +92,23 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 			dev_priv->vgpu.pv_caps);
 	dev_priv->vgpu.pv_caps = __raw_i915_read32(dev_priv,
 			vgtif_reg(enable_pvmmio));
-
+	if (intel_vgpu_active(dev_priv) && dev_priv->vgpu.pv_caps) {
+		dev_priv->vgpu.shared_page =  (struct gvt_shared_page *)
+				get_zeroed_page(GFP_KERNEL);
+		if (!dev_priv->vgpu.shared_page) {
+			DRM_ERROR("out of memory for shared page memory\n");
+			return;
+		}
+		shared_page_gpa = __pa(dev_priv->vgpu.shared_page);
+		__raw_i915_write32(dev_priv, vgtif_reg(shared_page_gpa.lo),
+				lower_32_bits(shared_page_gpa));
+		__raw_i915_write32(dev_priv, vgtif_reg(shared_page_gpa.hi),
+				upper_32_bits(shared_page_gpa));
+
+		spin_lock_init(&dev_priv->vgpu.shared_page_lock);
+
+		DRM_INFO("VGPU shared page enabled\n");
+	}
 	DRM_INFO("Virtual GPU for Intel GVT-g detected with pvmmio 0x%x\n",
 			dev_priv->vgpu.pv_caps);
 }
-- 
2.7.4

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[v1 03/10] drm/i915: context submission pvmmio optimization

[Xiaolin Zhang]

It is performance optimization to reduce mmio trap numbers from 4 to
1 durning ELSP porting writing (context submission).

When context subission, to cache elsp_data[4] values in
the shared page, the last elsp_data[0] port writing will be trapped
to gvt for real context submission.

Use PVMMIO_ELSP_SUBMIT to control this level of pvmmio optimization.

v1: rebase
v0: RFC

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_vgpu.c |  2 ++
 drivers/gpu/drm/i915/intel_lrc.c | 37 ++++++++++++++++++++++++++++++++++++-
 2 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 609eefe..84241a7 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -66,6 +66,8 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 
 	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
 
+	dev_priv->vgpu.pv_caps = PVMMIO_ELSP_SUBMIT;
+
 	magic = __raw_i915_read64(dev_priv, vgtif_reg(magic));
 	if (magic != VGT_MAGIC)
 		return;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d604d8a..1f52633 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -407,6 +407,11 @@ static void execlists_submit_ports(struct intel_engine_cs *engine)
 	struct intel_engine_execlists *execlists = &engine->execlists;
 	struct execlist_port *port = execlists->port;
 	unsigned int n;
+	u32 __iomem *elsp =
+		engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
+	u32 *elsp_data;
+	u32 descs[4];
+	int i = 0;
 
 	/*
 	 * We can skip acquiring intel_runtime_pm_get() here as it was taken
@@ -449,8 +454,24 @@ static void execlists_submit_ports(struct intel_engine_cs *engine)
 			GEM_BUG_ON(!n);
 			desc = 0;
 		}
+		if (PVMMIO_LEVEL_ENABLE(engine->i915, PVMMIO_ELSP_SUBMIT)) {
+			GEM_BUG_ON(i >= 4);
+			descs[i] = upper_32_bits(desc);
+			descs[i + 1] = lower_32_bits(desc);
+			i += 2;
+		} else {
+			write_desc(execlists, desc, n);
+		}
+	}
 
-		write_desc(execlists, desc, n);
+	if (PVMMIO_LEVEL_ENABLE(engine->i915, PVMMIO_ELSP_SUBMIT)) {
+		spin_lock(&engine->i915->vgpu.shared_page_lock);
+		elsp_data = engine->i915->vgpu.shared_page->elsp_data;
+		*elsp_data = descs[0];
+		*(elsp_data + 1) = descs[1];
+		*(elsp_data + 2) = descs[2];
+		writel(descs[3], elsp);
+		spin_unlock(&engine->i915->vgpu.shared_page_lock);
 	}
 
 	/* we need to manually load the submit queue */
@@ -493,11 +514,25 @@ static void inject_preempt_context(struct intel_engine_cs *engine)
 	struct intel_engine_execlists *execlists = &engine->execlists;
 	struct intel_context *ce =
 		to_intel_context(engine->i915->preempt_context, engine);
+	u32 __iomem *elsp =
+		engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
+	u32 *elsp_data;
 	unsigned int n;
 
 	GEM_BUG_ON(execlists->preempt_complete_status !=
 		   upper_32_bits(ce->lrc_desc));
 
+	if (PVMMIO_LEVEL_ENABLE(engine->i915, PVMMIO_ELSP_SUBMIT)) {
+		spin_lock(&engine->i915->vgpu.shared_page_lock);
+		elsp_data = engine->i915->vgpu.shared_page->elsp_data;
+		*elsp_data = 0;
+		*(elsp_data + 1) = 0;
+		*(elsp_data + 2) = upper_32_bits(ce->lrc_desc);
+		writel(lower_32_bits(ce->lrc_desc), elsp);
+		spin_unlock(&engine->i915->vgpu.shared_page_lock);
+		return;
+	}
+
 	/*
 	 * Switch to our empty preempt context so
 	 * the state of the GPU is known (idle).
-- 
2.7.4

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[v1 04/10] drm/i915: master irq pvmmio optimization

[Xiaolin Zhang]

Master irq register is accessed twice every irq handling, then trapped
to SOS very frequently. Optimize it by moving master irq register
to share page, writing don't need be trapped.

When need enable irq to let SOS inject irq timely, use another pvmmio
register to achieve this purpose. So avoid one trap when we disable
master irq.

Use PVMMIO_MASTER_IRQ to control this level of pvmmio optimization.

v1: rebase
v0: RFC

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c    | 29 +++++++++++++++++++++++------
 drivers/gpu/drm/i915/i915_pvinfo.h |  3 ++-
 drivers/gpu/drm/i915/i915_vgpu.c   |  2 +-
 3 files changed, 26 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2e24227..54db60a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2901,7 +2901,10 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 	if (!master_ctl)
 		return IRQ_NONE;
 
-	I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
+	if (PVMMIO_LEVEL_ENABLE(dev_priv, PVMMIO_MASTER_IRQ))
+		dev_priv->vgpu.shared_page->disable_irq = 1;
+	else
+		I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
 
 	/* Find, clear, then process each source of interrupt */
 	gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
@@ -2913,7 +2916,12 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 		enable_rpm_wakeref_asserts(dev_priv);
 	}
 
-	I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
+	if (PVMMIO_LEVEL_ENABLE(dev_priv, PVMMIO_MASTER_IRQ)) {
+		dev_priv->vgpu.shared_page->disable_irq = 0;
+		__raw_i915_write32(dev_priv, vgtif_reg(check_pending_irq), 1);
+	} else {
+		I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
+	}
 
 	gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
 
@@ -3598,8 +3606,12 @@ static void gen8_irq_reset(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int pipe;
 
-	I915_WRITE(GEN8_MASTER_IRQ, 0);
-	POSTING_READ(GEN8_MASTER_IRQ);
+	if (PVMMIO_LEVEL_ENABLE(dev_priv, PVMMIO_MASTER_IRQ)) {
+		dev_priv->vgpu.shared_page->disable_irq = 1;
+	} else {
+		I915_WRITE(GEN8_MASTER_IRQ, 0);
+		POSTING_READ(GEN8_MASTER_IRQ);
+	}
 
 	gen8_gt_irq_reset(dev_priv);
 
@@ -4244,8 +4256,13 @@ static int gen8_irq_postinstall(struct drm_device *dev)
 	if (HAS_PCH_SPLIT(dev_priv))
 		ibx_irq_postinstall(dev);
 
-	I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
-	POSTING_READ(GEN8_MASTER_IRQ);
+	if (PVMMIO_LEVEL_ENABLE(dev_priv, PVMMIO_MASTER_IRQ)) {
+		dev_priv->vgpu.shared_page->disable_irq = 0;
+		__raw_i915_write32(dev_priv, vgtif_reg(check_pending_irq), 1);
+	} else {
+		I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
+		POSTING_READ(GEN8_MASTER_IRQ);
+	}
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index 179d558..1e24c45 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -143,8 +143,9 @@ struct vgt_if {
 		u32 lo;
 		u32 hi;
 	} shared_page_gpa;
+	u32 check_pending_irq;
 
-	u32  rsv7[0x200 - 27];    /* pad to one page */
+	u32  rsv7[0x200 - 28];    /* pad to one page */
 } __packed;
 
 #define vgtif_reg(x) \
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 84241a7..6471574 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -66,7 +66,7 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 
 	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
 
-	dev_priv->vgpu.pv_caps = PVMMIO_ELSP_SUBMIT;
+	dev_priv->vgpu.pv_caps = PVMMIO_ELSP_SUBMIT | PVMMIO_MASTER_IRQ;
 
 	magic = __raw_i915_read64(dev_priv, vgtif_reg(magic));
 	if (magic != VGT_MAGIC)
-- 
2.7.4

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[v1 05/10] drm/i915: ppgtt update pvmmio optimization

[Xiaolin Zhang]

This patch extends g2v notification to notify host GVT-g of
ppgtt update from guest, including alloc_4lvl, clear_4lv4 and
insert_4lvl. It uses shared page to pass the additional params.
This patch also add one new pvmmio level to control ppgtt update.

Use PVMMIO_PPGTT_UPDATE to control this level of pvmmio optimization.

v1: rebase
v0: RFC

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 36 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_pvinfo.h  |  3 +++
 drivers/gpu/drm/i915/i915_vgpu.c    |  3 ++-
 3 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 29ca900..3e7cb35 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -941,6 +941,8 @@ static void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
 	struct i915_pml4 *pml4 = &ppgtt->pml4;
 	struct i915_page_directory_pointer *pdp;
 	unsigned int pml4e;
+	u64 orig_start = start;
+	u64 orig_length = length;
 
 	GEM_BUG_ON(!use_4lvl(vm));
 
@@ -954,6 +956,16 @@ static void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
 
 		free_pdp(vm, pdp);
 	}
+
+	if (PVMMIO_LEVEL_ENABLE(vm->i915, PVMMIO_PPGTT_UPDATE)) {
+		struct drm_i915_private *dev_priv = vm->i915;
+		struct pv_ppgtt_update *pv_ppgtt =
+				&dev_priv->vgpu.shared_page->pv_ppgtt;
+		pv_ppgtt->pdp = px_dma(pml4);
+		pv_ppgtt->start = orig_start;
+		pv_ppgtt->length = orig_length;
+		I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_CLEAR);
+	}
 }
 
 static inline struct sgt_dma {
@@ -1195,6 +1207,18 @@ static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
 
 		vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
 	}
+
+	if (PVMMIO_LEVEL_ENABLE(vm->i915, PVMMIO_PPGTT_UPDATE)) {
+		struct drm_i915_private *dev_priv = vm->i915;
+		struct pv_ppgtt_update *pv_ppgtt =
+				&dev_priv->vgpu.shared_page->pv_ppgtt;
+		pv_ppgtt->pdp = px_dma(&ppgtt->pml4);
+		pv_ppgtt->start = vma->node.start;
+		pv_ppgtt->length = vma->node.size;
+		pv_ppgtt->cache_level = cache_level;
+		I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_INSERT);
+	}
+
 }
 
 static void gen8_free_page_tables(struct i915_address_space *vm,
@@ -1438,6 +1462,8 @@ static int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
 	u64 from = start;
 	u32 pml4e;
 	int ret;
+	u64 orig_start = start;
+	u64 orig_length = length;
 
 	gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
 		if (pml4->pdps[pml4e] == vm->scratch_pdp) {
@@ -1454,6 +1480,16 @@ static int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
 			goto unwind_pdp;
 	}
 
+	if (PVMMIO_LEVEL_ENABLE(vm->i915, PVMMIO_PPGTT_UPDATE)) {
+		struct drm_i915_private *dev_priv = vm->i915;
+		struct pv_ppgtt_update *pv_ppgtt =
+				&dev_priv->vgpu.shared_page->pv_ppgtt;
+		pv_ppgtt->pdp = px_dma(pml4);
+		pv_ppgtt->start = orig_start;
+		pv_ppgtt->length = orig_length;
+		I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_ALLOC);
+	}
+
 	return 0;
 
 unwind_pdp:
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index 1e24c45..790db50 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -46,6 +46,9 @@ enum vgt_g2v_type {
 	VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
 	VGT_G2V_EXECLIST_CONTEXT_CREATE,
 	VGT_G2V_EXECLIST_CONTEXT_DESTROY,
+	VGT_G2V_PPGTT_L4_ALLOC,
+	VGT_G2V_PPGTT_L4_CLEAR,
+	VGT_G2V_PPGTT_L4_INSERT,
 	VGT_G2V_MAX,
 };
 
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 6471574..ee81b62 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -66,7 +66,8 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 
 	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
 
-	dev_priv->vgpu.pv_caps = PVMMIO_ELSP_SUBMIT | PVMMIO_MASTER_IRQ;
+	dev_priv->vgpu.pv_caps = PVMMIO_ELSP_SUBMIT
+			| PVMMIO_MASTER_IRQ | PVMMIO_PPGTT_UPDATE;
 
 	magic = __raw_i915_read64(dev_priv, vgtif_reg(magic));
 	if (magic != VGT_MAGIC)
-- 
2.7.4

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[v1 06/10] drm/i915/gvt: GVTg handle enable_pvmmio PVINFO register

[Xiaolin Zhang]

implement enable_pvmmio PVINFO register handler in GVTg to
control different level pvmmio optimization within guest.

report VGT_CAPS_PVMMIO capability in pvinfo page for guest.

v1: rebase
v0: RFC

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/gvt/handlers.c | 10 ++++++++++
 drivers/gpu/drm/i915/gvt/vgpu.c     |  7 +++++++
 2 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 9692d2a..3cc6a8e 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1242,6 +1242,16 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 	case _vgtif_reg(g2v_notify):
 		ret = handle_g2v_notification(vgpu, data);
 		break;
+	case _vgtif_reg(enable_pvmmio):
+		if (vgpu->gvt->dev_priv->vgpu.pv_caps) {
+			vgpu_vreg(vgpu, offset) = data &
+				vgpu->gvt->dev_priv->vgpu.pv_caps;
+			DRM_INFO("vgpu id=%d pvmmio=0x%x\n",
+				vgpu->id, VGPU_PVMMIO(vgpu));
+		} else {
+			vgpu_vreg(vgpu, offset) = 0;
+		}
+		break;
 	/* add xhot and yhot to handled list to avoid error log */
 	case _vgtif_reg(cursor_x_hot):
 	case _vgtif_reg(cursor_y_hot):
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index c628be0..d1674db 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -47,6 +47,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
+	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_PVMMIO;
 
 	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
 		vgpu_aperture_gmadr_base(vgpu);
@@ -62,6 +63,8 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
 	vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;
 	vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;
 
+	vgpu_vreg_t(vgpu, vgtif_reg(enable_pvmmio)) = 0;
+
 	gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
 	gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
 		vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
@@ -491,6 +494,8 @@ struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
 	return vgpu;
 }
 
+#define _vgtif_reg(x) \
+	(VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
 /**
  * intel_gvt_reset_vgpu_locked - reset a virtual GPU by DMLR or GT reset
  * @vgpu: virtual GPU
@@ -525,6 +530,7 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
 	struct intel_gvt *gvt = vgpu->gvt;
 	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 	unsigned int resetting_eng = dmlr ? ALL_ENGINES : engine_mask;
+	int enable_pvmmio = vgpu_vreg(vgpu, _vgtif_reg(enable_pvmmio));
 
 	gvt_dbg_core("------------------------------------------\n");
 	gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
@@ -556,6 +562,7 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
 
 		intel_vgpu_reset_mmio(vgpu, dmlr);
 		populate_pvinfo_page(vgpu);
+		vgpu_vreg(vgpu, _vgtif_reg(enable_pvmmio)) = enable_pvmmio;
 		intel_vgpu_reset_display(vgpu);
 
 		if (dmlr) {
-- 
2.7.4

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[v1 07/10] drm/i915/gvt: GVTg read_shared_page implementation

[Xiaolin Zhang]

GVTg implemented the read_shared_page functionality based on
hypervisor_read_gpa().

the shared_page_gpa was passed from guest driver through PVINFO
shared_page_gpa register.

v1: rebase
v0: RFC

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/gvt/gvt.h      |  4 +++-
 drivers/gpu/drm/i915/gvt/handlers.c |  5 +++++
 drivers/gpu/drm/i915/gvt/vgpu.c     | 14 ++++++++++++++
 3 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 31f6cdb..7562f75 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -232,6 +232,7 @@ struct intel_vgpu {
 	struct completion vblank_done;
 
 	u32 scan_nonprivbb;
+	u64 shared_page_gpa;
 };
 
 /* validating GM healthy status*/
@@ -690,7 +691,8 @@ int intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu);
 void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu);
 int intel_gvt_debugfs_init(struct intel_gvt *gvt);
 void intel_gvt_debugfs_clean(struct intel_gvt *gvt);
-
+void intel_gvt_read_shared_page(struct intel_vgpu *vgpu,
+		unsigned int offset, void *buf, unsigned long len);
 
 #include "trace.h"
 #include "mpt.h"
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 3cc6a8e..42dfe03 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1252,6 +1252,11 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 			vgpu_vreg(vgpu, offset) = 0;
 		}
 		break;
+	case _vgtif_reg(shared_page_gpa.lo):
+	case _vgtif_reg(shared_page_gpa.hi):
+		vgpu->shared_page_gpa = vgpu_vreg64_t(vgpu,
+			vgtif_reg(shared_page_gpa));
+		break;
 	/* add xhot and yhot to handled list to avoid error log */
 	case _vgtif_reg(cursor_x_hot):
 	case _vgtif_reg(cursor_y_hot):
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index d1674db..44507c9 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -591,3 +591,17 @@ void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
 	intel_gvt_reset_vgpu_locked(vgpu, true, 0);
 	mutex_unlock(&vgpu->vgpu_lock);
 }
+
+/**
+ * intel_gvt_read_shared_page - read content from shared page
+ */
+void intel_gvt_read_shared_page(struct intel_vgpu *vgpu,
+		unsigned int offset, void *buf, unsigned long len)
+{
+	int ret = 0;
+	unsigned long gpa = vgpu->shared_page_gpa + offset;
+
+	ret = intel_gvt_hypervisor_read_gpa(vgpu, gpa, buf, len);
+	if (ret)
+		gvt_vgpu_err("read shared page (offset %x) failed", offset);
+}
-- 
2.7.4

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[v1 08/10] drm/i915/gvt: GVTg support context submission pvmmio optimization

[Xiaolin Zhang]

implemented context submission pvmmio optimizaiton with GVTg.

GVTg to read context submission data (elsp_data) from the shared_page
directly without trap cost to improve guest GPU peformrnace.

v1: rebase
v0: RFC

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/gvt/handlers.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 42dfe03..63d1597 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1667,6 +1667,8 @@ static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 	int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
 	struct intel_vgpu_execlist *execlist;
 	u32 data = *(u32 *)p_data;
+	u32 elsp_data[4];
+	u32 elsp_data_off;
 	int ret = 0;
 
 	if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES))
@@ -1674,6 +1676,16 @@ static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 
 	execlist = &vgpu->submission.execlist[ring_id];
 
+	if (VGPU_PVMMIO(vgpu) & PVMMIO_ELSP_SUBMIT) {
+		elsp_data_off = offsetof(struct gvt_shared_page, elsp_data);
+		intel_gvt_read_shared_page(vgpu, elsp_data_off, &elsp_data, 16);
+		execlist->elsp_dwords.data[3] = elsp_data[0];
+		execlist->elsp_dwords.data[2] = elsp_data[1];
+		execlist->elsp_dwords.data[1] = elsp_data[2];
+		execlist->elsp_dwords.data[0] = data;
+		return intel_vgpu_submit_execlist(vgpu, ring_id);
+	}
+
 	execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;
 	if (execlist->elsp_dwords.index == 3) {
 		ret = intel_vgpu_submit_execlist(vgpu, ring_id);
-- 
2.7.4

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[v1 09/10] drm/i915/gvt: GVTg support master irq pvmmio optimization

[Xiaolin Zhang]

GVTg to check master irq status in the shared_page instead
of register.

v1: rebase
v0: RFC

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/gvt/handlers.c  |  4 ++++
 drivers/gpu/drm/i915/gvt/interrupt.c | 17 +++++++++++++----
 2 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 63d1597..7a53011 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1231,6 +1231,7 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 {
 	u32 data;
 	int ret;
+	struct intel_gvt_irq_ops *ops = vgpu->gvt->irq.ops;
 
 	write_vreg(vgpu, offset, p_data, bytes);
 	data = vgpu_vreg(vgpu, offset);
@@ -1257,6 +1258,9 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 		vgpu->shared_page_gpa = vgpu_vreg64_t(vgpu,
 			vgtif_reg(shared_page_gpa));
 		break;
+	case _vgtif_reg(check_pending_irq):
+		ops->check_pending_irq(vgpu);
+		break;
 	/* add xhot and yhot to handled list to avoid error log */
 	case _vgtif_reg(cursor_x_hot):
 	case _vgtif_reg(cursor_y_hot):
diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c
index 5daa23a..c1884f8 100644
--- a/drivers/gpu/drm/i915/gvt/interrupt.c
+++ b/drivers/gpu/drm/i915/gvt/interrupt.c
@@ -465,10 +465,19 @@ static void gen8_check_pending_irq(struct intel_vgpu *vgpu)
 {
 	struct intel_gvt_irq *irq = &vgpu->gvt->irq;
 	int i;
-
-	if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &
-				GEN8_MASTER_IRQ_CONTROL))
-		return;
+	u32 offset;
+	u32 disable_irq;
+
+	if (VGPU_PVMMIO(vgpu) & PVMMIO_MASTER_IRQ) {
+		offset = offsetof(struct gvt_shared_page, disable_irq);
+		intel_gvt_read_shared_page(vgpu, offset, &disable_irq, 4);
+		if (disable_irq)
+			return;
+	} else {
+		if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &
+		       GEN8_MASTER_IRQ_CONTROL))
+			return;
+	}
 
 	for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {
 		struct intel_gvt_irq_info *info = irq->info[i];
-- 
2.7.4

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[v1 10/10] drm/i915/gvt: GVTg support ppgtt pvmmio optimization

[Xiaolin Zhang]

This patch handles ppgtt update from g2v notification.

It read out ppgtt pte entries from guest pte tables page and
convert them to host pfns.

It creates local ppgtt tables and insert the content pages
into the local ppgtt tables directly, which does not track
the usage of guest page table and removes the cost of write
protection from the original shadow page mechansim.

v1: rebase
v0: RFC

Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/gvt/gtt.c      | 318 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/gvt/gtt.h      |   9 +
 drivers/gpu/drm/i915/gvt/handlers.c |  13 +-
 3 files changed, 338 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 58e166e..8d3e21a 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1744,6 +1744,26 @@ static int ppgtt_handle_guest_write_page_table_bytes(
 	return 0;
 }
 
+static void invalidate_mm_pv(struct intel_vgpu_mm *mm)
+{
+	struct intel_vgpu *vgpu = mm->vgpu;
+	struct intel_gvt *gvt = vgpu->gvt;
+	struct intel_gvt_gtt *gtt = &gvt->gtt;
+	struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
+	struct intel_gvt_gtt_entry se;
+
+	i915_ppgtt_close(&mm->ppgtt->vm);
+	i915_ppgtt_put(mm->ppgtt);
+
+	ppgtt_get_shadow_root_entry(mm, &se, 0);
+	if (!ops->test_present(&se))
+		return;
+	se.val64 = 0;
+	ppgtt_set_shadow_root_entry(mm, &se, 0);
+
+	mm->ppgtt_mm.shadowed  = false;
+}
+
 static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
 {
 	struct intel_vgpu *vgpu = mm->vgpu;
@@ -1756,6 +1776,11 @@ static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
 	if (!mm->ppgtt_mm.shadowed)
 		return;
 
+	if (VGPU_PVMMIO(mm->vgpu) & PVMMIO_PPGTT_UPDATE) {
+		invalidate_mm_pv(mm);
+		return;
+	}
+
 	for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.shadow_pdps); index++) {
 		ppgtt_get_shadow_root_entry(mm, &se, index);
 
@@ -1773,6 +1798,26 @@ static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
 	mm->ppgtt_mm.shadowed = false;
 }
 
+static int shadow_mm_pv(struct intel_vgpu_mm *mm)
+{
+	struct intel_vgpu *vgpu = mm->vgpu;
+	struct intel_gvt *gvt = vgpu->gvt;
+	struct intel_gvt_gtt_entry se;
+
+	mm->ppgtt = i915_ppgtt_create(gvt->dev_priv, NULL);
+	if (IS_ERR(mm->ppgtt)) {
+		gvt_vgpu_err("fail to create ppgtt for pdp 0x%llx\n",
+				px_dma(&mm->ppgtt->pml4));
+		return PTR_ERR(mm->ppgtt);
+	}
+
+	se.type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
+	se.val64 = px_dma(&mm->ppgtt->pml4);
+	ppgtt_set_shadow_root_entry(mm, &se, 0);
+	mm->ppgtt_mm.shadowed  = true;
+
+	return 0;
+}
 
 static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm)
 {
@@ -1787,6 +1832,9 @@ static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm)
 	if (mm->ppgtt_mm.shadowed)
 		return 0;
 
+	if (VGPU_PVMMIO(mm->vgpu) & PVMMIO_PPGTT_UPDATE)
+		return shadow_mm_pv(mm);
+
 	mm->ppgtt_mm.shadowed = true;
 
 	for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.guest_pdps); index++) {
@@ -2767,3 +2815,273 @@ void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu)
 	intel_vgpu_destroy_all_ppgtt_mm(vgpu);
 	intel_vgpu_reset_ggtt(vgpu, true);
 }
+
+int intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[])
+{
+	struct intel_vgpu_mm *mm;
+	int ret = 0;
+	u32 offset;
+	struct pv_ppgtt_update pv_ppgtt;
+
+	offset = offsetof(struct gvt_shared_page, pv_ppgtt);
+	intel_gvt_read_shared_page(vgpu, offset, &pv_ppgtt, sizeof(pv_ppgtt));
+
+	mm = intel_vgpu_find_ppgtt_mm(vgpu, &pv_ppgtt.pdp);
+	if (!mm) {
+		gvt_vgpu_err("failed to find pdp 0x%llx\n", pv_ppgtt.pdp);
+		ret = -EINVAL;
+	} else {
+		ret = mm->ppgtt->vm.allocate_va_range(&mm->ppgtt->vm,
+			pv_ppgtt.start, pv_ppgtt.length);
+		if (ret)
+			gvt_vgpu_err("failed to alloc %llx\n", pv_ppgtt.pdp);
+	}
+
+	return ret;
+}
+
+int intel_vgpu_g2v_pv_ppgtt_clear_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[])
+{
+	struct intel_vgpu_mm *mm;
+	int ret = 0;
+	u32 offset;
+	struct pv_ppgtt_update pv_ppgtt;
+
+	offset = offsetof(struct gvt_shared_page, pv_ppgtt);
+	intel_gvt_read_shared_page(vgpu, offset, &pv_ppgtt, sizeof(pv_ppgtt));
+	mm = intel_vgpu_find_ppgtt_mm(vgpu, &pv_ppgtt.pdp);
+	if (!mm) {
+		gvt_vgpu_err("failed to find pdp 0x%llx\n", pv_ppgtt.pdp);
+		ret = -EINVAL;
+	} else {
+		mm->ppgtt->vm.clear_range(&mm->ppgtt->vm,
+			pv_ppgtt.start, pv_ppgtt.length);
+	}
+
+	return ret;
+}
+
+#define GEN8_PML4E_SIZE		(1UL << GEN8_PML4E_SHIFT)
+#define GEN8_PML4E_SIZE_MASK	(~(GEN8_PML4E_SIZE - 1))
+#define GEN8_PDPE_SIZE		(1UL << GEN8_PDPE_SHIFT)
+#define GEN8_PDPE_SIZE_MASK	(~(GEN8_PDPE_SIZE - 1))
+#define GEN8_PDE_SIZE		(1UL << GEN8_PDE_SHIFT)
+#define GEN8_PDE_SIZE_MASK	(~(GEN8_PDE_SIZE - 1))
+
+#define pml4_addr_end(addr, end)					\
+({	unsigned long __boundary = \
+			((addr) + GEN8_PML4E_SIZE) & GEN8_PML4E_SIZE_MASK; \
+	(__boundary < (end)) ? __boundary : (end);		\
+})
+
+#define pdp_addr_end(addr, end)						\
+({	unsigned long __boundary = \
+			((addr) + GEN8_PDPE_SIZE) & GEN8_PDPE_SIZE_MASK; \
+	(__boundary < (end)) ? __boundary : (end);		\
+})
+
+#define pd_addr_end(addr, end)						\
+({	unsigned long __boundary = \
+			((addr) + GEN8_PDE_SIZE) & GEN8_PDE_SIZE_MASK;	\
+	(__boundary < (end)) ? __boundary : (end);		\
+})
+
+struct ppgtt_walk {
+	unsigned long *mfns;
+	int mfn_index;
+	unsigned long *pt;
+};
+
+static int walk_pt_range(struct intel_vgpu *vgpu, u64 pt,
+				u64 start, u64 end, struct ppgtt_walk *walk)
+{
+	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
+	struct intel_gvt_gtt_gma_ops *gma_ops = vgpu->gvt->gtt.gma_ops;
+	unsigned long start_index, end_index;
+	int ret;
+	int i;
+	unsigned long mfn, gfn;
+
+	start_index = gma_ops->gma_to_pte_index(start);
+	end_index = ((end - start) >> PAGE_SHIFT) + start_index;
+
+	ret = intel_gvt_hypervisor_read_gpa(vgpu,
+		(pt & PAGE_MASK) + (start_index << info->gtt_entry_size_shift),
+		walk->pt + start_index,
+		(end_index - start_index) << info->gtt_entry_size_shift);
+	if (ret) {
+		gvt_vgpu_err("fail to read gpa %llx\n", pt);
+		return ret;
+	}
+
+	for (i = start_index; i < end_index; i++) {
+		gfn = walk->pt[i] >> PAGE_SHIFT;
+		mfn = intel_gvt_hypervisor_gfn_to_mfn(vgpu, gfn);
+		if (mfn == INTEL_GVT_INVALID_ADDR) {
+			gvt_vgpu_err("fail to translate gfn: 0x%lx\n", gfn);
+			return -ENXIO;
+		}
+		walk->mfns[walk->mfn_index++] = mfn << PAGE_SHIFT;
+	}
+
+	return 0;
+}
+
+
+static int walk_pd_range(struct intel_vgpu *vgpu, u64 pd,
+				u64 start, u64 end, struct ppgtt_walk *walk)
+{
+	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
+	struct intel_gvt_gtt_gma_ops *gma_ops = vgpu->gvt->gtt.gma_ops;
+	unsigned long index;
+	u64 pt, next;
+	int ret  = 0;
+
+	do {
+		index = gma_ops->gma_to_pde_index(start);
+
+		ret = intel_gvt_hypervisor_read_gpa(vgpu,
+			(pd & PAGE_MASK) + (index <<
+			info->gtt_entry_size_shift), &pt, 8);
+		if (ret)
+			return ret;
+		next = pd_addr_end(start, end);
+		walk_pt_range(vgpu, pt, start, next, walk);
+
+		start = next;
+	} while (start != end);
+
+	return ret;
+}
+
+
+static int walk_pdp_range(struct intel_vgpu *vgpu, u64 pdp,
+				  u64 start, u64 end, struct ppgtt_walk *walk)
+{
+	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
+	struct intel_gvt_gtt_gma_ops *gma_ops = vgpu->gvt->gtt.gma_ops;
+	unsigned long index;
+	u64 pd, next;
+	int ret  = 0;
+
+	do {
+		index = gma_ops->gma_to_l4_pdp_index(start);
+
+		ret = intel_gvt_hypervisor_read_gpa(vgpu,
+			(pdp & PAGE_MASK) + (index <<
+			info->gtt_entry_size_shift), &pd, 8);
+		if (ret)
+			return ret;
+		next = pdp_addr_end(start, end);
+		walk_pd_range(vgpu, pd, start, next, walk);
+		start = next;
+	} while (start != end);
+
+	return ret;
+}
+
+
+static int walk_pml4_range(struct intel_vgpu *vgpu, u64 pml4,
+				u64 start, u64 end, struct ppgtt_walk *walk)
+{
+	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
+	struct intel_gvt_gtt_gma_ops *gma_ops = vgpu->gvt->gtt.gma_ops;
+	unsigned long index;
+	u64 pdp, next;
+	int ret  = 0;
+
+	do {
+		index = gma_ops->gma_to_pml4_index(start);
+		ret = intel_gvt_hypervisor_read_gpa(vgpu,
+			(pml4 & PAGE_MASK) + (index <<
+			info->gtt_entry_size_shift), &pdp, 8);
+		if (ret)
+			return ret;
+		next = pml4_addr_end(start, end);
+		walk_pdp_range(vgpu, pdp, start, next, walk);
+		start = next;
+	} while (start != end);
+
+	return ret;
+}
+
+int intel_vgpu_g2v_pv_ppgtt_insert_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[])
+{
+	struct intel_vgpu_mm *mm;
+	u64 pml4, start, length;
+	u32 cache_level;
+	int ret = 0;
+	struct sg_table st;
+	struct scatterlist *sg = NULL;
+	int num_pages;
+	struct i915_vma vma;
+	struct ppgtt_walk walk;
+	int i;
+	u32 offset;
+	struct pv_ppgtt_update pv_ppgtt;
+
+	offset = offsetof(struct gvt_shared_page, pv_ppgtt);
+	intel_gvt_read_shared_page(vgpu, offset, &pv_ppgtt, sizeof(pv_ppgtt));
+	pml4 = pv_ppgtt.pdp;
+	start = pv_ppgtt.start;
+	length = pv_ppgtt.length;
+	cache_level = pv_ppgtt.cache_level;
+	num_pages = length >> PAGE_SHIFT;
+
+	mm = intel_vgpu_find_ppgtt_mm(vgpu, &pml4);
+	if (!mm) {
+		gvt_vgpu_err("fail to find mm for pml4 0x%llx\n", pml4);
+		return -EINVAL;
+	}
+
+	walk.mfn_index = 0;
+	walk.mfns = NULL;
+	walk.pt = NULL;
+
+	walk.mfns = kmalloc_array(num_pages,
+			sizeof(unsigned long), GFP_KERNEL);
+	if (!walk.mfns) {
+		ret = -ENOMEM;
+		goto fail;
+	}
+
+	walk.pt = (unsigned long *)__get_free_pages(GFP_KERNEL, 0);
+	if (!walk.pt) {
+		ret = -ENOMEM;
+		goto fail;
+	}
+
+	if (sg_alloc_table(&st, num_pages, GFP_KERNEL)) {
+		ret = -ENOMEM;
+		goto fail;
+	}
+
+	ret = walk_pml4_range(vgpu, pml4, start, start + length, &walk);
+	if (ret)
+		goto fail_free_sg;
+
+	WARN_ON(num_pages != walk.mfn_index);
+
+	for_each_sg(st.sgl, sg, num_pages, i) {
+		sg->offset = 0;
+		sg->length = PAGE_SIZE;
+		sg_dma_address(sg) = walk.mfns[i];
+		sg_dma_len(sg) = PAGE_SIZE;
+	}
+
+	memset(&vma, 0, sizeof(vma));
+	vma.node.start = start;
+	vma.pages = &st;
+	mm->ppgtt->vm.insert_entries(&mm->ppgtt->vm, &vma, cache_level, 0);
+
+fail_free_sg:
+	sg_free_table(&st);
+fail:
+	kfree(walk.mfns);
+	free_page((unsigned long)walk.pt);
+
+	return ret;
+}
diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
index a11bfee..4edaed9 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.h
+++ b/drivers/gpu/drm/i915/gvt/gtt.h
@@ -141,6 +141,7 @@ struct intel_gvt_partial_pte {
 
 struct intel_vgpu_mm {
 	enum intel_gvt_mm_type type;
+	struct i915_hw_ppgtt *ppgtt;
 	struct intel_vgpu *vgpu;
 
 	struct kref ref;
@@ -277,4 +278,12 @@ int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu,
 int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
 	unsigned int off, void *p_data, unsigned int bytes);
 
+int intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[]);
+
+int intel_vgpu_g2v_pv_ppgtt_clear_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[]);
+
+int intel_vgpu_g2v_pv_ppgtt_insert_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[]);
 #endif /* _GVT_GTT_H_ */
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 7a53011..1ae21cb 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1186,7 +1186,7 @@ static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
 	intel_gvt_gtt_type_t root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
 	struct intel_vgpu_mm *mm;
 	u64 *pdps;
-
+	int ret = 0;
 	pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
 
 	switch (notification) {
@@ -1199,6 +1199,15 @@ static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
 	case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
 	case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
 		return intel_vgpu_put_ppgtt_mm(vgpu, pdps);
+	case VGT_G2V_PPGTT_L4_ALLOC:
+		ret = intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(vgpu, pdps);
+			break;
+	case VGT_G2V_PPGTT_L4_INSERT:
+		ret = intel_vgpu_g2v_pv_ppgtt_insert_4lvl(vgpu, pdps);
+		break;
+	case VGT_G2V_PPGTT_L4_CLEAR:
+		ret = intel_vgpu_g2v_pv_ppgtt_clear_4lvl(vgpu, pdps);
+		break;
 	case VGT_G2V_EXECLIST_CONTEXT_CREATE:
 	case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
 	case 1:	/* Remove this in guest driver. */
@@ -1206,7 +1215,7 @@ static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
 	default:
 		gvt_vgpu_err("Invalid PV notification %d\n", notification);
 	}
-	return 0;
+	return ret;
 }
 
 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.CHECKPATCH: warning for series starting with [v1,01/10] drm/i915: introduced pv capability for vgpu

[Patchwork]

== Series Details ==

Series: series starting with [v1,01/10] drm/i915: introduced pv capability for vgpu
URL   : https://patchwork.freedesktop.org/series/50851/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
aeb1adffcb63 drm/i915: introduced pv capability for vgpu
-:56: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#56: FILE: drivers/gpu/drm/i915/i915_drv.h:3888:
+#define PVMMIO_LEVEL_ENABLE(dev_priv, level)	\
+	(intel_vgpu_active(dev_priv) && intel_vgpu_has_pvmmio(dev_priv) \
+			&& (dev_priv->vgpu.pv_caps & level))

-:56: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'level' may be better as '(level)' to avoid precedence issues
#56: FILE: drivers/gpu/drm/i915/i915_drv.h:3888:
+#define PVMMIO_LEVEL_ENABLE(dev_priv, level)	\
+	(intel_vgpu_active(dev_priv) && intel_vgpu_has_pvmmio(dev_priv) \
+			&& (dev_priv->vgpu.pv_caps & level))

-:58: CHECK:LOGICAL_CONTINUATIONS: Logical continuations should be on the previous line
#58: FILE: drivers/gpu/drm/i915/i915_drv.h:3890:
+	(intel_vgpu_active(dev_priv) && intel_vgpu_has_pvmmio(dev_priv) \
+			&& (dev_priv->vgpu.pv_caps & level))

-:138: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#138: FILE: drivers/gpu/drm/i915/i915_vgpu.c:91:
+	__raw_i915_write32(dev_priv, vgtif_reg(enable_pvmmio),
+			dev_priv->vgpu.pv_caps);

-:140: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#140: FILE: drivers/gpu/drm/i915/i915_vgpu.c:93:
+	dev_priv->vgpu.pv_caps = __raw_i915_read32(dev_priv,
+			vgtif_reg(enable_pvmmio));

-:143: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#143: FILE: drivers/gpu/drm/i915/i915_vgpu.c:96:
+	DRM_INFO("Virtual GPU for Intel GVT-g detected with pvmmio 0x%x\n",
+			dev_priv->vgpu.pv_caps);

total: 0 errors, 0 warnings, 6 checks, 103 lines checked
317678bb037d drm/i915: get ready of memory for pvmmio
-:50: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#50: FILE: drivers/gpu/drm/i915/i915_drv.h:1348:
+	spinlock_t shared_page_lock;

-:124: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#124: FILE: drivers/gpu/drm/i915/i915_vgpu.c:104:
+		__raw_i915_write32(dev_priv, vgtif_reg(shared_page_gpa.lo),
+				lower_32_bits(shared_page_gpa));

-:126: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#126: FILE: drivers/gpu/drm/i915/i915_vgpu.c:106:
+		__raw_i915_write32(dev_priv, vgtif_reg(shared_page_gpa.hi),
+				upper_32_bits(shared_page_gpa));

total: 0 errors, 0 warnings, 3 checks, 92 lines checked
1dde34d63842 drm/i915: context submission pvmmio optimization
18b5f4aa055d drm/i915: master irq pvmmio optimization
14033ac83189 drm/i915: ppgtt update pvmmio optimization
657a3ae6fb1e drm/i915/gvt: GVTg handle enable_pvmmio PVINFO register
-:29: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#29: FILE: drivers/gpu/drm/i915/gvt/handlers.c:1249:
+			DRM_INFO("vgpu id=%d pvmmio=0x%x\n",
+				vgpu->id, VGPU_PVMMIO(vgpu));

total: 0 errors, 0 warnings, 1 checks, 53 lines checked
3e9412478d43 drm/i915/gvt: GVTg read_shared_page implementation
-:35: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#35: FILE: drivers/gpu/drm/i915/gvt/gvt.h:695:
+void intel_gvt_read_shared_page(struct intel_vgpu *vgpu,
+		unsigned int offset, void *buf, unsigned long len);

-:50: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#50: FILE: drivers/gpu/drm/i915/gvt/handlers.c:1257:
+		vgpu->shared_page_gpa = vgpu_vreg64_t(vgpu,
+			vgtif_reg(shared_page_gpa));

-:68: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#68: FILE: drivers/gpu/drm/i915/gvt/vgpu.c:599:
+void intel_gvt_read_shared_page(struct intel_vgpu *vgpu,
+		unsigned int offset, void *buf, unsigned long len)

total: 0 errors, 0 warnings, 3 checks, 44 lines checked
4e2a15c60584 drm/i915/gvt: GVTg support context submission pvmmio optimization
4cb1532b4851 drm/i915/gvt: GVTg support master irq pvmmio optimization
7ff85a910ce0 drm/i915/gvt: GVTg support ppgtt pvmmio optimization
-:77: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#77: FILE: drivers/gpu/drm/i915/gvt/gtt.c:1810:
+		gvt_vgpu_err("fail to create ppgtt for pdp 0x%llx\n",
+				px_dma(&mm->ppgtt->pml4));

-:107: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#107: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2819:
+int intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[])

-:132: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#132: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2844:
+int intel_vgpu_g2v_pv_ppgtt_clear_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[])

-:160: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'end' - possible side-effects?
#160: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2872:
+#define pml4_addr_end(addr, end)					\
+({	unsigned long __boundary = \
+			((addr) + GEN8_PML4E_SIZE) & GEN8_PML4E_SIZE_MASK; \
+	(__boundary < (end)) ? __boundary : (end);		\
+})

-:166: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'end' - possible side-effects?
#166: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2878:
+#define pdp_addr_end(addr, end)						\
+({	unsigned long __boundary = \
+			((addr) + GEN8_PDPE_SIZE) & GEN8_PDPE_SIZE_MASK; \
+	(__boundary < (end)) ? __boundary : (end);		\
+})

-:172: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'end' - possible side-effects?
#172: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2884:
+#define pd_addr_end(addr, end)						\
+({	unsigned long __boundary = \
+			((addr) + GEN8_PDE_SIZE) & GEN8_PDE_SIZE_MASK;	\
+	(__boundary < (end)) ? __boundary : (end);		\
+})

-:185: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#185: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2897:
+static int walk_pt_range(struct intel_vgpu *vgpu, u64 pt,
+				u64 start, u64 end, struct ppgtt_walk *walk)

-:198: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#198: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2910:
+	ret = intel_gvt_hypervisor_read_gpa(vgpu,
+		(pt & PAGE_MASK) + (start_index << info->gtt_entry_size_shift),

-:219: CHECK:LINE_SPACING: Please don't use multiple blank lines
#219: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2931:
+
+

-:221: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#221: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2933:
+static int walk_pd_range(struct intel_vgpu *vgpu, u64 pd,
+				u64 start, u64 end, struct ppgtt_walk *walk)

-:233: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#233: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2945:
+		ret = intel_gvt_hypervisor_read_gpa(vgpu,
+			(pd & PAGE_MASK) + (index <<

-:246: CHECK:LINE_SPACING: Please don't use multiple blank lines
#246: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2958:
+
+

-:248: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#248: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2960:
+static int walk_pdp_range(struct intel_vgpu *vgpu, u64 pdp,
+				  u64 start, u64 end, struct ppgtt_walk *walk)

-:260: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#260: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2972:
+		ret = intel_gvt_hypervisor_read_gpa(vgpu,
+			(pdp & PAGE_MASK) + (index <<

-:272: CHECK:LINE_SPACING: Please don't use multiple blank lines
#272: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2984:
+
+

-:274: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#274: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2986:
+static int walk_pml4_range(struct intel_vgpu *vgpu, u64 pml4,
+				u64 start, u64 end, struct ppgtt_walk *walk)

-:285: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#285: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2997:
+		ret = intel_gvt_hypervisor_read_gpa(vgpu,
+			(pml4 & PAGE_MASK) + (index <<

-:298: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#298: FILE: drivers/gpu/drm/i915/gvt/gtt.c:3010:
+int intel_vgpu_g2v_pv_ppgtt_insert_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[])

-:332: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#332: FILE: drivers/gpu/drm/i915/gvt/gtt.c:3044:
+	walk.mfns = kmalloc_array(num_pages,
+			sizeof(unsigned long), GFP_KERNEL);

-:392: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#392: FILE: drivers/gpu/drm/i915/gvt/gtt.h:277:
+int intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[]);

-:395: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#395: FILE: drivers/gpu/drm/i915/gvt/gtt.h:280:
+int intel_vgpu_g2v_pv_ppgtt_clear_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[]);

-:398: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#398: FILE: drivers/gpu/drm/i915/gvt/gtt.h:283:
+int intel_vgpu_g2v_pv_ppgtt_insert_4lvl(struct intel_vgpu *vgpu,
+		u64 pdps[]);

total: 0 errors, 0 warnings, 22 checks, 395 lines checked

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✗ Fi.CI.SPARSE: warning for series starting with [v1,01/10] drm/i915: introduced pv capability for vgpu

[Patchwork]

== Series Details ==

Series: series starting with [v1,01/10] drm/i915: introduced pv capability for vgpu
URL   : https://patchwork.freedesktop.org/series/50851/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: introduced pv capability for vgpu
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3725:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3732:16: warning: expression using sizeof(void)

Commit: drm/i915: get ready of memory for pvmmio
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3732:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3734:16: warning: expression using sizeof(void)

Commit: drm/i915: context submission pvmmio optimization
Okay!

Commit: drm/i915: master irq pvmmio optimization
Okay!

Commit: drm/i915: ppgtt update pvmmio optimization
-O:drivers/gpu/drm/i915/i915_gem_gtt.c:1442:9: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/i915_gem_gtt.c:1442:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_gem_gtt.c:1468:9: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_gem_gtt.c:1468:9: warning: expression using sizeof(void)

Commit: drm/i915/gvt: GVTg handle enable_pvmmio PVINFO register
Okay!

Commit: drm/i915/gvt: GVTg read_shared_page implementation
Okay!

Commit: drm/i915/gvt: GVTg support context submission pvmmio optimization
Okay!

Commit: drm/i915/gvt: GVTg support master irq pvmmio optimization
Okay!

Commit: drm/i915/gvt: GVTg support ppgtt pvmmio optimization
+./include/linux/slab.h:631:13: error: undefined identifier '__builtin_mul_overflow'
+./include/linux/slab.h:631:13: warning: call with no type!

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✓ Fi.CI.BAT: success for series starting with [v1,01/10] drm/i915: introduced pv capability for vgpu

[Patchwork]

== Series Details ==

Series: series starting with [v1,01/10] drm/i915: introduced pv capability for vgpu
URL   : https://patchwork.freedesktop.org/series/50851/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4968 -> Patchwork_10421 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/50851/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10421 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@amdgpu/amd_basic@cs-compute:
      fi-kbl-8809g:       NOTRUN -> FAIL (fdo#108094)

    igt@amdgpu/amd_prime@amd-to-i915:
      fi-kbl-8809g:       NOTRUN -> FAIL (fdo#107341)

    igt@kms_flip@basic-flip-vs-dpms:
      fi-bxt-dsi:         PASS -> INCOMPLETE (fdo#103927)

    igt@kms_frontbuffer_tracking@basic:
      fi-byt-clapper:     PASS -> FAIL (fdo#103167)

    
    ==== Possible fixes ====

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-cfl-8109u:       INCOMPLETE (fdo#106070, fdo#108126) -> PASS

    
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#106070 https://bugs.freedesktop.org/show_bug.cgi?id=106070
  fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341
  fdo#108094 https://bugs.freedesktop.org/show_bug.cgi?id=108094
  fdo#108126 https://bugs.freedesktop.org/show_bug.cgi?id=108126


== Participating hosts (45 -> 39) ==

  Missing    (6): fi-ilk-m540 fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-ctg-p8600 fi-byt-n2820 


== Build changes ==

    * Linux: CI_DRM_4968 -> Patchwork_10421

  CI_DRM_4968: 6c3870cc045403bc59ab66ea6ca4bad98114d0a4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4673: 54cb1aeb4e50dea9f3abae632e317875d147c4ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10421: 7ff85a910ce0b6f49fd98d45e3f53e3e0904f017 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

7ff85a910ce0 drm/i915/gvt: GVTg support ppgtt pvmmio optimization
4cb1532b4851 drm/i915/gvt: GVTg support master irq pvmmio optimization
4e2a15c60584 drm/i915/gvt: GVTg support context submission pvmmio optimization
3e9412478d43 drm/i915/gvt: GVTg read_shared_page implementation
657a3ae6fb1e drm/i915/gvt: GVTg handle enable_pvmmio PVINFO register
14033ac83189 drm/i915: ppgtt update pvmmio optimization
18b5f4aa055d drm/i915: master irq pvmmio optimization
1dde34d63842 drm/i915: context submission pvmmio optimization
317678bb037d drm/i915: get ready of memory for pvmmio
aeb1adffcb63 drm/i915: introduced pv capability for vgpu

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10421/issues.html
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Re: [v1 10/10] drm/i915/gvt: GVTg support ppgtt pvmmio optimization

[Zhao, Yakui]

On 2018年10月11日 14:14, Xiaolin Zhang wrote:
> This patch handles ppgtt update from g2v notification.
> 
> It read out ppgtt pte entries from guest pte tables page and
> convert them to host pfns.
> 
> It creates local ppgtt tables and insert the content pages
> into the local ppgtt tables directly, which does not track
> the usage of guest page table and removes the cost of write
> protection from the original shadow page mechansim.

It is possible that Guest VGPU writes the ppgtt entry by using 2M/64K 
page mode.

If so, the gvtg should also handle it in PVMMIO mode.

> 
> v1: rebase
> v0: RFC
> 
> Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
> ---
>   drivers/gpu/drm/i915/gvt/gtt.c      | 318 ++++++++++++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/gvt/gtt.h      |   9 +
>   drivers/gpu/drm/i915/gvt/handlers.c |  13 +-
>   3 files changed, 338 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> index 58e166e..8d3e21a 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.c
> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> @@ -1744,6 +1744,26 @@ static int ppgtt_handle_guest_write_page_table_bytes(
>   	return 0;
>   }
>   
> +static void invalidate_mm_pv(struct intel_vgpu_mm *mm)
> +{
> +	struct intel_vgpu *vgpu = mm->vgpu;
> +	struct intel_gvt *gvt = vgpu->gvt;
> +	struct intel_gvt_gtt *gtt = &gvt->gtt;
> +	struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
> +	struct intel_gvt_gtt_entry se;
> +
> +	i915_ppgtt_close(&mm->ppgtt->vm);
> +	i915_ppgtt_put(mm->ppgtt);
> +
> +	ppgtt_get_shadow_root_entry(mm, &se, 0);
> +	if (!ops->test_present(&se))
> +		return;
> +	se.val64 = 0;
> +	ppgtt_set_shadow_root_entry(mm, &se, 0);
> +
> +	mm->ppgtt_mm.shadowed  = false;
> +}
> +
>   static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
>   {
>   	struct intel_vgpu *vgpu = mm->vgpu;
> @@ -1756,6 +1776,11 @@ static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
>   	if (!mm->ppgtt_mm.shadowed)
>   		return;
>   
> +	if (VGPU_PVMMIO(mm->vgpu) & PVMMIO_PPGTT_UPDATE) {
> +		invalidate_mm_pv(mm);
> +		return;
> +	}
> +
>   	for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.shadow_pdps); index++) {
>   		ppgtt_get_shadow_root_entry(mm, &se, index);
>   
> @@ -1773,6 +1798,26 @@ static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
>   	mm->ppgtt_mm.shadowed = false;
>   }
>   
> +static int shadow_mm_pv(struct intel_vgpu_mm *mm)
> +{
> +	struct intel_vgpu *vgpu = mm->vgpu;
> +	struct intel_gvt *gvt = vgpu->gvt;
> +	struct intel_gvt_gtt_entry se;
> +
> +	mm->ppgtt = i915_ppgtt_create(gvt->dev_priv, NULL);
> +	if (IS_ERR(mm->ppgtt)) {
> +		gvt_vgpu_err("fail to create ppgtt for pdp 0x%llx\n",
> +				px_dma(&mm->ppgtt->pml4));
> +		return PTR_ERR(mm->ppgtt);
> +	}
> +
> +	se.type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
> +	se.val64 = px_dma(&mm->ppgtt->pml4);
> +	ppgtt_set_shadow_root_entry(mm, &se, 0);
> +	mm->ppgtt_mm.shadowed  = true;
> +
> +	return 0;
> +}
>   
>   static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm)
>   {
> @@ -1787,6 +1832,9 @@ static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm)
>   	if (mm->ppgtt_mm.shadowed)
>   		return 0;
>   
> +	if (VGPU_PVMMIO(mm->vgpu) & PVMMIO_PPGTT_UPDATE)
> +		return shadow_mm_pv(mm);
> +
>   	mm->ppgtt_mm.shadowed = true;
>   
>   	for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.guest_pdps); index++) {
> @@ -2767,3 +2815,273 @@ void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu)
>   	intel_vgpu_destroy_all_ppgtt_mm(vgpu);
>   	intel_vgpu_reset_ggtt(vgpu, true);
>   }
> +
> +int intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(struct intel_vgpu *vgpu,
> +		u64 pdps[])
> +{
> +	struct intel_vgpu_mm *mm;
> +	int ret = 0;
> +	u32 offset;
> +	struct pv_ppgtt_update pv_ppgtt;
> +
> +	offset = offsetof(struct gvt_shared_page, pv_ppgtt);
> +	intel_gvt_read_shared_page(vgpu, offset, &pv_ppgtt, sizeof(pv_ppgtt));
> +
> +	mm = intel_vgpu_find_ppgtt_mm(vgpu, &pv_ppgtt.pdp);
> +	if (!mm) {
> +		gvt_vgpu_err("failed to find pdp 0x%llx\n", pv_ppgtt.pdp);
> +		ret = -EINVAL;
> +	} else {
> +		ret = mm->ppgtt->vm.allocate_va_range(&mm->ppgtt->vm,
> +			pv_ppgtt.start, pv_ppgtt.length);
> +		if (ret)
> +			gvt_vgpu_err("failed to alloc %llx\n", pv_ppgtt.pdp);
> +	}
> +
> +	return ret;
> +}
> +
> +int intel_vgpu_g2v_pv_ppgtt_clear_4lvl(struct intel_vgpu *vgpu,
> +		u64 pdps[])
> +{
> +	struct intel_vgpu_mm *mm;
> +	int ret = 0;
> +	u32 offset;
> +	struct pv_ppgtt_update pv_ppgtt;
> +
> +	offset = offsetof(struct gvt_shared_page, pv_ppgtt);
> +	intel_gvt_read_shared_page(vgpu, offset, &pv_ppgtt, sizeof(pv_ppgtt));
> +	mm = intel_vgpu_find_ppgtt_mm(vgpu, &pv_ppgtt.pdp);
> +	if (!mm) {
> +		gvt_vgpu_err("failed to find pdp 0x%llx\n", pv_ppgtt.pdp);
> +		ret = -EINVAL;
> +	} else {
> +		mm->ppgtt->vm.clear_range(&mm->ppgtt->vm,
> +			pv_ppgtt.start, pv_ppgtt.length);
> +	}
> +
> +	return ret;
> +}
> +
> +#define GEN8_PML4E_SIZE		(1UL << GEN8_PML4E_SHIFT)
> +#define GEN8_PML4E_SIZE_MASK	(~(GEN8_PML4E_SIZE - 1))
> +#define GEN8_PDPE_SIZE		(1UL << GEN8_PDPE_SHIFT)
> +#define GEN8_PDPE_SIZE_MASK	(~(GEN8_PDPE_SIZE - 1))
> +#define GEN8_PDE_SIZE		(1UL << GEN8_PDE_SHIFT)
> +#define GEN8_PDE_SIZE_MASK	(~(GEN8_PDE_SIZE - 1))
> +
> +#define pml4_addr_end(addr, end)					\
> +({	unsigned long __boundary = \
> +			((addr) + GEN8_PML4E_SIZE) & GEN8_PML4E_SIZE_MASK; \
> +	(__boundary < (end)) ? __boundary : (end);		\
> +})
> +
> +#define pdp_addr_end(addr, end)						\
> +({	unsigned long __boundary = \
> +			((addr) + GEN8_PDPE_SIZE) & GEN8_PDPE_SIZE_MASK; \
> +	(__boundary < (end)) ? __boundary : (end);		\
> +})
> +
> +#define pd_addr_end(addr, end)						\
> +({	unsigned long __boundary = \
> +			((addr) + GEN8_PDE_SIZE) & GEN8_PDE_SIZE_MASK;	\
> +	(__boundary < (end)) ? __boundary : (end);		\
> +})
> +
> +struct ppgtt_walk {
> +	unsigned long *mfns;
> +	int mfn_index;
> +	unsigned long *pt;
> +};
> +
> +static int walk_pt_range(struct intel_vgpu *vgpu, u64 pt,
> +				u64 start, u64 end, struct ppgtt_walk *walk)
> +{
> +	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
> +	struct intel_gvt_gtt_gma_ops *gma_ops = vgpu->gvt->gtt.gma_ops;
> +	unsigned long start_index, end_index;
> +	int ret;
> +	int i;
> +	unsigned long mfn, gfn;
> +
> +	start_index = gma_ops->gma_to_pte_index(start);
> +	end_index = ((end - start) >> PAGE_SHIFT) + start_index;
> +
> +	ret = intel_gvt_hypervisor_read_gpa(vgpu,
> +		(pt & PAGE_MASK) + (start_index << info->gtt_entry_size_shift),
> +		walk->pt + start_index,
> +		(end_index - start_index) << info->gtt_entry_size_shift);
> +	if (ret) {
> +		gvt_vgpu_err("fail to read gpa %llx\n", pt);
> +		return ret;
> +	}
> +
> +	for (i = start_index; i < end_index; i++) {
> +		gfn = walk->pt[i] >> PAGE_SHIFT;
> +		mfn = intel_gvt_hypervisor_gfn_to_mfn(vgpu, gfn);
> +		if (mfn == INTEL_GVT_INVALID_ADDR) {
> +			gvt_vgpu_err("fail to translate gfn: 0x%lx\n", gfn);
> +			return -ENXIO;
> +		}
> +		walk->mfns[walk->mfn_index++] = mfn << PAGE_SHIFT;
> +	}
> +
> +	return 0;
> +}
> +
> +
> +static int walk_pd_range(struct intel_vgpu *vgpu, u64 pd,
> +				u64 start, u64 end, struct ppgtt_walk *walk)
> +{
> +	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
> +	struct intel_gvt_gtt_gma_ops *gma_ops = vgpu->gvt->gtt.gma_ops;
> +	unsigned long index;
> +	u64 pt, next;
> +	int ret  = 0;
> +
> +	do {
> +		index = gma_ops->gma_to_pde_index(start);
> +
> +		ret = intel_gvt_hypervisor_read_gpa(vgpu,
> +			(pd & PAGE_MASK) + (index <<
> +			info->gtt_entry_size_shift), &pt, 8);
> +		if (ret)
> +			return ret;
> +		next = pd_addr_end(start, end);
> +		walk_pt_range(vgpu, pt, start, next, walk);
> +
> +		start = next;
> +	} while (start != end);
> +
> +	return ret;
> +}
> +
> +
> +static int walk_pdp_range(struct intel_vgpu *vgpu, u64 pdp,
> +				  u64 start, u64 end, struct ppgtt_walk *walk)
> +{
> +	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
> +	struct intel_gvt_gtt_gma_ops *gma_ops = vgpu->gvt->gtt.gma_ops;
> +	unsigned long index;
> +	u64 pd, next;
> +	int ret  = 0;
> +
> +	do {
> +		index = gma_ops->gma_to_l4_pdp_index(start);
> +
> +		ret = intel_gvt_hypervisor_read_gpa(vgpu,
> +			(pdp & PAGE_MASK) + (index <<
> +			info->gtt_entry_size_shift), &pd, 8);
> +		if (ret)
> +			return ret;
> +		next = pdp_addr_end(start, end);
> +		walk_pd_range(vgpu, pd, start, next, walk);
> +		start = next;
> +	} while (start != end);
> +
> +	return ret;
> +}
> +
> +
> +static int walk_pml4_range(struct intel_vgpu *vgpu, u64 pml4,
> +				u64 start, u64 end, struct ppgtt_walk *walk)
> +{
> +	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
> +	struct intel_gvt_gtt_gma_ops *gma_ops = vgpu->gvt->gtt.gma_ops;
> +	unsigned long index;
> +	u64 pdp, next;
> +	int ret  = 0;
> +
> +	do {
> +		index = gma_ops->gma_to_pml4_index(start);
> +		ret = intel_gvt_hypervisor_read_gpa(vgpu,
> +			(pml4 & PAGE_MASK) + (index <<
> +			info->gtt_entry_size_shift), &pdp, 8);
> +		if (ret)
> +			return ret;
> +		next = pml4_addr_end(start, end);
> +		walk_pdp_range(vgpu, pdp, start, next, walk);
> +		start = next;
> +	} while (start != end);
> +
> +	return ret;
> +}
> +
> +int intel_vgpu_g2v_pv_ppgtt_insert_4lvl(struct intel_vgpu *vgpu,
> +		u64 pdps[])
> +{
> +	struct intel_vgpu_mm *mm;
> +	u64 pml4, start, length;
> +	u32 cache_level;
> +	int ret = 0;
> +	struct sg_table st;
> +	struct scatterlist *sg = NULL;
> +	int num_pages;
> +	struct i915_vma vma;
> +	struct ppgtt_walk walk;
> +	int i;
> +	u32 offset;
> +	struct pv_ppgtt_update pv_ppgtt;
> +
> +	offset = offsetof(struct gvt_shared_page, pv_ppgtt);
> +	intel_gvt_read_shared_page(vgpu, offset, &pv_ppgtt, sizeof(pv_ppgtt));
> +	pml4 = pv_ppgtt.pdp;
> +	start = pv_ppgtt.start;
> +	length = pv_ppgtt.length;
> +	cache_level = pv_ppgtt.cache_level;
> +	num_pages = length >> PAGE_SHIFT;
> +
> +	mm = intel_vgpu_find_ppgtt_mm(vgpu, &pml4);
> +	if (!mm) {
> +		gvt_vgpu_err("fail to find mm for pml4 0x%llx\n", pml4);
> +		return -EINVAL;
> +	}
> +
> +	walk.mfn_index = 0;
> +	walk.mfns = NULL;
> +	walk.pt = NULL;
> +
> +	walk.mfns = kmalloc_array(num_pages,
> +			sizeof(unsigned long), GFP_KERNEL);
> +	if (!walk.mfns) {
> +		ret = -ENOMEM;
> +		goto fail;
> +	}
> +
> +	walk.pt = (unsigned long *)__get_free_pages(GFP_KERNEL, 0);
> +	if (!walk.pt) {
> +		ret = -ENOMEM;
> +		goto fail;
> +	}
> +
> +	if (sg_alloc_table(&st, num_pages, GFP_KERNEL)) {
> +		ret = -ENOMEM;
> +		goto fail;
> +	}
> +
> +	ret = walk_pml4_range(vgpu, pml4, start, start + length, &walk);
> +	if (ret)
> +		goto fail_free_sg;
> +
> +	WARN_ON(num_pages != walk.mfn_index);
> +
> +	for_each_sg(st.sgl, sg, num_pages, i) {
> +		sg->offset = 0;
> +		sg->length = PAGE_SIZE;
> +		sg_dma_address(sg) = walk.mfns[i];
> +		sg_dma_len(sg) = PAGE_SIZE;
> +	}
> +
> +	memset(&vma, 0, sizeof(vma));
> +	vma.node.start = start;
> +	vma.pages = &st;
> +	mm->ppgtt->vm.insert_entries(&mm->ppgtt->vm, &vma, cache_level, 0);
> +
> +fail_free_sg:
> +	sg_free_table(&st);
> +fail:
> +	kfree(walk.mfns);
> +	free_page((unsigned long)walk.pt);
> +
> +	return ret;
> +}
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
> index a11bfee..4edaed9 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.h
> +++ b/drivers/gpu/drm/i915/gvt/gtt.h
> @@ -141,6 +141,7 @@ struct intel_gvt_partial_pte {
>   
>   struct intel_vgpu_mm {
>   	enum intel_gvt_mm_type type;
> +	struct i915_hw_ppgtt *ppgtt;
>   	struct intel_vgpu *vgpu;
>   
>   	struct kref ref;
> @@ -277,4 +278,12 @@ int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu,
>   int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
>   	unsigned int off, void *p_data, unsigned int bytes);
>   
> +int intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(struct intel_vgpu *vgpu,
> +		u64 pdps[]);
> +
> +int intel_vgpu_g2v_pv_ppgtt_clear_4lvl(struct intel_vgpu *vgpu,
> +		u64 pdps[]);
> +
> +int intel_vgpu_g2v_pv_ppgtt_insert_4lvl(struct intel_vgpu *vgpu,
> +		u64 pdps[]);
>   #endif /* _GVT_GTT_H_ */
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 7a53011..1ae21cb 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -1186,7 +1186,7 @@ static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
>   	intel_gvt_gtt_type_t root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
>   	struct intel_vgpu_mm *mm;
>   	u64 *pdps;
> -
> +	int ret = 0;
>   	pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
>   
>   	switch (notification) {
> @@ -1199,6 +1199,15 @@ static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
>   	case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
>   	case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
>   		return intel_vgpu_put_ppgtt_mm(vgpu, pdps);
> +	case VGT_G2V_PPGTT_L4_ALLOC:
> +		ret = intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(vgpu, pdps);
> +			break;
> +	case VGT_G2V_PPGTT_L4_INSERT:
> +		ret = intel_vgpu_g2v_pv_ppgtt_insert_4lvl(vgpu, pdps);
> +		break;
> +	case VGT_G2V_PPGTT_L4_CLEAR:
> +		ret = intel_vgpu_g2v_pv_ppgtt_clear_4lvl(vgpu, pdps);
> +		break;
>   	case VGT_G2V_EXECLIST_CONTEXT_CREATE:
>   	case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
>   	case 1:	/* Remove this in guest driver. */
> @@ -1206,7 +1215,7 @@ static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
>   	default:
>   		gvt_vgpu_err("Invalid PV notification %d\n", notification);
>   	}
> -	return 0;
> +	return ret;
>   }
>   
>   static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
> 
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Re: [v1 03/10] drm/i915: context submission pvmmio optimization

[Chris Wilson]

Quoting Xiaolin Zhang (2018-10-11 07:14:05)
> It is performance optimization to reduce mmio trap numbers from 4 to
> 1 durning ELSP porting writing (context submission).
> 
> When context subission, to cache elsp_data[4] values in
> the shared page, the last elsp_data[0] port writing will be trapped
> to gvt for real context submission.
> 
> Use PVMMIO_ELSP_SUBMIT to control this level of pvmmio optimization.
> 
> v1: rebase
> v0: RFC
> 
> Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_vgpu.c |  2 ++
>  drivers/gpu/drm/i915/intel_lrc.c | 37 ++++++++++++++++++++++++++++++++++++-

Hint: intel_vgpu_submission.c and go wild. You do not need to emulate
execlists at all, an async interface along the lines of guc would
strangely enough be more akin to what you want.
-Chris
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✓ Fi.CI.IGT: success for series starting with [v1,01/10] drm/i915: introduced pv capability for vgpu

[Patchwork]

== Series Details ==

Series: series starting with [v1,01/10] drm/i915: introduced pv capability for vgpu
URL   : https://patchwork.freedesktop.org/series/50851/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4968_full -> Patchwork_10421_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_10421_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@core_prop_blob@invalid-get-prop-any:
      shard-snb:          NOTRUN -> INCOMPLETE (fdo#105411)

    igt@gem_exec_schedule@pi-ringfull-bsd:
      shard-skl:          NOTRUN -> FAIL (fdo#103158) +2

    igt@kms_addfb_basic@bo-too-small-due-to-tiling:
      shard-snb:          NOTRUN -> DMESG-WARN (fdo#107469) +3

    igt@kms_atomic_transition@2x-modeset-transitions-nonblocking-fencing:
      shard-glk:          NOTRUN -> INCOMPLETE (fdo#103359, k.org#198133)

    igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
      shard-skl:          NOTRUN -> DMESG-WARN (fdo#107956)

    igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
      shard-snb:          NOTRUN -> DMESG-WARN (fdo#107956) +1

    igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
      shard-glk:          PASS -> DMESG-WARN (fdo#106538, fdo#105763)

    igt@kms_flip@plain-flip-fb-recreate:
      shard-kbl:          PASS -> FAIL (fdo#100368)

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
      shard-glk:          PASS -> FAIL (fdo#103167)

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
      shard-apl:          PASS -> FAIL (fdo#103167) +1

    igt@kms_pipe_crc_basic@read-crc-pipe-c:
      shard-skl:          NOTRUN -> FAIL (fdo#107362) +1

    igt@kms_plane@pixel-format-pipe-c-planes:
      shard-skl:          NOTRUN -> DMESG-FAIL (fdo#103166, fdo#106885)

    igt@kms_plane@plane-position-covered-pipe-c-planes:
      shard-apl:          PASS -> FAIL (fdo#103166) +2

    {igt@kms_plane_alpha_blend@pipe-a-alpha-7efc}:
      shard-skl:          NOTRUN -> FAIL (fdo#108145) +3

    {igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb}:
      shard-kbl:          NOTRUN -> FAIL (fdo#108145)

    {igt@kms_plane_alpha_blend@pipe-c-alpha-7efc}:
      shard-skl:          NOTRUN -> FAIL (fdo#108146)

    {igt@kms_plane_alpha_blend@pipe-c-coverage-7efc}:
      shard-apl:          NOTRUN -> FAIL (fdo#108146)

    igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
      shard-skl:          NOTRUN -> FAIL (fdo#103166)

    igt@kms_sysfs_edid_timing:
      shard-skl:          NOTRUN -> FAIL (fdo#100047)

    
    ==== Possible fixes ====

    igt@drv_hangman@error-state-capture-render:
      shard-glk:          INCOMPLETE (fdo#103359, k.org#198133) -> PASS

    igt@gem_userptr_blits@readonly-unsync:
      shard-kbl:          INCOMPLETE (fdo#103665) -> PASS

    igt@kms_cursor_crc@cursor-64x64-dpms:
      shard-apl:          FAIL (fdo#103232) -> PASS

    igt@kms_flip@flip-vs-expired-vblank:
      shard-kbl:          FAIL (fdo#102887, fdo#105363) -> PASS

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
      shard-apl:          FAIL (fdo#103167) -> PASS +3

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite:
      shard-glk:          FAIL (fdo#103167) -> PASS +3

    igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
      shard-skl:          INCOMPLETE (fdo#107773, fdo#104108) -> PASS +1

    igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
      shard-apl:          FAIL (fdo#103166) -> PASS +2

    igt@perf_pmu@rc6-runtime-pm:
      shard-apl:          FAIL (fdo#105010) -> PASS

    
    ==== Warnings ====

    igt@kms_busy@extended-modeset-hang-newfb-render-b:
      shard-apl:          INCOMPLETE (fdo#103927) -> DMESG-WARN (fdo#107956)

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
  fdo#105010 https://bugs.freedesktop.org/show_bug.cgi?id=105010
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
  fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
  fdo#106885 https://bugs.freedesktop.org/show_bug.cgi?id=106885
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107469 https://bugs.freedesktop.org/show_bug.cgi?id=107469
  fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
  fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
  fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
  fdo#108146 https://bugs.freedesktop.org/show_bug.cgi?id=108146
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4968 -> Patchwork_10421

  CI_DRM_4968: 6c3870cc045403bc59ab66ea6ca4bad98114d0a4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4673: 54cb1aeb4e50dea9f3abae632e317875d147c4ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10421: 7ff85a910ce0b6f49fd98d45e3f53e3e0904f017 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10421/shards.html
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Re: [v1 03/10] drm/i915: context submission pvmmio optimization

[Zhang, Xiaolin]

On 10/11/2018 05:12 PM, Chris Wilson wrote:
> Quoting Xiaolin Zhang (2018-10-11 07:14:05)
>> It is performance optimization to reduce mmio trap numbers from 4 to
>> 1 durning ELSP porting writing (context submission).
>>
>> When context subission, to cache elsp_data[4] values in
>> the shared page, the last elsp_data[0] port writing will be trapped
>> to gvt for real context submission.
>>
>> Use PVMMIO_ELSP_SUBMIT to control this level of pvmmio optimization.
>>
>> v1: rebase
>> v0: RFC
>>
>> Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_vgpu.c |  2 ++
>>  drivers/gpu/drm/i915/intel_lrc.c | 37 ++++++++++++++++++++++++++++++++++++-
> Hint: intel_vgpu_submission.c and go wild. You do not need to emulate
> execlists at all, an async interface along the lines of guc would
> strangely enough be more akin to what you want.
> -Chris
>
can't understand your comment very well. so far, vgpu only support
execlist workload submission only, this pv optimization is only valid
for execlist submission and can't support guc.

BRs, Xiaolin

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Re: [v1 10/10] drm/i915/gvt: GVTg support ppgtt pvmmio optimization

[Zhang, Xiaolin]

On 10/11/2018 04:07 PM, Zhao, Yakui wrote:
>
> On 2018年10月11日 14:14, Xiaolin Zhang wrote:
>> This patch handles ppgtt update from g2v notification.
>>
>> It read out ppgtt pte entries from guest pte tables page and
>> convert them to host pfns.
>>
>> It creates local ppgtt tables and insert the content pages
>> into the local ppgtt tables directly, which does not track
>> the usage of guest page table and removes the cost of write
>> protection from the original shadow page mechansim.
> It is possible that Guest VGPU writes the ppgtt entry by using 2M/64K 
> page mode.
>
> If so, the gvtg should also handle it in PVMMIO mode.
it is possible that guest vgpu can support huge page mode. currently it
is a gap for pvppgtt since this feature is only valid for non-huge-page
mode.  it is WIP to support guest huge page mode.
BRs, Xiaolin
>> v1: rebase
>> v0: RFC
>>
>> Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
>> ---
>>   drivers/gpu/drm/i915/gvt/gtt.c      | 318 ++++++++++++++++++++++++++++++++++++
>>   drivers/gpu/drm/i915/gvt/gtt.h      |   9 +
>>   drivers/gpu/drm/i915/gvt/handlers.c |  13 +-
>>   3 files changed, 338 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
>> index 58e166e..8d3e21a 100644
>> --- a/drivers/gpu/drm/i915/gvt/gtt.c
>> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
>> @@ -1744,6 +1744,26 @@ static int ppgtt_handle_guest_write_page_table_bytes(
>>   	return 0;
>>   }
>>   
>> +static void invalidate_mm_pv(struct intel_vgpu_mm *mm)
>> +{
>> +	struct intel_vgpu *vgpu = mm->vgpu;
>> +	struct intel_gvt *gvt = vgpu->gvt;
>> +	struct intel_gvt_gtt *gtt = &gvt->gtt;
>> +	struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
>> +	struct intel_gvt_gtt_entry se;
>> +
>> +	i915_ppgtt_close(&mm->ppgtt->vm);
>> +	i915_ppgtt_put(mm->ppgtt);
>> +
>> +	ppgtt_get_shadow_root_entry(mm, &se, 0);
>> +	if (!ops->test_present(&se))
>> +		return;
>> +	se.val64 = 0;
>> +	ppgtt_set_shadow_root_entry(mm, &se, 0);
>> +
>> +	mm->ppgtt_mm.shadowed  = false;
>> +}
>> +
>>   static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
>>   {
>>   	struct intel_vgpu *vgpu = mm->vgpu;
>> @@ -1756,6 +1776,11 @@ static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
>>   	if (!mm->ppgtt_mm.shadowed)
>>   		return;
>>   
>> +	if (VGPU_PVMMIO(mm->vgpu) & PVMMIO_PPGTT_UPDATE) {
>> +		invalidate_mm_pv(mm);
>> +		return;
>> +	}
>> +
>>   	for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.shadow_pdps); index++) {
>>   		ppgtt_get_shadow_root_entry(mm, &se, index);
>>   
>> @@ -1773,6 +1798,26 @@ static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
>>   	mm->ppgtt_mm.shadowed = false;
>>   }
>>   
>> +static int shadow_mm_pv(struct intel_vgpu_mm *mm)
>> +{
>> +	struct intel_vgpu *vgpu = mm->vgpu;
>> +	struct intel_gvt *gvt = vgpu->gvt;
>> +	struct intel_gvt_gtt_entry se;
>> +
>> +	mm->ppgtt = i915_ppgtt_create(gvt->dev_priv, NULL);
>> +	if (IS_ERR(mm->ppgtt)) {
>> +		gvt_vgpu_err("fail to create ppgtt for pdp 0x%llx\n",
>> +				px_dma(&mm->ppgtt->pml4));
>> +		return PTR_ERR(mm->ppgtt);
>> +	}
>> +
>> +	se.type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
>> +	se.val64 = px_dma(&mm->ppgtt->pml4);
>> +	ppgtt_set_shadow_root_entry(mm, &se, 0);
>> +	mm->ppgtt_mm.shadowed  = true;
>> +
>> +	return 0;
>> +}
>>   
>>   static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm)
>>   {
>> @@ -1787,6 +1832,9 @@ static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm)
>>   	if (mm->ppgtt_mm.shadowed)
>>   		return 0;
>>   
>> +	if (VGPU_PVMMIO(mm->vgpu) & PVMMIO_PPGTT_UPDATE)
>> +		return shadow_mm_pv(mm);
>> +
>>   	mm->ppgtt_mm.shadowed = true;
>>   
>>   	for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.guest_pdps); index++) {
>> @@ -2767,3 +2815,273 @@ void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu)
>>   	intel_vgpu_destroy_all_ppgtt_mm(vgpu);
>>   	intel_vgpu_reset_ggtt(vgpu, true);
>>   }
>> +
>> +int intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(struct intel_vgpu *vgpu,
>> +		u64 pdps[])
>> +{
>> +	struct intel_vgpu_mm *mm;
>> +	int ret = 0;
>> +	u32 offset;
>> +	struct pv_ppgtt_update pv_ppgtt;
>> +
>> +	offset = offsetof(struct gvt_shared_page, pv_ppgtt);
>> +	intel_gvt_read_shared_page(vgpu, offset, &pv_ppgtt, sizeof(pv_ppgtt));
>> +
>> +	mm = intel_vgpu_find_ppgtt_mm(vgpu, &pv_ppgtt.pdp);
>> +	if (!mm) {
>> +		gvt_vgpu_err("failed to find pdp 0x%llx\n", pv_ppgtt.pdp);
>> +		ret = -EINVAL;
>> +	} else {
>> +		ret = mm->ppgtt->vm.allocate_va_range(&mm->ppgtt->vm,
>> +			pv_ppgtt.start, pv_ppgtt.length);
>> +		if (ret)
>> +			gvt_vgpu_err("failed to alloc %llx\n", pv_ppgtt.pdp);
>> +	}
>> +
>> +	return ret;
>> +}
>> +
>> +int intel_vgpu_g2v_pv_ppgtt_clear_4lvl(struct intel_vgpu *vgpu,
>> +		u64 pdps[])
>> +{
>> +	struct intel_vgpu_mm *mm;
>> +	int ret = 0;
>> +	u32 offset;
>> +	struct pv_ppgtt_update pv_ppgtt;
>> +
>> +	offset = offsetof(struct gvt_shared_page, pv_ppgtt);
>> +	intel_gvt_read_shared_page(vgpu, offset, &pv_ppgtt, sizeof(pv_ppgtt));
>> +	mm = intel_vgpu_find_ppgtt_mm(vgpu, &pv_ppgtt.pdp);
>> +	if (!mm) {
>> +		gvt_vgpu_err("failed to find pdp 0x%llx\n", pv_ppgtt.pdp);
>> +		ret = -EINVAL;
>> +	} else {
>> +		mm->ppgtt->vm.clear_range(&mm->ppgtt->vm,
>> +			pv_ppgtt.start, pv_ppgtt.length);
>> +	}
>> +
>> +	return ret;
>> +}
>> +
>> +#define GEN8_PML4E_SIZE		(1UL << GEN8_PML4E_SHIFT)
>> +#define GEN8_PML4E_SIZE_MASK	(~(GEN8_PML4E_SIZE - 1))
>> +#define GEN8_PDPE_SIZE		(1UL << GEN8_PDPE_SHIFT)
>> +#define GEN8_PDPE_SIZE_MASK	(~(GEN8_PDPE_SIZE - 1))
>> +#define GEN8_PDE_SIZE		(1UL << GEN8_PDE_SHIFT)
>> +#define GEN8_PDE_SIZE_MASK	(~(GEN8_PDE_SIZE - 1))
>> +
>> +#define pml4_addr_end(addr, end)					\
>> +({	unsigned long __boundary = \
>> +			((addr) + GEN8_PML4E_SIZE) & GEN8_PML4E_SIZE_MASK; \
>> +	(__boundary < (end)) ? __boundary : (end);		\
>> +})
>> +
>> +#define pdp_addr_end(addr, end)						\
>> +({	unsigned long __boundary = \
>> +			((addr) + GEN8_PDPE_SIZE) & GEN8_PDPE_SIZE_MASK; \
>> +	(__boundary < (end)) ? __boundary : (end);		\
>> +})
>> +
>> +#define pd_addr_end(addr, end)						\
>> +({	unsigned long __boundary = \
>> +			((addr) + GEN8_PDE_SIZE) & GEN8_PDE_SIZE_MASK;	\
>> +	(__boundary < (end)) ? __boundary : (end);		\
>> +})
>> +
>> +struct ppgtt_walk {
>> +	unsigned long *mfns;
>> +	int mfn_index;
>> +	unsigned long *pt;
>> +};
>> +
>> +static int walk_pt_range(struct intel_vgpu *vgpu, u64 pt,
>> +				u64 start, u64 end, struct ppgtt_walk *walk)
>> +{
>> +	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
>> +	struct intel_gvt_gtt_gma_ops *gma_ops = vgpu->gvt->gtt.gma_ops;
>> +	unsigned long start_index, end_index;
>> +	int ret;
>> +	int i;
>> +	unsigned long mfn, gfn;
>> +
>> +	start_index = gma_ops->gma_to_pte_index(start);
>> +	end_index = ((end - start) >> PAGE_SHIFT) + start_index;
>> +
>> +	ret = intel_gvt_hypervisor_read_gpa(vgpu,
>> +		(pt & PAGE_MASK) + (start_index << info->gtt_entry_size_shift),
>> +		walk->pt + start_index,
>> +		(end_index - start_index) << info->gtt_entry_size_shift);
>> +	if (ret) {
>> +		gvt_vgpu_err("fail to read gpa %llx\n", pt);
>> +		return ret;
>> +	}
>> +
>> +	for (i = start_index; i < end_index; i++) {
>> +		gfn = walk->pt[i] >> PAGE_SHIFT;
>> +		mfn = intel_gvt_hypervisor_gfn_to_mfn(vgpu, gfn);
>> +		if (mfn == INTEL_GVT_INVALID_ADDR) {
>> +			gvt_vgpu_err("fail to translate gfn: 0x%lx\n", gfn);
>> +			return -ENXIO;
>> +		}
>> +		walk->mfns[walk->mfn_index++] = mfn << PAGE_SHIFT;
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +
>> +static int walk_pd_range(struct intel_vgpu *vgpu, u64 pd,
>> +				u64 start, u64 end, struct ppgtt_walk *walk)
>> +{
>> +	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
>> +	struct intel_gvt_gtt_gma_ops *gma_ops = vgpu->gvt->gtt.gma_ops;
>> +	unsigned long index;
>> +	u64 pt, next;
>> +	int ret  = 0;
>> +
>> +	do {
>> +		index = gma_ops->gma_to_pde_index(start);
>> +
>> +		ret = intel_gvt_hypervisor_read_gpa(vgpu,
>> +			(pd & PAGE_MASK) + (index <<
>> +			info->gtt_entry_size_shift), &pt, 8);
>> +		if (ret)
>> +			return ret;
>> +		next = pd_addr_end(start, end);
>> +		walk_pt_range(vgpu, pt, start, next, walk);
>> +
>> +		start = next;
>> +	} while (start != end);
>> +
>> +	return ret;
>> +}
>> +
>> +
>> +static int walk_pdp_range(struct intel_vgpu *vgpu, u64 pdp,
>> +				  u64 start, u64 end, struct ppgtt_walk *walk)
>> +{
>> +	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
>> +	struct intel_gvt_gtt_gma_ops *gma_ops = vgpu->gvt->gtt.gma_ops;
>> +	unsigned long index;
>> +	u64 pd, next;
>> +	int ret  = 0;
>> +
>> +	do {
>> +		index = gma_ops->gma_to_l4_pdp_index(start);
>> +
>> +		ret = intel_gvt_hypervisor_read_gpa(vgpu,
>> +			(pdp & PAGE_MASK) + (index <<
>> +			info->gtt_entry_size_shift), &pd, 8);
>> +		if (ret)
>> +			return ret;
>> +		next = pdp_addr_end(start, end);
>> +		walk_pd_range(vgpu, pd, start, next, walk);
>> +		start = next;
>> +	} while (start != end);
>> +
>> +	return ret;
>> +}
>> +
>> +
>> +static int walk_pml4_range(struct intel_vgpu *vgpu, u64 pml4,
>> +				u64 start, u64 end, struct ppgtt_walk *walk)
>> +{
>> +	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
>> +	struct intel_gvt_gtt_gma_ops *gma_ops = vgpu->gvt->gtt.gma_ops;
>> +	unsigned long index;
>> +	u64 pdp, next;
>> +	int ret  = 0;
>> +
>> +	do {
>> +		index = gma_ops->gma_to_pml4_index(start);
>> +		ret = intel_gvt_hypervisor_read_gpa(vgpu,
>> +			(pml4 & PAGE_MASK) + (index <<
>> +			info->gtt_entry_size_shift), &pdp, 8);
>> +		if (ret)
>> +			return ret;
>> +		next = pml4_addr_end(start, end);
>> +		walk_pdp_range(vgpu, pdp, start, next, walk);
>> +		start = next;
>> +	} while (start != end);
>> +
>> +	return ret;
>> +}
>> +
>> +int intel_vgpu_g2v_pv_ppgtt_insert_4lvl(struct intel_vgpu *vgpu,
>> +		u64 pdps[])
>> +{
>> +	struct intel_vgpu_mm *mm;
>> +	u64 pml4, start, length;
>> +	u32 cache_level;
>> +	int ret = 0;
>> +	struct sg_table st;
>> +	struct scatterlist *sg = NULL;
>> +	int num_pages;
>> +	struct i915_vma vma;
>> +	struct ppgtt_walk walk;
>> +	int i;
>> +	u32 offset;
>> +	struct pv_ppgtt_update pv_ppgtt;
>> +
>> +	offset = offsetof(struct gvt_shared_page, pv_ppgtt);
>> +	intel_gvt_read_shared_page(vgpu, offset, &pv_ppgtt, sizeof(pv_ppgtt));
>> +	pml4 = pv_ppgtt.pdp;
>> +	start = pv_ppgtt.start;
>> +	length = pv_ppgtt.length;
>> +	cache_level = pv_ppgtt.cache_level;
>> +	num_pages = length >> PAGE_SHIFT;
>> +
>> +	mm = intel_vgpu_find_ppgtt_mm(vgpu, &pml4);
>> +	if (!mm) {
>> +		gvt_vgpu_err("fail to find mm for pml4 0x%llx\n", pml4);
>> +		return -EINVAL;
>> +	}
>> +
>> +	walk.mfn_index = 0;
>> +	walk.mfns = NULL;
>> +	walk.pt = NULL;
>> +
>> +	walk.mfns = kmalloc_array(num_pages,
>> +			sizeof(unsigned long), GFP_KERNEL);
>> +	if (!walk.mfns) {
>> +		ret = -ENOMEM;
>> +		goto fail;
>> +	}
>> +
>> +	walk.pt = (unsigned long *)__get_free_pages(GFP_KERNEL, 0);
>> +	if (!walk.pt) {
>> +		ret = -ENOMEM;
>> +		goto fail;
>> +	}
>> +
>> +	if (sg_alloc_table(&st, num_pages, GFP_KERNEL)) {
>> +		ret = -ENOMEM;
>> +		goto fail;
>> +	}
>> +
>> +	ret = walk_pml4_range(vgpu, pml4, start, start + length, &walk);
>> +	if (ret)
>> +		goto fail_free_sg;
>> +
>> +	WARN_ON(num_pages != walk.mfn_index);
>> +
>> +	for_each_sg(st.sgl, sg, num_pages, i) {
>> +		sg->offset = 0;
>> +		sg->length = PAGE_SIZE;
>> +		sg_dma_address(sg) = walk.mfns[i];
>> +		sg_dma_len(sg) = PAGE_SIZE;
>> +	}
>> +
>> +	memset(&vma, 0, sizeof(vma));
>> +	vma.node.start = start;
>> +	vma.pages = &st;
>> +	mm->ppgtt->vm.insert_entries(&mm->ppgtt->vm, &vma, cache_level, 0);
>> +
>> +fail_free_sg:
>> +	sg_free_table(&st);
>> +fail:
>> +	kfree(walk.mfns);
>> +	free_page((unsigned long)walk.pt);
>> +
>> +	return ret;
>> +}
>> diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
>> index a11bfee..4edaed9 100644
>> --- a/drivers/gpu/drm/i915/gvt/gtt.h
>> +++ b/drivers/gpu/drm/i915/gvt/gtt.h
>> @@ -141,6 +141,7 @@ struct intel_gvt_partial_pte {
>>   
>>   struct intel_vgpu_mm {
>>   	enum intel_gvt_mm_type type;
>> +	struct i915_hw_ppgtt *ppgtt;
>>   	struct intel_vgpu *vgpu;
>>   
>>   	struct kref ref;
>> @@ -277,4 +278,12 @@ int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu,
>>   int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
>>   	unsigned int off, void *p_data, unsigned int bytes);
>>   
>> +int intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(struct intel_vgpu *vgpu,
>> +		u64 pdps[]);
>> +
>> +int intel_vgpu_g2v_pv_ppgtt_clear_4lvl(struct intel_vgpu *vgpu,
>> +		u64 pdps[]);
>> +
>> +int intel_vgpu_g2v_pv_ppgtt_insert_4lvl(struct intel_vgpu *vgpu,
>> +		u64 pdps[]);
>>   #endif /* _GVT_GTT_H_ */
>> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
>> index 7a53011..1ae21cb 100644
>> --- a/drivers/gpu/drm/i915/gvt/handlers.c
>> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
>> @@ -1186,7 +1186,7 @@ static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
>>   	intel_gvt_gtt_type_t root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
>>   	struct intel_vgpu_mm *mm;
>>   	u64 *pdps;
>> -
>> +	int ret = 0;
>>   	pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
>>   
>>   	switch (notification) {
>> @@ -1199,6 +1199,15 @@ static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
>>   	case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
>>   	case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
>>   		return intel_vgpu_put_ppgtt_mm(vgpu, pdps);
>> +	case VGT_G2V_PPGTT_L4_ALLOC:
>> +		ret = intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(vgpu, pdps);
>> +			break;
>> +	case VGT_G2V_PPGTT_L4_INSERT:
>> +		ret = intel_vgpu_g2v_pv_ppgtt_insert_4lvl(vgpu, pdps);
>> +		break;
>> +	case VGT_G2V_PPGTT_L4_CLEAR:
>> +		ret = intel_vgpu_g2v_pv_ppgtt_clear_4lvl(vgpu, pdps);
>> +		break;
>>   	case VGT_G2V_EXECLIST_CONTEXT_CREATE:
>>   	case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
>>   	case 1:	/* Remove this in guest driver. */
>> @@ -1206,7 +1215,7 @@ static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
>>   	default:
>>   		gvt_vgpu_err("Invalid PV notification %d\n", notification);
>>   	}
>> -	return 0;
>> +	return ret;
>>   }
>>   
>>   static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
>>

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