From: Chris Wilson <chris@chris-wilson.co.uk>
To: Xiaolin Zhang <xiaolin.zhang@intel.com>,
intel-gfx@lists.freedesktop.org,
intel-gvt-dev@lists.freedesktop.org
Cc: joonas.lahtinen@intel.com, zhiyuan.lv@intel.com,
fei.jiang@intel.com, zhenyu.z.wang@intel.com,
hang.yuan@intel.com
Subject: Re: [v1 03/10] drm/i915: context submission pvmmio optimization
Date: Thu, 11 Oct 2018 10:12:09 +0100 [thread overview]
Message-ID: <153924912984.533.13759332714915158455@skylake-alporthouse-com> (raw)
In-Reply-To: <1539238452-4389-3-git-send-email-xiaolin.zhang@intel.com>
Quoting Xiaolin Zhang (2018-10-11 07:14:05)
> It is performance optimization to reduce mmio trap numbers from 4 to
> 1 durning ELSP porting writing (context submission).
>
> When context subission, to cache elsp_data[4] values in
> the shared page, the last elsp_data[0] port writing will be trapped
> to gvt for real context submission.
>
> Use PVMMIO_ELSP_SUBMIT to control this level of pvmmio optimization.
>
> v1: rebase
> v0: RFC
>
> Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
> ---
> drivers/gpu/drm/i915/i915_vgpu.c | 2 ++
> drivers/gpu/drm/i915/intel_lrc.c | 37 ++++++++++++++++++++++++++++++++++++-
Hint: intel_vgpu_submission.c and go wild. You do not need to emulate
execlists at all, an async interface along the lines of guc would
strangely enough be more akin to what you want.
-Chris
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next prev parent reply other threads:[~2018-10-11 9:12 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-11 6:14 [v1 01/10] drm/i915: introduced pv capability for vgpu Xiaolin Zhang
2018-10-11 6:14 ` [v1 02/10] drm/i915: get ready of memory for pvmmio Xiaolin Zhang
2018-10-11 6:14 ` [v1 03/10] drm/i915: context submission pvmmio optimization Xiaolin Zhang
2018-10-11 9:12 ` Chris Wilson [this message]
2018-10-15 2:35 ` Zhang, Xiaolin
2018-10-11 6:14 ` [v1 04/10] drm/i915: master irq " Xiaolin Zhang
2018-10-11 6:14 ` [v1 05/10] drm/i915: ppgtt update " Xiaolin Zhang
2018-10-11 6:14 ` [v1 06/10] drm/i915/gvt: GVTg handle enable_pvmmio PVINFO register Xiaolin Zhang
2018-10-11 6:14 ` [v1 07/10] drm/i915/gvt: GVTg read_shared_page implementation Xiaolin Zhang
2018-10-11 6:14 ` [v1 08/10] drm/i915/gvt: GVTg support context submission pvmmio optimization Xiaolin Zhang
2018-10-11 6:14 ` [v1 09/10] drm/i915/gvt: GVTg support master irq " Xiaolin Zhang
2018-10-11 6:14 ` [v1 10/10] drm/i915/gvt: GVTg support ppgtt " Xiaolin Zhang
2018-10-11 8:06 ` Zhao, Yakui
2018-10-15 2:38 ` Zhang, Xiaolin
2018-10-11 6:32 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v1,01/10] drm/i915: introduced pv capability for vgpu Patchwork
2018-10-11 6:35 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-10-11 6:47 ` ✓ Fi.CI.BAT: success " Patchwork
2018-10-11 13:07 ` ✓ Fi.CI.IGT: " Patchwork
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