All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH v1] drm/i915/icl: Define MOCS table for Icelake
@ 2018-10-19 15:19 Tomasz Lis
  2018-10-19 16:19 ` Daniele Ceraolo Spurio
                   ` (7 more replies)
  0 siblings, 8 replies; 18+ messages in thread
From: Tomasz Lis @ 2018-10-19 15:19 UTC (permalink / raw)
  To: intel-gfx; +Cc: Mika Kuoppala

The table has been unified across OSes to minimize virtualization overhead.

The MOCS table is now versioned; the patch includes version 1 entries.

BSpec: 34007
BSpec: 560
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_mocs.c | 246 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 244 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 77e9871..b76d6db 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -44,6 +44,8 @@ struct drm_i915_mocs_table {
 #define LE_SCC(value)		((value) << 8)
 #define LE_PFM(value)		((value) << 11)
 #define LE_SCF(value)		((value) << 14)
+#define LE_CoS(value)		((value) << 15)
+#define LE_SSE(value)		((value) << 17)
 
 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
 #define L3_ESC(value)		((value) << 0)
@@ -96,6 +98,243 @@ struct drm_i915_mocs_table {
  *       may only be updated incrementally by adding entries at the
  *       end.
  */
+static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
+	[0] = {
+	  /* Base - Uncached (Deprecated) */
+	  .control_value = LE_CACHEABILITY(LE_UC) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[1] = {
+	  /* Base - L3 + LeCC:PAT (Deprecated) */
+	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[2] = {
+	  /* Base - L3 + LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[3] = {
+	  /* Base - Uncached */
+	  .control_value = LE_CACHEABILITY(LE_UC) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[4] = {
+	  /* Base - L3 */
+	  .control_value = LE_CACHEABILITY(LE_UC) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[5] = {
+	  /* Base - LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[6] = {
+	  /* Age 0 - LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[7] = {
+	  /* Age 0 - L3 + LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[8] = {
+	  /* Age: Don't Chg. - LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[9] = {
+	  /* Age: Don't Chg. - L3 + LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[10] = {
+	  /* No AOM - LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[11] = {
+	  /* No AOM - L3 + LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[12] = {
+	  /* No AOM; Age 0 - LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[13] = {
+	  /* No AOM; Age 0 - L3 + LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[14] = {
+	  /* No AOM; Age:DC - LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[15] = {
+	  /* No AOM; Age:DC - L3 + LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[16] = {
+	  /* Reserved - For future use */
+	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
+			   LE_TGT_CACHE(LE_TC_PAGETABLE) |
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT),
+	},
+	[17] = {
+	  /* Reserved - For future use */
+	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
+			   LE_TGT_CACHE(LE_TC_PAGETABLE) |
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT),
+	},
+	[18] = {
+	  /* Self-Snoop - L3 + LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(3),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[19] = {
+	  /* Skip Caching - L3 + LLC(12.5%) */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[20] = {
+	  /* Skip Caching - L3 + LLC(25%) */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[21] = {
+	  /* Skip Caching - L3 + LLC(50%) */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[22] = {
+	  /* Skip Caching - L3 + LLC(75%) */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[23] = {
+	  /* Skip Caching - L3 + LLC(87.5%) */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[62] = {
+	  /* HW Reserved - SW program but never use */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[63] = {
+	  /* HW Reserved - SW program but never use */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+};
+
 static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
 	[I915_MOCS_UNCACHED] = {
 	  /* 0x00000009 */
@@ -178,8 +417,11 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
 {
 	bool result = false;
 
-	if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) ||
-	    IS_ICELAKE(dev_priv)) {
+	if (IS_ICELAKE(dev_priv)) {
+		table->size  = ARRAY_SIZE(icelake_mocs_table);
+		table->table = icelake_mocs_table;
+		result = true;
+	} else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 		table->size  = ARRAY_SIZE(skylake_mocs_table);
 		table->table = skylake_mocs_table;
 		result = true;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 18+ messages in thread
* Re: [PATCH v1] drm/i915/icl: Define MOCS table for Icelake
  2018-10-19 15:19 [PATCH v1] drm/i915/icl: Define MOCS table for Icelake Tomasz Lis
@ 2018-10-19 16:19 ` Daniele Ceraolo Spurio
  2018-10-19 16:23   ` Lionel Landwerlin
  2018-10-22 12:42 ` ✓ Fi.CI.BAT: success for " Patchwork
                   ` (6 subsequent siblings)
  7 siblings, 1 reply; 18+ messages in thread
From: Daniele Ceraolo Spurio @ 2018-10-19 16:19 UTC (permalink / raw)
  To: Tomasz Lis, intel-gfx; +Cc: Mika Kuoppala



On 19/10/18 08:19, Tomasz Lis wrote:
> The table has been unified across OSes to minimize virtualization overhead.
> 
> The MOCS table is now versioned; the patch includes version 1 entries.

A bit more explanation is required here. We need to make clear the fact 
that existing entries in the table for a given gen will not change in 
new versions of the table and only new entries might be added. Also the 
fact that since the table is in the specs we expect the users to know 
what each entry of the table means and we're therefore deprecating 
exposing the entries in the uapi with an enum.
Might also be worth mentioning that the first 3 entries are compatible 
with the legacy i915 entries for previous gen but that this is not 
guaranteed on future gens so userland drivers need to use the ICL 
timeframe to transition.

Lastly, we need a way to query what version of the table the kernel is 
programming in HW.

> 
> BSpec: 34007
> BSpec: 560
> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>

CC some mesa people here? not sure who the right contact would be for this

> ---
>   drivers/gpu/drm/i915/intel_mocs.c | 246 +++++++++++++++++++++++++++++++++++++-
>   1 file changed, 244 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index 77e9871..b76d6db 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -44,6 +44,8 @@ struct drm_i915_mocs_table {
>   #define LE_SCC(value)		((value) << 8)
>   #define LE_PFM(value)		((value) << 11)
>   #define LE_SCF(value)		((value) << 14)
> +#define LE_CoS(value)		((value) << 15)
> +#define LE_SSE(value)		((value) << 17)
>   
>   /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
>   #define L3_ESC(value)		((value) << 0)
> @@ -96,6 +98,243 @@ struct drm_i915_mocs_table {
>    *       may only be updated incrementally by adding entries at the
>    *       end.
>    */
> +static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
> +	[0] = {
> +	  /* Base - Uncached (Deprecated) */
> +	  .control_value = LE_CACHEABILITY(LE_UC) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[1] = {
> +	  /* Base - L3 + LeCC:PAT (Deprecated) */
> +	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[2] = {
> +	  /* Base - L3 + LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[3] = {
> +	  /* Base - Uncached */
> +	  .control_value = LE_CACHEABILITY(LE_UC) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[4] = {
> +	  /* Base - L3 */
> +	  .control_value = LE_CACHEABILITY(LE_UC) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[5] = {
> +	  /* Base - LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[6] = {
> +	  /* Age 0 - LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[7] = {
> +	  /* Age 0 - L3 + LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[8] = {
> +	  /* Age: Don't Chg. - LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[9] = {
> +	  /* Age: Don't Chg. - L3 + LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[10] = {
> +	  /* No AOM - LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[11] = {
> +	  /* No AOM - L3 + LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[12] = {
> +	  /* No AOM; Age 0 - LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[13] = {
> +	  /* No AOM; Age 0 - L3 + LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[14] = {
> +	  /* No AOM; Age:DC - LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[15] = {
> +	  /* No AOM; Age:DC - L3 + LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[16] = {
> +	  /* Reserved - For future use */
> +	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
> +			   LE_TGT_CACHE(LE_TC_PAGETABLE) |
> +			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT),
> +	},
> +	[17] = {
> +	  /* Reserved - For future use */
> +	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
> +			   LE_TGT_CACHE(LE_TC_PAGETABLE) |
> +			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT),
> +	},
> +	[18] = {
> +	  /* Self-Snoop - L3 + LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(3),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[19] = {
> +	  /* Skip Caching - L3 + LLC(12.5%) */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |

The spec have LE_SCC(7) here

> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[20] = {
> +	  /* Skip Caching - L3 + LLC(25%) */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |

LE_SCC(3) here

> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[21] = {
> +	  /* Skip Caching - L3 + LLC(50%) */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |

LE_SCC(1) here

> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[22] = {
> +	  /* Skip Caching - L3 + LLC(75%) */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(0) |

LE_SCC(3) here

> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[23] = {
> +	  /* Skip Caching - L3 + LLC(87.5%) */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(0) |

LE_SCC(7) here

Thanks,
Daniele

> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[62] = {
> +	  /* HW Reserved - SW program but never use */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[63] = {
> +	  /* HW Reserved - SW program but never use */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +};
> +
>   static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
>   	[I915_MOCS_UNCACHED] = {
>   	  /* 0x00000009 */
> @@ -178,8 +417,11 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
>   {
>   	bool result = false;
>   
> -	if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) ||
> -	    IS_ICELAKE(dev_priv)) {
> +	if (IS_ICELAKE(dev_priv)) {
> +		table->size  = ARRAY_SIZE(icelake_mocs_table);
> +		table->table = icelake_mocs_table;
> +		result = true;
> +	} else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>   		table->size  = ARRAY_SIZE(skylake_mocs_table);
>   		table->table = skylake_mocs_table;
>   		result = true;
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread
* Re: [PATCH v1] drm/i915/icl: Define MOCS table for Icelake
  2018-10-19 16:19 ` Daniele Ceraolo Spurio
@ 2018-10-19 16:23   ` Lionel Landwerlin
  0 siblings, 0 replies; 18+ messages in thread
From: Lionel Landwerlin @ 2018-10-19 16:23 UTC (permalink / raw)
  To: Daniele Ceraolo Spurio, Tomasz Lis, intel-gfx; +Cc: Phogat, Anuj, Mika Kuoppala

On 19/10/2018 17:19, Daniele Ceraolo Spurio wrote:
> CC some mesa people here? not sure who the right contact would be for 
> this 
Adding Anuj.

-
Lionel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/icl: Define MOCS table for Icelake
  2018-10-19 15:19 [PATCH v1] drm/i915/icl: Define MOCS table for Icelake Tomasz Lis
  2018-10-19 16:19 ` Daniele Ceraolo Spurio
@ 2018-10-22 12:42 ` Patchwork
  2018-10-22 15:15 ` ✓ Fi.CI.IGT: " Patchwork
                   ` (5 subsequent siblings)
  7 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2018-10-22 12:42 UTC (permalink / raw)
  To: Lis, Tomasz; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/icl: Define MOCS table for Icelake
URL   : https://patchwork.freedesktop.org/series/51258/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_5016 -> Patchwork_10516 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10516 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10516, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/51258/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10516:

  === IGT changes ===

    ==== Warnings ====

    igt@drv_selftest@live_guc:
      fi-apl-guc:         PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_10516 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_selftest@live_execlists:
      fi-apl-guc:         PASS -> INCOMPLETE (fdo#106693)

    igt@kms_flip@basic-flip-vs-dpms:
      fi-skl-6700hq:      PASS -> DMESG-WARN (fdo#105998)

    igt@kms_pipe_crc_basic@hang-read-crc-pipe-b:
      fi-byt-clapper:     PASS -> FAIL (fdo#103191, fdo#107362)

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
      fi-byt-clapper:     PASS -> FAIL (fdo#107362)

    igt@kms_pipe_crc_basic@read-crc-pipe-a:
      fi-ilk-650:         PASS -> DMESG-WARN (fdo#106387)

    
    ==== Possible fixes ====

    igt@kms_pipe_crc_basic@read-crc-pipe-b:
      fi-byt-clapper:     FAIL (fdo#107362) -> PASS

    
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
  fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387
  fdo#106693 https://bugs.freedesktop.org/show_bug.cgi?id=106693
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362


== Participating hosts (51 -> 44) ==

  Additional (1): fi-cfl-8109u 
  Missing    (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-snb-2520m fi-ctg-p8600 fi-icl-u 


== Build changes ==

    * Linux: CI_DRM_5016 -> Patchwork_10516

  CI_DRM_5016: dd5831c406bfcbb9662ff8b6e874f8d455c097e1 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4685: 78619fde4008424c472906041edb1d204e014f7c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10516: 9b800d19a4bbb0350ee102fcf519c2ff6a908cae @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

9b800d19a4bb drm/i915/icl: Define MOCS table for Icelake

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10516/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/icl: Define MOCS table for Icelake
  2018-10-19 15:19 [PATCH v1] drm/i915/icl: Define MOCS table for Icelake Tomasz Lis
  2018-10-19 16:19 ` Daniele Ceraolo Spurio
  2018-10-22 12:42 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2018-10-22 15:15 ` Patchwork
  2018-10-22 17:13 ` [PATCH v2 1/2] " Tomasz Lis
                   ` (4 subsequent siblings)
  7 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2018-10-22 15:15 UTC (permalink / raw)
  To: Lis, Tomasz; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/icl: Define MOCS table for Icelake
URL   : https://patchwork.freedesktop.org/series/51258/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_5016_full -> Patchwork_10516_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10516_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10516_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10516_full:

  === IGT changes ===

    ==== Warnings ====

    igt@pm_rc6_residency@rc6-accuracy:
      shard-snb:          PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_10516_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
      shard-snb:          PASS -> DMESG-WARN (fdo#107956)

    igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
      shard-glk:          PASS -> FAIL (fdo#108145)

    igt@kms_cursor_crc@cursor-64x21-onscreen:
      shard-apl:          PASS -> FAIL (fdo#103232)

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
      shard-glk:          PASS -> FAIL (fdo#103167) +3

    igt@kms_plane@pixel-format-pipe-a-planes:
      shard-skl:          NOTRUN -> DMESG-FAIL (fdo#106885, fdo#103166)

    igt@kms_plane@plane-position-covered-pipe-a-planes:
      shard-glk:          PASS -> FAIL (fdo#103166)

    igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
      shard-skl:          NOTRUN -> FAIL (fdo#108145) +1

    igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
      shard-skl:          NOTRUN -> FAIL (fdo#108145, fdo#107815)

    igt@kms_setmode@basic:
      shard-apl:          PASS -> FAIL (fdo#99912)

    igt@perf_pmu@interrupts-sync:
      shard-glk:          PASS -> INCOMPLETE (k.org#198133, fdo#103359)

    igt@pm_rps@reset:
      shard-glk:          PASS -> FAIL (fdo#102250)

    igt@syncobj_wait@wait-all-for-submit-delayed-submit:
      shard-skl:          NOTRUN -> INCOMPLETE (fdo#108490)

    
    ==== Possible fixes ====

    igt@kms_color@pipe-a-legacy-gamma:
      shard-skl:          FAIL (fdo#108145, fdo#104782) -> PASS

    igt@kms_cursor_crc@cursor-size-change:
      shard-apl:          FAIL (fdo#103232) -> PASS

    igt@kms_draw_crc@draw-method-rgb565-blt-xtiled:
      shard-skl:          FAIL (fdo#103184) -> PASS

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt:
      shard-skl:          FAIL (fdo#105682) -> PASS +1

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
      shard-glk:          FAIL (fdo#103167) -> PASS +2

    igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-render:
      shard-skl:          FAIL (fdo#103167) -> PASS +1

    igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
      shard-skl:          FAIL (fdo#103166) -> PASS

    igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
      shard-skl:          FAIL (fdo#108145, fdo#107815) -> PASS

    igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
      shard-apl:          FAIL (fdo#108145) -> PASS

    
    ==== Warnings ====

    igt@kms_fbcon_fbt@psr-suspend:
      shard-skl:          INCOMPLETE (fdo#104108) -> FAIL (fdo#107882)

    
  fdo#102250 https://bugs.freedesktop.org/show_bug.cgi?id=102250
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
  fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782
  fdo#105682 https://bugs.freedesktop.org/show_bug.cgi?id=105682
  fdo#106885 https://bugs.freedesktop.org/show_bug.cgi?id=106885
  fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815
  fdo#107882 https://bugs.freedesktop.org/show_bug.cgi?id=107882
  fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
  fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
  fdo#108490 https://bugs.freedesktop.org/show_bug.cgi?id=108490
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_5016 -> Patchwork_10516

  CI_DRM_5016: dd5831c406bfcbb9662ff8b6e874f8d455c097e1 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4685: 78619fde4008424c472906041edb1d204e014f7c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10516: 9b800d19a4bbb0350ee102fcf519c2ff6a908cae @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10516/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread
* [PATCH v2 1/2] drm/i915/icl: Define MOCS table for Icelake
  2018-10-19 15:19 [PATCH v1] drm/i915/icl: Define MOCS table for Icelake Tomasz Lis
                   ` (2 preceding siblings ...)
  2018-10-22 15:15 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-10-22 17:13 ` Tomasz Lis
  2018-10-22 17:13   ` [PATCH v2 2/2] drm/i915/icl: Add IOCTL for getting MOCS table version Tomasz Lis
  2018-10-22 17:40   ` [PATCH v2 1/2] drm/i915/icl: Define MOCS table for Icelake Daniele Ceraolo Spurio
  2018-10-23 13:23 ` [PATCH v3] " Tomasz Lis
                   ` (3 subsequent siblings)
  7 siblings, 2 replies; 18+ messages in thread
From: Tomasz Lis @ 2018-10-22 17:13 UTC (permalink / raw)
  To: intel-gfx; +Cc: Anuj Phogat, Mika Kuoppala

The table has been unified across OSes to minimize virtualization overhead.

The MOCS table is now published as part of bspec, and versioned. Entries
are supposed to never be modified, but new ones can be added. Adding
entries increases table version. The patch includes version 1 entries.

Meaning of each entry is now explained in bspec, and user mode clients
are expected to know what each entry means. The 3 entries used for previous
platforms are still compatible with their legacy definitions, but that is
not guaranteed to be true for future platforms.

BSpec: 34007
BSpec: 560
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi A Wang <zhi.a.wang@intel.com>
Cc: Anuj Phogat <anuj.phogat@intel.com>
---
 drivers/gpu/drm/i915/intel_mocs.c | 246 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 244 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 77e9871..dc34e83 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -44,6 +44,8 @@ struct drm_i915_mocs_table {
 #define LE_SCC(value)		((value) << 8)
 #define LE_PFM(value)		((value) << 11)
 #define LE_SCF(value)		((value) << 14)
+#define LE_CoS(value)		((value) << 15)
+#define LE_SSE(value)		((value) << 17)
 
 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
 #define L3_ESC(value)		((value) << 0)
@@ -96,6 +98,243 @@ struct drm_i915_mocs_table {
  *       may only be updated incrementally by adding entries at the
  *       end.
  */
+static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
+	[0] = {
+	  /* Base - Uncached (Deprecated) */
+	  .control_value = LE_CACHEABILITY(LE_UC) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[1] = {
+	  /* Base - L3 + LeCC:PAT (Deprecated) */
+	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[2] = {
+	  /* Base - L3 + LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[3] = {
+	  /* Base - Uncached */
+	  .control_value = LE_CACHEABILITY(LE_UC) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[4] = {
+	  /* Base - L3 */
+	  .control_value = LE_CACHEABILITY(LE_UC) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[5] = {
+	  /* Base - LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[6] = {
+	  /* Age 0 - LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[7] = {
+	  /* Age 0 - L3 + LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[8] = {
+	  /* Age: Don't Chg. - LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[9] = {
+	  /* Age: Don't Chg. - L3 + LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[10] = {
+	  /* No AOM - LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[11] = {
+	  /* No AOM - L3 + LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[12] = {
+	  /* No AOM; Age 0 - LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[13] = {
+	  /* No AOM; Age 0 - L3 + LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[14] = {
+	  /* No AOM; Age:DC - LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[15] = {
+	  /* No AOM; Age:DC - L3 + LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[16] = {
+	  /* Reserved - For future use */
+	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
+			   LE_TGT_CACHE(LE_TC_PAGETABLE) |
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT),
+	},
+	[17] = {
+	  /* Reserved - For future use */
+	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
+			   LE_TGT_CACHE(LE_TC_PAGETABLE) |
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT),
+	},
+	[18] = {
+	  /* Self-Snoop - L3 + LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(3),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[19] = {
+	  /* Skip Caching - L3 + LLC(12.5%) */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(7) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[20] = {
+	  /* Skip Caching - L3 + LLC(25%) */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(3) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[21] = {
+	  /* Skip Caching - L3 + LLC(50%) */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(1) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[22] = {
+	  /* Skip Caching - L3 + LLC(75%) */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(3) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[23] = {
+	  /* Skip Caching - L3 + LLC(87.5%) */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(7) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[62] = {
+	  /* HW Reserved - SW program but never use */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[63] = {
+	  /* HW Reserved - SW program but never use */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+};
+
 static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
 	[I915_MOCS_UNCACHED] = {
 	  /* 0x00000009 */
@@ -178,8 +417,11 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
 {
 	bool result = false;
 
-	if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) ||
-	    IS_ICELAKE(dev_priv)) {
+	if (IS_ICELAKE(dev_priv)) {
+		table->size  = ARRAY_SIZE(icelake_mocs_table);
+		table->table = icelake_mocs_table;
+		result = true;
+	} else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 		table->size  = ARRAY_SIZE(skylake_mocs_table);
 		table->table = skylake_mocs_table;
 		result = true;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 18+ messages in thread
* [PATCH v2 2/2] drm/i915/icl: Add IOCTL for getting MOCS table version
  2018-10-22 17:13 ` [PATCH v2 1/2] " Tomasz Lis
@ 2018-10-22 17:13   ` Tomasz Lis
  2018-10-22 18:18     ` Daniele Ceraolo Spurio
  2018-10-23  9:06     ` Joonas Lahtinen
  2018-10-22 17:40   ` [PATCH v2 1/2] drm/i915/icl: Define MOCS table for Icelake Daniele Ceraolo Spurio
  1 sibling, 2 replies; 18+ messages in thread
From: Tomasz Lis @ 2018-10-22 17:13 UTC (permalink / raw)
  To: intel-gfx; +Cc: Anuj Phogat, Mika Kuoppala

For Icelake and above, MOCS table for each platform is published
within bspec. The table is versioned, and new entries are assigned
a version number. Existing entries do not change and their version
is constant.

This introduces a parameter which allows getting max version number
of the MOCS entries currently supported, ie. value of 2 would mean
only version 1 and version 2 entries are initialized and can be used
by the user mode clients.

BSpec: 34007
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi A Wang <zhi.a.wang@intel.com>
Cc: Anuj Phogat <anuj.phogat@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c   |  6 ++++++
 drivers/gpu/drm/i915/intel_mocs.c | 12 ++++++++++++
 drivers/gpu/drm/i915/intel_mocs.h |  1 +
 include/uapi/drm/i915_drm.h       | 11 +++++++++++
 4 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index baac35f..92fa8fd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -53,6 +53,7 @@
 #include "i915_vgpu.h"
 #include "intel_drv.h"
 #include "intel_uc.h"
+#include "intel_mocs.h"
 
 static struct drm_driver driver;
 
@@ -444,6 +445,11 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 	case I915_PARAM_MMAP_GTT_COHERENT:
 		value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
 		break;
+	case I915_PARAM_MOCS_TABLE_VERSION:
+		value = intel_mocs_table_version(dev_priv);
+		if (!value)
+			return -ENODEV;
+		break;
 	default:
 		DRM_DEBUG("Unknown parameter %d\n", param->param);
 		return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index dc34e83..fc1e98b 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -469,6 +469,18 @@ static i915_reg_t mocs_register(enum intel_engine_id engine_id, int index)
 }
 
 /**
+ * intel_mocs_table_version() - get version of mocs table implementation
+ * @i915: i915 device struct.
+ */
+int intel_mocs_table_version(struct drm_i915_private *i915)
+{
+	if (IS_ICELAKE(i915))
+		return 1;
+	else
+		return 0;
+}
+
+/**
  * intel_mocs_init_engine() - emit the mocs control table
  * @engine:	The engine for whom to emit the registers.
  *
diff --git a/drivers/gpu/drm/i915/intel_mocs.h b/drivers/gpu/drm/i915/intel_mocs.h
index d89080d..dc1d64a 100644
--- a/drivers/gpu/drm/i915/intel_mocs.h
+++ b/drivers/gpu/drm/i915/intel_mocs.h
@@ -55,5 +55,6 @@
 int intel_rcs_context_init_mocs(struct i915_request *rq);
 void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv);
 void intel_mocs_init_engine(struct intel_engine_cs *engine);
+int intel_mocs_table_version(struct drm_i915_private *i915);
 
 #endif
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 298b2e1..16aafc4 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -559,6 +559,17 @@ typedef struct drm_i915_irq_wait {
  */
 #define I915_PARAM_MMAP_GTT_COHERENT	52
 
+/*
+ * Query MOCS table version used during hardware initialization.
+ *
+ * The MOCS table for each platform is published as part of bspec. Entries in
+ * the table are supposed to never be modified, but new enties are added, making
+ * more indexes in the table valid. This parameter informs which version
+ * of the table was used to initialize the currently used graphics hardware,
+ * and therefore which MOCS indexes are useable.
+ */
+#define I915_PARAM_MOCS_TABLE_VERSION	53
+
 typedef struct drm_i915_getparam {
 	__s32 param;
 	/*
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 18+ messages in thread
* Re: [PATCH v2 1/2] drm/i915/icl: Define MOCS table for Icelake
  2018-10-22 17:13 ` [PATCH v2 1/2] " Tomasz Lis
  2018-10-22 17:13   ` [PATCH v2 2/2] drm/i915/icl: Add IOCTL for getting MOCS table version Tomasz Lis
@ 2018-10-22 17:40   ` Daniele Ceraolo Spurio
  2018-10-23 13:07     ` Lis, Tomasz
  1 sibling, 1 reply; 18+ messages in thread
From: Daniele Ceraolo Spurio @ 2018-10-22 17:40 UTC (permalink / raw)
  To: Tomasz Lis, intel-gfx; +Cc: Anuj Phogat, Mika Kuoppala



On 22/10/18 10:13, Tomasz Lis wrote:
> The table has been unified across OSes to minimize virtualization overhead.
> 
> The MOCS table is now published as part of bspec, and versioned. Entries
> are supposed to never be modified, but new ones can be added. Adding
> entries increases table version. The patch includes version 1 entries.
> 
> Meaning of each entry is now explained in bspec, and user mode clients
> are expected to know what each entry means. The 3 entries used for previous
> platforms are still compatible with their legacy definitions, but that is
> not guaranteed to be true for future platforms.
> 
> BSpec: 34007
> BSpec: 560
> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> Cc: Zhi A Wang <zhi.a.wang@intel.com>
> Cc: Anuj Phogat <anuj.phogat@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_mocs.c | 246 +++++++++++++++++++++++++++++++++++++-
>   1 file changed, 244 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index 77e9871..dc34e83 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -44,6 +44,8 @@ struct drm_i915_mocs_table {
>   #define LE_SCC(value)		((value) << 8)
>   #define LE_PFM(value)		((value) << 11)
>   #define LE_SCF(value)		((value) << 14)
> +#define LE_CoS(value)		((value) << 15)
> +#define LE_SSE(value)		((value) << 17)
>   
>   /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
>   #define L3_ESC(value)		((value) << 0)
> @@ -96,6 +98,243 @@ struct drm_i915_mocs_table {
>    *       may only be updated incrementally by adding entries at the
>    *       end.
>    */

This comment needs to be updated as some of the expectations are not 
true anymore, e.g. we're now defining entries 62 and 63 in SW, usage of 
mocs 0 is changing. Also could be useful to add some of the info you 
have in the commit message here, like the fact that the table is 
versioned in the specs for gen11+, so it is close to the table.

 From a POV of following the specs, with the updated comments this is:

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

But please get acks from the relevant interested parties to make sure 
there are no concerns with the new approach. Also having someone else 
double-check the table as well would be nice since I might have missed 
something and it's going to be hard to catch issues in testing if the 
only impact is a very small performance delta.

Thanks,
Daniele

> +static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
> +	[0] = {
> +	  /* Base - Uncached (Deprecated) */
> +	  .control_value = LE_CACHEABILITY(LE_UC) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[1] = {
> +	  /* Base - L3 + LeCC:PAT (Deprecated) */
> +	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[2] = {
> +	  /* Base - L3 + LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[3] = {
> +	  /* Base - Uncached */
> +	  .control_value = LE_CACHEABILITY(LE_UC) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[4] = {
> +	  /* Base - L3 */
> +	  .control_value = LE_CACHEABILITY(LE_UC) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[5] = {
> +	  /* Base - LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[6] = {
> +	  /* Age 0 - LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[7] = {
> +	  /* Age 0 - L3 + LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[8] = {
> +	  /* Age: Don't Chg. - LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[9] = {
> +	  /* Age: Don't Chg. - L3 + LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[10] = {
> +	  /* No AOM - LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[11] = {
> +	  /* No AOM - L3 + LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[12] = {
> +	  /* No AOM; Age 0 - LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[13] = {
> +	  /* No AOM; Age 0 - L3 + LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[14] = {
> +	  /* No AOM; Age:DC - LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[15] = {
> +	  /* No AOM; Age:DC - L3 + LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[16] = {
> +	  /* Reserved - For future use */
> +	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
> +			   LE_TGT_CACHE(LE_TC_PAGETABLE) |
> +			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT),
> +	},
> +	[17] = {
> +	  /* Reserved - For future use */
> +	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
> +			   LE_TGT_CACHE(LE_TC_PAGETABLE) |
> +			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT),
> +	},
> +	[18] = {
> +	  /* Self-Snoop - L3 + LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(3),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[19] = {
> +	  /* Skip Caching - L3 + LLC(12.5%) */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(7) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[20] = {
> +	  /* Skip Caching - L3 + LLC(25%) */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(3) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[21] = {
> +	  /* Skip Caching - L3 + LLC(50%) */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(1) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[22] = {
> +	  /* Skip Caching - L3 + LLC(75%) */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(3) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[23] = {
> +	  /* Skip Caching - L3 + LLC(87.5%) */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(7) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[62] = {
> +	  /* HW Reserved - SW program but never use */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[63] = {
> +	  /* HW Reserved - SW program but never use */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +};
> +
>   static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
>   	[I915_MOCS_UNCACHED] = {
>   	  /* 0x00000009 */
> @@ -178,8 +417,11 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
>   {
>   	bool result = false;
>   
> -	if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) ||
> -	    IS_ICELAKE(dev_priv)) {
> +	if (IS_ICELAKE(dev_priv)) {
> +		table->size  = ARRAY_SIZE(icelake_mocs_table);
> +		table->table = icelake_mocs_table;
> +		result = true;
> +	} else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>   		table->size  = ARRAY_SIZE(skylake_mocs_table);
>   		table->table = skylake_mocs_table;
>   		result = true;
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread
* Re: [PATCH v2 2/2] drm/i915/icl: Add IOCTL for getting MOCS table version
  2018-10-22 17:13   ` [PATCH v2 2/2] drm/i915/icl: Add IOCTL for getting MOCS table version Tomasz Lis
@ 2018-10-22 18:18     ` Daniele Ceraolo Spurio
  2018-10-23 12:02       ` Lis, Tomasz
  2018-10-23  9:06     ` Joonas Lahtinen
  1 sibling, 1 reply; 18+ messages in thread
From: Daniele Ceraolo Spurio @ 2018-10-22 18:18 UTC (permalink / raw)
  To: Tomasz Lis, intel-gfx; +Cc: Anuj Phogat, Mika Kuoppala



On 22/10/18 10:13, Tomasz Lis wrote:
> For Icelake and above, MOCS table for each platform is published
> within bspec. The table is versioned, and new entries are assigned
> a version number. Existing entries do not change and their version
> is constant.
> 
> This introduces a parameter which allows getting max version number
> of the MOCS entries currently supported, ie. value of 2 would mean
> only version 1 and version 2 entries are initialized and can be used
> by the user mode clients.
> 
> BSpec: 34007
> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> Cc: Zhi A Wang <zhi.a.wang@intel.com>
> Cc: Anuj Phogat <anuj.phogat@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.c   |  6 ++++++
>   drivers/gpu/drm/i915/intel_mocs.c | 12 ++++++++++++
>   drivers/gpu/drm/i915/intel_mocs.h |  1 +
>   include/uapi/drm/i915_drm.h       | 11 +++++++++++
>   4 files changed, 30 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index baac35f..92fa8fd 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -53,6 +53,7 @@
>   #include "i915_vgpu.h"
>   #include "intel_drv.h"
>   #include "intel_uc.h"
> +#include "intel_mocs.h"
>   
>   static struct drm_driver driver;
>   
> @@ -444,6 +445,11 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
>   	case I915_PARAM_MMAP_GTT_COHERENT:
>   		value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
>   		break;
> +	case I915_PARAM_MOCS_TABLE_VERSION:
> +		value = intel_mocs_table_version(dev_priv);
> +		if (!value)
> +			return -ENODEV;

Do we really want to return -ENODEV for platforms that do have a MOCS 
table programmed, but the table is not one versioned in the specs (i.e. 
Gen9-10)? I think returning "0" for those to indicate "kernel-defined 
table" would be ok and we could limit -ENODEV for platforms that don't 
have a table at all. But what wins is what the callers of the ioctl 
would like to get from the kernel ;)

> +		break;
>   	default:
>   		DRM_DEBUG("Unknown parameter %d\n", param->param);
>   		return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index dc34e83..fc1e98b 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -469,6 +469,18 @@ static i915_reg_t mocs_register(enum intel_engine_id engine_id, int index)
>   }
>   
>   /**
> + * intel_mocs_table_version() - get version of mocs table implementation
> + * @i915: i915 device struct.
> + */
> +int intel_mocs_table_version(struct drm_i915_private *i915)
> +{
> +	if (IS_ICELAKE(i915))
> +		return 1;

Can we add this version value as a define above the table, to keep them 
close to each other?

If we agree on my suggestion above to differentiate between no table at 
all (< 0), kernel-defined table (= 0) and spec-defined versioned table 
(> 0), it might also be useful to store the version with the table info 
in drm_i915_mocs_table and then have intel_mocs_table_version call 
get_mocs_settings(), e.g:

int intel_mocs_table_version(struct drm_i915_private *i915)
{
	struct drm_i915_mocs_table table;

	if (!get_mocs_settings(i915, &table))
		return -ENODEV;

	return table->version;
}

Thanks,
Daniele

> +	else
> +		return 0;
> +}
> +
> +/**
>    * intel_mocs_init_engine() - emit the mocs control table
>    * @engine:	The engine for whom to emit the registers.
>    *
> diff --git a/drivers/gpu/drm/i915/intel_mocs.h b/drivers/gpu/drm/i915/intel_mocs.h
> index d89080d..dc1d64a 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.h
> +++ b/drivers/gpu/drm/i915/intel_mocs.h
> @@ -55,5 +55,6 @@
>   int intel_rcs_context_init_mocs(struct i915_request *rq);
>   void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv);
>   void intel_mocs_init_engine(struct intel_engine_cs *engine);
> +int intel_mocs_table_version(struct drm_i915_private *i915);
>   
>   #endif
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 298b2e1..16aafc4 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -559,6 +559,17 @@ typedef struct drm_i915_irq_wait {
>    */
>   #define I915_PARAM_MMAP_GTT_COHERENT	52
>   
> +/*
> + * Query MOCS table version used during hardware initialization.
> + *
> + * The MOCS table for each platform is published as part of bspec. Entries in
> + * the table are supposed to never be modified, but new enties are added, making
> + * more indexes in the table valid. This parameter informs which version
> + * of the table was used to initialize the currently used graphics hardware,
> + * and therefore which MOCS indexes are useable.
> + */
> +#define I915_PARAM_MOCS_TABLE_VERSION	53
> +
>   typedef struct drm_i915_getparam {
>   	__s32 param;
>   	/*
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread
* Re: [PATCH v2 2/2] drm/i915/icl: Add IOCTL for getting MOCS table version
  2018-10-22 17:13   ` [PATCH v2 2/2] drm/i915/icl: Add IOCTL for getting MOCS table version Tomasz Lis
  2018-10-22 18:18     ` Daniele Ceraolo Spurio
@ 2018-10-23  9:06     ` Joonas Lahtinen
  1 sibling, 0 replies; 18+ messages in thread
From: Joonas Lahtinen @ 2018-10-23  9:06 UTC (permalink / raw)
  To: Tomasz Lis, intel-gfx; +Cc: Anuj Phogat, Mika Kuoppala

Quoting Tomasz Lis (2018-10-22 20:13:15)
> For Icelake and above, MOCS table for each platform is published
> within bspec. The table is versioned, and new entries are assigned
> a version number. Existing entries do not change and their version
> is constant.
> 
> This introduces a parameter which allows getting max version number
> of the MOCS entries currently supported, ie. value of 2 would mean
> only version 1 and version 2 entries are initialized and can be used
> by the user mode clients.
> 
> BSpec: 34007
> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> Cc: Zhi A Wang <zhi.a.wang@intel.com>
> Cc: Anuj Phogat <anuj.phogat@intel.com>

As a heads-up, as this adds to the uAPI, this needs Acked-by from the
respective userspace that will use the information, a link to the
userspace change series and IGT test series all linked from the patch
text.

But as we're hoping to stay at version 1, I also would see that we only
need to add this IOCTL if we get a version 2 of the tables. So there
should be no need for this interface before we have some variance.

Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread
* Re: [PATCH v2 2/2] drm/i915/icl: Add IOCTL for getting MOCS table version
  2018-10-22 18:18     ` Daniele Ceraolo Spurio
@ 2018-10-23 12:02       ` Lis, Tomasz
  0 siblings, 0 replies; 18+ messages in thread
From: Lis, Tomasz @ 2018-10-23 12:02 UTC (permalink / raw)
  To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Anuj Phogat, Mika Kuoppala



On 2018-10-22 20:18, Daniele Ceraolo Spurio wrote:
>
>
> On 22/10/18 10:13, Tomasz Lis wrote:
>> For Icelake and above, MOCS table for each platform is published
>> within bspec. The table is versioned, and new entries are assigned
>> a version number. Existing entries do not change and their version
>> is constant.
>>
>> This introduces a parameter which allows getting max version number
>> of the MOCS entries currently supported, ie. value of 2 would mean
>> only version 1 and version 2 entries are initialized and can be used
>> by the user mode clients.
>>
>> BSpec: 34007
>> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
>> Cc: Zhi A Wang <zhi.a.wang@intel.com>
>> Cc: Anuj Phogat <anuj.phogat@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_drv.c   |  6 ++++++
>>   drivers/gpu/drm/i915/intel_mocs.c | 12 ++++++++++++
>>   drivers/gpu/drm/i915/intel_mocs.h |  1 +
>>   include/uapi/drm/i915_drm.h       | 11 +++++++++++
>>   4 files changed, 30 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c 
>> b/drivers/gpu/drm/i915/i915_drv.c
>> index baac35f..92fa8fd 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -53,6 +53,7 @@
>>   #include "i915_vgpu.h"
>>   #include "intel_drv.h"
>>   #include "intel_uc.h"
>> +#include "intel_mocs.h"
>>     static struct drm_driver driver;
>>   @@ -444,6 +445,11 @@ static int i915_getparam_ioctl(struct 
>> drm_device *dev, void *data,
>>       case I915_PARAM_MMAP_GTT_COHERENT:
>>           value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
>>           break;
>> +    case I915_PARAM_MOCS_TABLE_VERSION:
>> +        value = intel_mocs_table_version(dev_priv);
>> +        if (!value)
>> +            return -ENODEV;
>
> Do we really want to return -ENODEV for platforms that do have a MOCS 
> table programmed, but the table is not one versioned in the specs 
> (i.e. Gen9-10)? I think returning "0" for those to indicate 
> "kernel-defined table" would be ok and we could limit -ENODEV for 
> platforms that don't have a table at all. But what wins is what the 
> callers of the ioctl would like to get from the kernel ;)
>
>> +        break;
>>       default:
>>           DRM_DEBUG("Unknown parameter %d\n", param->param);
>>           return -EINVAL;
>> diff --git a/drivers/gpu/drm/i915/intel_mocs.c 
>> b/drivers/gpu/drm/i915/intel_mocs.c
>> index dc34e83..fc1e98b 100644
>> --- a/drivers/gpu/drm/i915/intel_mocs.c
>> +++ b/drivers/gpu/drm/i915/intel_mocs.c
>> @@ -469,6 +469,18 @@ static i915_reg_t mocs_register(enum 
>> intel_engine_id engine_id, int index)
>>   }
>>     /**
>> + * intel_mocs_table_version() - get version of mocs table 
>> implementation
>> + * @i915: i915 device struct.
>> + */
>> +int intel_mocs_table_version(struct drm_i915_private *i915)
>> +{
>> +    if (IS_ICELAKE(i915))
>> +        return 1;
>
> Can we add this version value as a define above the table, to keep 
> them close to each other?
>
> If we agree on my suggestion above to differentiate between no table 
> at all (< 0), kernel-defined table (= 0) and spec-defined versioned 
> table (> 0), it might also be useful to store the version with the 
> table info in drm_i915_mocs_table and then have 
> intel_mocs_table_version call get_mocs_settings(), e.g:
>
> int intel_mocs_table_version(struct drm_i915_private *i915)
> {
>     struct drm_i915_mocs_table table;
>
>     if (!get_mocs_settings(i915, &table))
>         return -ENODEV;
>
>     return table->version;
> }
>
> Thanks,
> Daniele
That does sound reasonable. And I agree we should really ask userland 
what exactly they want.
Right now there is no request from any UMD for such interface; we will 
get back to this patch when it is requested.
Joonas also mentioned there is no need for an interface which always 
returns "1", and is expected to return only that value for future 
platforms as well. That's a good argument.

I will remove this patch from the current series.

-Tomasz
>
>> +    else
>> +        return 0;
>> +}
>> +
>> +/**
>>    * intel_mocs_init_engine() - emit the mocs control table
>>    * @engine:    The engine for whom to emit the registers.
>>    *
>> diff --git a/drivers/gpu/drm/i915/intel_mocs.h 
>> b/drivers/gpu/drm/i915/intel_mocs.h
>> index d89080d..dc1d64a 100644
>> --- a/drivers/gpu/drm/i915/intel_mocs.h
>> +++ b/drivers/gpu/drm/i915/intel_mocs.h
>> @@ -55,5 +55,6 @@
>>   int intel_rcs_context_init_mocs(struct i915_request *rq);
>>   void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv);
>>   void intel_mocs_init_engine(struct intel_engine_cs *engine);
>> +int intel_mocs_table_version(struct drm_i915_private *i915);
>>     #endif
>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
>> index 298b2e1..16aafc4 100644
>> --- a/include/uapi/drm/i915_drm.h
>> +++ b/include/uapi/drm/i915_drm.h
>> @@ -559,6 +559,17 @@ typedef struct drm_i915_irq_wait {
>>    */
>>   #define I915_PARAM_MMAP_GTT_COHERENT    52
>>   +/*
>> + * Query MOCS table version used during hardware initialization.
>> + *
>> + * The MOCS table for each platform is published as part of bspec. 
>> Entries in
>> + * the table are supposed to never be modified, but new enties are 
>> added, making
>> + * more indexes in the table valid. This parameter informs which 
>> version
>> + * of the table was used to initialize the currently used graphics 
>> hardware,
>> + * and therefore which MOCS indexes are useable.
>> + */
>> +#define I915_PARAM_MOCS_TABLE_VERSION    53
>> +
>>   typedef struct drm_i915_getparam {
>>       __s32 param;
>>       /*
>>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread
* Re: [PATCH v2 1/2] drm/i915/icl: Define MOCS table for Icelake
  2018-10-22 17:40   ` [PATCH v2 1/2] drm/i915/icl: Define MOCS table for Icelake Daniele Ceraolo Spurio
@ 2018-10-23 13:07     ` Lis, Tomasz
  0 siblings, 0 replies; 18+ messages in thread
From: Lis, Tomasz @ 2018-10-23 13:07 UTC (permalink / raw)
  To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Anuj Phogat, Mika Kuoppala



On 2018-10-22 19:40, Daniele Ceraolo Spurio wrote:
>
>
> On 22/10/18 10:13, Tomasz Lis wrote:
>> The table has been unified across OSes to minimize virtualization 
>> overhead.
>>
>> The MOCS table is now published as part of bspec, and versioned. Entries
>> are supposed to never be modified, but new ones can be added. Adding
>> entries increases table version. The patch includes version 1 entries.
>>
>> Meaning of each entry is now explained in bspec, and user mode clients
>> are expected to know what each entry means. The 3 entries used for 
>> previous
>> platforms are still compatible with their legacy definitions, but 
>> that is
>> not guaranteed to be true for future platforms.
>>
>> BSpec: 34007
>> BSpec: 560
>> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
>> Cc: Zhi A Wang <zhi.a.wang@intel.com>
>> Cc: Anuj Phogat <anuj.phogat@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_mocs.c | 246 
>> +++++++++++++++++++++++++++++++++++++-
>>   1 file changed, 244 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_mocs.c 
>> b/drivers/gpu/drm/i915/intel_mocs.c
>> index 77e9871..dc34e83 100644
>> --- a/drivers/gpu/drm/i915/intel_mocs.c
>> +++ b/drivers/gpu/drm/i915/intel_mocs.c
>> @@ -44,6 +44,8 @@ struct drm_i915_mocs_table {
>>   #define LE_SCC(value)        ((value) << 8)
>>   #define LE_PFM(value)        ((value) << 11)
>>   #define LE_SCF(value)        ((value) << 14)
>> +#define LE_CoS(value)        ((value) << 15)
>> +#define LE_SSE(value)        ((value) << 17)
>>     /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries 
>> per word */
>>   #define L3_ESC(value)        ((value) << 0)
>> @@ -96,6 +98,243 @@ struct drm_i915_mocs_table {
>>    *       may only be updated incrementally by adding entries at the
>>    *       end.
>>    */
>
> This comment needs to be updated as some of the expectations are not 
> true anymore, e.g. we're now defining entries 62 and 63 in SW, usage 
> of mocs 0 is changing. Also could be useful to add some of the info 
> you have in the commit message here, like the fact that the table is 
> versioned in the specs for gen11+, so it is close to the table.
>
> From a POV of following the specs, with the updated comments this is:
>
> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>
> But please get acks from the relevant interested parties to make sure 
> there are no concerns with the new approach.
I believe all parties are informed; will add some more cc's to v3.
> Also having someone else double-check the table as well would be nice 
> since I might have missed something and it's going to be hard to catch 
> issues in testing if the only impact is a very small performance delta.
>
> Thanks,
> Daniele
The IGT test for MOCS settings compares explicitly content of the 
registers with expected values hard-coded into that test; since someone 
else than me will be updating that test for correct Icelake values, we 
can count that as second verification.
-Tomasz
>
>> +static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
>> +    [0] = {
>> +      /* Base - Uncached (Deprecated) */
>> +      .control_value = LE_CACHEABILITY(LE_UC) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
>> +    },
>> +    [1] = {
>> +      /* Base - L3 + LeCC:PAT (Deprecated) */
>> +      .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
>> +    },
>> +    [2] = {
>> +      /* Base - L3 + LLC */
>> +      .control_value = LE_CACHEABILITY(LE_WB) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
>> +    },
>> +    [3] = {
>> +      /* Base - Uncached */
>> +      .control_value = LE_CACHEABILITY(LE_UC) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
>> +    },
>> +    [4] = {
>> +      /* Base - L3 */
>> +      .control_value = LE_CACHEABILITY(LE_UC) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
>> +    },
>> +    [5] = {
>> +      /* Base - LLC */
>> +      .control_value = LE_CACHEABILITY(LE_WB) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
>> +    },
>> +    [6] = {
>> +      /* Age 0 - LLC */
>> +      .control_value = LE_CACHEABILITY(LE_WB) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
>> +    },
>> +    [7] = {
>> +      /* Age 0 - L3 + LLC */
>> +      .control_value = LE_CACHEABILITY(LE_WB) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
>> +    },
>> +    [8] = {
>> +      /* Age: Don't Chg. - LLC */
>> +      .control_value = LE_CACHEABILITY(LE_WB) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
>> +    },
>> +    [9] = {
>> +      /* Age: Don't Chg. - L3 + LLC */
>> +      .control_value = LE_CACHEABILITY(LE_WB) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
>> +    },
>> +    [10] = {
>> +      /* No AOM - LLC */
>> +      .control_value = LE_CACHEABILITY(LE_WB) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
>> +    },
>> +    [11] = {
>> +      /* No AOM - L3 + LLC */
>> +      .control_value = LE_CACHEABILITY(LE_WB) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
>> +    },
>> +    [12] = {
>> +      /* No AOM; Age 0 - LLC */
>> +      .control_value = LE_CACHEABILITY(LE_WB) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
>> +    },
>> +    [13] = {
>> +      /* No AOM; Age 0 - L3 + LLC */
>> +      .control_value = LE_CACHEABILITY(LE_WB) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
>> +    },
>> +    [14] = {
>> +      /* No AOM; Age:DC - LLC */
>> +      .control_value = LE_CACHEABILITY(LE_WB) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
>> +    },
>> +    [15] = {
>> +      /* No AOM; Age:DC - L3 + LLC */
>> +      .control_value = LE_CACHEABILITY(LE_WB) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
>> +    },
>> +    [16] = {
>> +      /* Reserved - For future use */
>> +      .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
>> +               LE_TGT_CACHE(LE_TC_PAGETABLE) |
>> +               LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | 
>> L3_CACHEABILITY(L3_DIRECT),
>> +    },
>> +    [17] = {
>> +      /* Reserved - For future use */
>> +      .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
>> +               LE_TGT_CACHE(LE_TC_PAGETABLE) |
>> +               LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | 
>> L3_CACHEABILITY(L3_DIRECT),
>> +    },
>> +    [18] = {
>> +      /* Self-Snoop - L3 + LLC */
>> +      .control_value = LE_CACHEABILITY(LE_WB) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(3),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
>> +    },
>> +    [19] = {
>> +      /* Skip Caching - L3 + LLC(12.5%) */
>> +      .control_value = LE_CACHEABILITY(LE_WB) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(7) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
>> +    },
>> +    [20] = {
>> +      /* Skip Caching - L3 + LLC(25%) */
>> +      .control_value = LE_CACHEABILITY(LE_WB) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(3) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
>> +    },
>> +    [21] = {
>> +      /* Skip Caching - L3 + LLC(50%) */
>> +      .control_value = LE_CACHEABILITY(LE_WB) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(1) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
>> +    },
>> +    [22] = {
>> +      /* Skip Caching - L3 + LLC(75%) */
>> +      .control_value = LE_CACHEABILITY(LE_WB) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(3) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
>> +    },
>> +    [23] = {
>> +      /* Skip Caching - L3 + LLC(87.5%) */
>> +      .control_value = LE_CACHEABILITY(LE_WB) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(7) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
>> +    },
>> +    [62] = {
>> +      /* HW Reserved - SW program but never use */
>> +      .control_value = LE_CACHEABILITY(LE_WB) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
>> +    },
>> +    [63] = {
>> +      /* HW Reserved - SW program but never use */
>> +      .control_value = LE_CACHEABILITY(LE_WB) |
>> +               LE_TGT_CACHE(LE_TC_LLC) |
>> +               LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
>> +               LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
>> +
>> +      .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
>> +    },
>> +};
>> +
>>   static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
>>       [I915_MOCS_UNCACHED] = {
>>         /* 0x00000009 */
>> @@ -178,8 +417,11 @@ static bool get_mocs_settings(struct 
>> drm_i915_private *dev_priv,
>>   {
>>       bool result = false;
>>   -    if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) ||
>> -        IS_ICELAKE(dev_priv)) {
>> +    if (IS_ICELAKE(dev_priv)) {
>> +        table->size  = ARRAY_SIZE(icelake_mocs_table);
>> +        table->table = icelake_mocs_table;
>> +        result = true;
>> +    } else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>>           table->size  = ARRAY_SIZE(skylake_mocs_table);
>>           table->table = skylake_mocs_table;
>>           result = true;
>>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread
* [PATCH v3] drm/i915/icl: Define MOCS table for Icelake
  2018-10-19 15:19 [PATCH v1] drm/i915/icl: Define MOCS table for Icelake Tomasz Lis
                   ` (3 preceding siblings ...)
  2018-10-22 17:13 ` [PATCH v2 1/2] " Tomasz Lis
@ 2018-10-23 13:23 ` Tomasz Lis
  2018-10-23 14:02 ` ✗ Fi.CI.BAT: failure for drm/i915/icl: Define MOCS table for Icelake (rev4) Patchwork
                   ` (2 subsequent siblings)
  7 siblings, 0 replies; 18+ messages in thread
From: Tomasz Lis @ 2018-10-23 13:23 UTC (permalink / raw)
  To: intel-gfx; +Cc: Adam Cetnerowski, Piotr Rozenfeld, Anuj Phogat, Mika Kuoppala

The table has been unified across OSes to minimize virtualization overhead.

The MOCS table is now published as part of bspec, and versioned. Entries
are supposed to never be modified, but new ones can be added. Adding
entries increases table version. The patch includes version 1 entries.

Meaning of each entry is now explained in bspec, and user mode clients
are expected to know what each entry means. The 3 entries used for previous
platforms are still compatible with their legacy definitions, but that is
not guaranteed to be true for future platforms.

v2: Fixed SCC values, improved commit comment (Daniele)
v3: Improved MOCS table comment (Daniele)

BSpec: 34007
BSpec: 560
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi A Wang <zhi.a.wang@intel.com>
Cc: Anuj Phogat <anuj.phogat@intel.com>
Cc: Adam Cetnerowski <adam.cetnerowski@intel.com>
Cc: Piotr Rozenfeld <piotr.rozenfeld@intel.com>
---
 drivers/gpu/drm/i915/intel_mocs.c | 270 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 256 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 77e9871..b7f96cb 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -44,6 +44,8 @@ struct drm_i915_mocs_table {
 #define LE_SCC(value)		((value) << 8)
 #define LE_PFM(value)		((value) << 11)
 #define LE_SCF(value)		((value) << 14)
+#define LE_CoS(value)		((value) << 15)
+#define LE_SSE(value)		((value) << 17)
 
 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
 #define L3_ESC(value)		((value) << 0)
@@ -80,22 +82,259 @@ struct drm_i915_mocs_table {
  * LNCFCMOCS0 - LNCFCMOCS32 registers.
  *
  * These tables are intended to be kept reasonably consistent across
- * platforms. However some of the fields are not applicable to all of
- * them.
+ * HW platforms, and for ICL+, be identical across OSes. To achieve
+ * that, for Icelake and above, list of entries is published as part
+ * of bspec.
  *
  * Entries not part of the following tables are undefined as far as
- * userspace is concerned and shouldn't be relied upon.  For the time
- * being they will be implicitly initialized to the strictest caching
- * configuration (uncached) to guarantee forwards compatibility with
- * userspace programs written against more recent kernels providing
- * additional MOCS entries.
+ * userspace is concerned and shouldn't be relied upon.
  *
- * NOTE: These tables MUST start with being uncached and the length
- *       MUST be less than 63 as the last two registers are reserved
- *       by the hardware.  These tables are part of the kernel ABI and
- *       may only be updated incrementally by adding entries at the
- *       end.
+ * The last two entries are reserved by the hardware. For ICL+ they
+ * should be initialized according to bspec and never used, for older
+ * platforms they should never be written to.
+ *
+ * NOTE: These tables are part of bspec and defined as part of hardware
+ *       interface for ICL+. For older platforms, they are part of kernel
+ *       ABI. It is expected that existing entries will remain constant
+ *       and the tables will only be updated by adding new entries.
  */
+static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
+	[0] = {
+	  /* Base - Uncached (Deprecated) */
+	  .control_value = LE_CACHEABILITY(LE_UC) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[1] = {
+	  /* Base - L3 + LeCC:PAT (Deprecated) */
+	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[2] = {
+	  /* Base - L3 + LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[3] = {
+	  /* Base - Uncached */
+	  .control_value = LE_CACHEABILITY(LE_UC) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[4] = {
+	  /* Base - L3 */
+	  .control_value = LE_CACHEABILITY(LE_UC) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[5] = {
+	  /* Base - LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[6] = {
+	  /* Age 0 - LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[7] = {
+	  /* Age 0 - L3 + LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[8] = {
+	  /* Age: Don't Chg. - LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[9] = {
+	  /* Age: Don't Chg. - L3 + LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[10] = {
+	  /* No AOM - LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[11] = {
+	  /* No AOM - L3 + LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[12] = {
+	  /* No AOM; Age 0 - LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[13] = {
+	  /* No AOM; Age 0 - L3 + LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[14] = {
+	  /* No AOM; Age:DC - LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[15] = {
+	  /* No AOM; Age:DC - L3 + LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[16] = {
+	  /* Reserved - For future use */
+	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
+			   LE_TGT_CACHE(LE_TC_PAGETABLE) |
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT),
+	},
+	[17] = {
+	  /* Reserved - For future use */
+	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
+			   LE_TGT_CACHE(LE_TC_PAGETABLE) |
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT),
+	},
+	[18] = {
+	  /* Self-Snoop - L3 + LLC */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(3),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[19] = {
+	  /* Skip Caching - L3 + LLC(12.5%) */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(7) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[20] = {
+	  /* Skip Caching - L3 + LLC(25%) */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(3) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[21] = {
+	  /* Skip Caching - L3 + LLC(50%) */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(1) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[22] = {
+	  /* Skip Caching - L3 + LLC(75%) */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(3) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[23] = {
+	  /* Skip Caching - L3 + LLC(87.5%) */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(7) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+	},
+	[62] = {
+	  /* HW Reserved - SW program but never use */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+	[63] = {
+	  /* HW Reserved - SW program but never use */
+	  .control_value = LE_CACHEABILITY(LE_WB) |
+			   LE_TGT_CACHE(LE_TC_LLC) |
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
+	},
+};
+
 static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
 	[I915_MOCS_UNCACHED] = {
 	  /* 0x00000009 */
@@ -178,8 +417,11 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
 {
 	bool result = false;
 
-	if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) ||
-	    IS_ICELAKE(dev_priv)) {
+	if (IS_ICELAKE(dev_priv)) {
+		table->size  = ARRAY_SIZE(icelake_mocs_table);
+		table->table = icelake_mocs_table;
+		result = true;
+	} else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 		table->size  = ARRAY_SIZE(skylake_mocs_table);
 		table->table = skylake_mocs_table;
 		result = true;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 18+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/icl: Define MOCS table for Icelake (rev4)
  2018-10-19 15:19 [PATCH v1] drm/i915/icl: Define MOCS table for Icelake Tomasz Lis
                   ` (4 preceding siblings ...)
  2018-10-23 13:23 ` [PATCH v3] " Tomasz Lis
@ 2018-10-23 14:02 ` Patchwork
  2018-10-26 15:32 ` [PATCH v4 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Tomasz Lis
  2018-10-31 21:57 ` [PATCH v1] drm/i915/icl: Define MOCS table for Icelake Lucas De Marchi
  7 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2018-10-23 14:02 UTC (permalink / raw)
  To: Tomasz Lis; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/icl: Define MOCS table for Icelake (rev4)
URL   : https://patchwork.freedesktop.org/series/51258/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_5020 -> Patchwork_10544 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10544 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10544, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/51258/revisions/4/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10544:

  === IGT changes ===

    ==== Possible regressions ====

    igt@pm_rpm@module-reload:
      fi-apl-guc:         PASS -> DMESG-WARN +4

    
    ==== Warnings ====

    igt@pm_rpm@basic-pci-d3-state:
      fi-apl-guc:         PASS -> SKIP +4

    
== Known issues ==

  Here are the changes found in Patchwork_10544 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_selftest@live_hangcheck:
      fi-kbl-7560u:       PASS -> INCOMPLETE (fdo#108044)

    igt@kms_flip@basic-flip-vs-modeset:
      fi-skl-6700hq:      PASS -> DMESG-WARN (fdo#105998)

    
    ==== Possible fixes ====

    igt@kms_frontbuffer_tracking@basic:
      fi-hsw-peppy:       DMESG-WARN (fdo#102614) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-byt-clapper:     FAIL (fdo#107362, fdo#103191) -> PASS +1

    igt@prime_vgem@basic-fence-flip:
      fi-cfl-8700k:       FAIL (fdo#104008) -> PASS

    
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
  fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#108044 https://bugs.freedesktop.org/show_bug.cgi?id=108044


== Participating hosts (47 -> 43) ==

  Additional (1): fi-cfl-8109u 
  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 


== Build changes ==

    * Linux: CI_DRM_5020 -> Patchwork_10544

  CI_DRM_5020: 95151c25e0433a2fe771b8bc272f3f8fb54a7e27 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4686: 741bf7064c467df725c14cc0b3b8b50436f9ee09 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10544: e4898ee712c0087f302391891e6ad493718ae1ae @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

e4898ee712c0 drm/i915/icl: Define MOCS table for Icelake

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10544/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread
* [PATCH v4 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
  2018-10-19 15:19 [PATCH v1] drm/i915/icl: Define MOCS table for Icelake Tomasz Lis
                   ` (5 preceding siblings ...)
  2018-10-23 14:02 ` ✗ Fi.CI.BAT: failure for drm/i915/icl: Define MOCS table for Icelake (rev4) Patchwork
@ 2018-10-26 15:32 ` Tomasz Lis
  2018-10-26 15:32   ` [PATCH v4 2/2] drm/i915/icl: Define MOCS table for Icelake Tomasz Lis
  2018-10-26 16:42   ` [PATCH v4 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Lucas De Marchi
  2018-10-31 21:57 ` [PATCH v1] drm/i915/icl: Define MOCS table for Icelake Lucas De Marchi
  7 siblings, 2 replies; 18+ messages in thread
From: Tomasz Lis @ 2018-10-26 15:32 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

The MOCS tables are going to be very similar across platforms.

To reduce the amount of copied code, this patch rips the common part and
puts it into a definition valid for all gen9 platforms.

Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/intel_mocs.c | 61 ++++++++++++++-------------------------
 1 file changed, 22 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 77e9871..76aed59 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -96,26 +96,29 @@ struct drm_i915_mocs_table {
  *       may only be updated incrementally by adding entries at the
  *       end.
  */
-static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
-	[I915_MOCS_UNCACHED] = {
-	  /* 0x00000009 */
-	  .control_value = LE_CACHEABILITY(LE_UC) |
-			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
-			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
-			   LE_PFM(0) | LE_SCF(0),
 
-	  /* 0x0010 */
-	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
-	},
-	[I915_MOCS_PTE] = {
-	  /* 0x00000038 */
-	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
-			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
-			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
-			   LE_PFM(0) | LE_SCF(0),
-	  /* 0x0030 */
-	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
+#define GEN9_MOCS_TABLE \
+	[I915_MOCS_UNCACHED] = { \
+	  /* 0x00000009 */ \
+	  .control_value = LE_CACHEABILITY(LE_UC) | \
+			   LE_TGT_CACHE(LE_TC_LLC_ELLC) | \
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+			   LE_PFM(0) | LE_SCF(0), \
+	  /* 0x0010 */ \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+	}, \
+	[I915_MOCS_PTE] = { \
+	  /* 0x00000038 */ \
+	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) | \
+			   LE_TGT_CACHE(LE_TC_LLC_ELLC) | \
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+			   LE_PFM(0) | LE_SCF(0), \
+	  /* 0x0030 */ \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
 	},
+
+static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
+	GEN9_MOCS_TABLE
 	[I915_MOCS_CACHED] = {
 	  /* 0x0000003b */
 	  .control_value = LE_CACHEABILITY(LE_WB) |
@@ -129,33 +132,13 @@ static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
 
 /* NOTE: the LE_TGT_CACHE is not used on Broxton */
 static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
-	[I915_MOCS_UNCACHED] = {
-	  /* 0x00000009 */
-	  .control_value = LE_CACHEABILITY(LE_UC) |
-			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
-			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
-			   LE_PFM(0) | LE_SCF(0),
-
-	  /* 0x0010 */
-	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
-	},
-	[I915_MOCS_PTE] = {
-	  /* 0x00000038 */
-	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
-			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
-			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
-			   LE_PFM(0) | LE_SCF(0),
-
-	  /* 0x0030 */
-	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
-	},
+	GEN9_MOCS_TABLE
 	[I915_MOCS_CACHED] = {
 	  /* 0x00000039 */
 	  .control_value = LE_CACHEABILITY(LE_UC) |
 			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
 			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
 			   LE_PFM(0) | LE_SCF(0),
-
 	  /* 0x0030 */
 	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
 	},
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 18+ messages in thread
* [PATCH v4 2/2] drm/i915/icl: Define MOCS table for Icelake
  2018-10-26 15:32 ` [PATCH v4 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Tomasz Lis
@ 2018-10-26 15:32   ` Tomasz Lis
  2018-10-26 16:42   ` [PATCH v4 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Lucas De Marchi
  1 sibling, 0 replies; 18+ messages in thread
From: Tomasz Lis @ 2018-10-26 15:32 UTC (permalink / raw)
  To: intel-gfx
  Cc: Adam Cetnerowski, Piotr Rozenfeld, Lucas De Marchi, Anuj Phogat,
	Mika Kuoppala

The table has been unified across OSes to minimize virtualization overhead.

The MOCS table is now published as part of bspec, and versioned. Entries
are supposed to never be modified, but new ones can be added. Adding
entries increases table version. The patch includes version 1 entries.

Meaning of each entry is now explained in bspec, and user mode clients
are expected to know what each entry means. The 3 entries used for previous
platforms are still compatible with their legacy definitions, but that is
not guaranteed to be true for future platforms.

v2: Fixed SCC values, improved commit comment (Daniele)
v3: Improved MOCS table comment (Daniele)
v4: Moved new entries below gen9 ones. Put common entries into
    definition to be used in multiple arrays. (Lucas)

BSpec: 34007
BSpec: 560
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> (v3)
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi A Wang <zhi.a.wang@intel.com>
Cc: Anuj Phogat <anuj.phogat@intel.com>
Cc: Adam Cetnerowski <adam.cetnerowski@intel.com>
Cc: Piotr Rozenfeld <piotr.rozenfeld@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/intel_mocs.c | 249 +++++++++++++++++++++++++++++++++++---
 1 file changed, 235 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 76aed59..2a1e5f0 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -44,6 +44,8 @@ struct drm_i915_mocs_table {
 #define LE_SCC(value)		((value) << 8)
 #define LE_PFM(value)		((value) << 11)
 #define LE_SCF(value)		((value) << 14)
+#define LE_CoS(value)		((value) << 15)
+#define LE_SSE(value)		((value) << 17)
 
 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
 #define L3_ESC(value)		((value) << 0)
@@ -80,21 +82,21 @@ struct drm_i915_mocs_table {
  * LNCFCMOCS0 - LNCFCMOCS32 registers.
  *
  * These tables are intended to be kept reasonably consistent across
- * platforms. However some of the fields are not applicable to all of
- * them.
+ * HW platforms, and for ICL+, be identical across OSes. To achieve
+ * that, for Icelake and above, list of entries is published as part
+ * of bspec.
  *
  * Entries not part of the following tables are undefined as far as
- * userspace is concerned and shouldn't be relied upon.  For the time
- * being they will be implicitly initialized to the strictest caching
- * configuration (uncached) to guarantee forwards compatibility with
- * userspace programs written against more recent kernels providing
- * additional MOCS entries.
+ * userspace is concerned and shouldn't be relied upon.
  *
- * NOTE: These tables MUST start with being uncached and the length
- *       MUST be less than 63 as the last two registers are reserved
- *       by the hardware.  These tables are part of the kernel ABI and
- *       may only be updated incrementally by adding entries at the
- *       end.
+ * The last two entries are reserved by the hardware. For ICL+ they
+ * should be initialized according to bspec and never used, for older
+ * platforms they should never be written to.
+ *
+ * NOTE: These tables are part of bspec and defined as part of hardware
+ *       interface for ICL+. For older platforms, they are part of kernel
+ *       ABI. It is expected that existing entries will remain constant
+ *       and the tables will only be updated by adding new entries.
  */
 
 #define GEN9_MOCS_TABLE \
@@ -144,6 +146,222 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
 	},
 };
 
+#define GEN11_MOCS_TABLE \
+	[0] = { \
+	  /* Base - Uncached (Deprecated) */ \
+	  .control_value = LE_CACHEABILITY(LE_UC) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+	}, \
+	[1] = { \
+	  /* Base - L3 + LeCC:PAT (Deprecated) */ \
+	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+	}, \
+	[2] = { \
+	  /* Base - L3 + LLC */ \
+	  .control_value = LE_CACHEABILITY(LE_WB) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+	}, \
+	[3] = { \
+	  /* Base - Uncached */ \
+	  .control_value = LE_CACHEABILITY(LE_UC) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+	}, \
+	[4] = { \
+	  /* Base - L3 */ \
+	  .control_value = LE_CACHEABILITY(LE_UC) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+	}, \
+	[5] = { \
+	  /* Base - LLC */ \
+	  .control_value = LE_CACHEABILITY(LE_WB) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+	}, \
+	[6] = { \
+	  /* Age 0 - LLC */ \
+	  .control_value = LE_CACHEABILITY(LE_WB) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+	}, \
+	[7] = { \
+	  /* Age 0 - L3 + LLC */ \
+	  .control_value = LE_CACHEABILITY(LE_WB) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+	}, \
+	[8] = { \
+	  /* Age: Don't Chg. - LLC */ \
+	  .control_value = LE_CACHEABILITY(LE_WB) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+	}, \
+	[9] = { \
+	  /* Age: Don't Chg. - L3 + LLC */ \
+	  .control_value = LE_CACHEABILITY(LE_WB) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+	}, \
+	[10] = { \
+	  /* No AOM - LLC */ \
+	  .control_value = LE_CACHEABILITY(LE_WB) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+	}, \
+	[11] = { \
+	  /* No AOM - L3 + LLC */ \
+	  .control_value = LE_CACHEABILITY(LE_WB) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+	}, \
+	[12] = { \
+	  /* No AOM; Age 0 - LLC */ \
+	  .control_value = LE_CACHEABILITY(LE_WB) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+	}, \
+	[13] = { \
+	  /* No AOM; Age 0 - L3 + LLC */ \
+	  .control_value = LE_CACHEABILITY(LE_WB) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+	}, \
+	[14] = { \
+	  /* No AOM; Age:DC - LLC */ \
+	  .control_value = LE_CACHEABILITY(LE_WB) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+	}, \
+	[15] = { \
+	  /* No AOM; Age:DC - L3 + LLC */ \
+	  .control_value = LE_CACHEABILITY(LE_WB) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+	}, \
+	[18] = { \
+	  /* Self-Snoop - L3 + LLC */ \
+	  .control_value = LE_CACHEABILITY(LE_WB) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(3), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+	}, \
+	[19] = { \
+	  /* Skip Caching - L3 + LLC(12.5%) */ \
+	  .control_value = LE_CACHEABILITY(LE_WB) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(7) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+	}, \
+	[20] = { \
+	  /* Skip Caching - L3 + LLC(25%) */ \
+	  .control_value = LE_CACHEABILITY(LE_WB) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(3) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+	}, \
+	[21] = { \
+	  /* Skip Caching - L3 + LLC(50%) */ \
+	  .control_value = LE_CACHEABILITY(LE_WB) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(1) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+	}, \
+	[22] = { \
+	  /* Skip Caching - L3 + LLC(75%) */ \
+	  .control_value = LE_CACHEABILITY(LE_WB) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(3) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+	}, \
+	[23] = { \
+	  /* Skip Caching - L3 + LLC(87.5%) */ \
+	  .control_value = LE_CACHEABILITY(LE_WB) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(7) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
+	}, \
+	[62] = { \
+	  /* HW Reserved - SW program but never use */ \
+	  .control_value = LE_CACHEABILITY(LE_WB) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+	}, \
+	[63] = { \
+	  /* HW Reserved - SW program but never use */ \
+	  .control_value = LE_CACHEABILITY(LE_WB) | \
+			   LE_TGT_CACHE(LE_TC_LLC) | \
+			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0), \
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
+	},
+
+static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
+	GEN11_MOCS_TABLE
+	[16] = {
+	  /* Reserved - For future use */
+	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
+			   LE_TGT_CACHE(LE_TC_PAGETABLE) |
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT),
+	},
+	[17] = {
+	  /* Reserved - For future use */
+	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
+			   LE_TGT_CACHE(LE_TC_PAGETABLE) |
+			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
+			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
+
+	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT),
+	},
+};
+
 /**
  * get_mocs_settings()
  * @dev_priv:	i915 device.
@@ -161,8 +379,11 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
 {
 	bool result = false;
 
-	if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) ||
-	    IS_ICELAKE(dev_priv)) {
+	if (IS_ICELAKE(dev_priv)) {
+		table->size  = ARRAY_SIZE(icelake_mocs_table);
+		table->table = icelake_mocs_table;
+		result = true;
+	} else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 		table->size  = ARRAY_SIZE(skylake_mocs_table);
 		table->table = skylake_mocs_table;
 		result = true;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 18+ messages in thread
* Re: [PATCH v4 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define
  2018-10-26 15:32 ` [PATCH v4 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Tomasz Lis
  2018-10-26 15:32   ` [PATCH v4 2/2] drm/i915/icl: Define MOCS table for Icelake Tomasz Lis
@ 2018-10-26 16:42   ` Lucas De Marchi
  1 sibling, 0 replies; 18+ messages in thread
From: Lucas De Marchi @ 2018-10-26 16:42 UTC (permalink / raw)
  To: Tomasz Lis; +Cc: intel-gfx

On Fri, Oct 26, 2018 at 05:32:45PM +0200, Tomasz Lis wrote:
> The MOCS tables are going to be very similar across platforms.
> 
> To reduce the amount of copied code, this patch rips the common part and
> puts it into a definition valid for all gen9 platforms.
> 
> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>

yeah, this is what I was suggesting.

Not sure if in future this will blow out of proportion - we need to remember that each
table is 64 entries of this struct in the ro section. If this happens, then maybe we
will need to change the approach and move the idx inside the entry rather than 64-entry
arrays.  I think this can be left for later if/when there's need.

Right now this improves the status quo IMO.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

thanks
Lucas De Marchi

> ---
>  drivers/gpu/drm/i915/intel_mocs.c | 61 ++++++++++++++-------------------------
>  1 file changed, 22 insertions(+), 39 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index 77e9871..76aed59 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -96,26 +96,29 @@ struct drm_i915_mocs_table {
>   *       may only be updated incrementally by adding entries at the
>   *       end.
>   */
> -static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
> -	[I915_MOCS_UNCACHED] = {
> -	  /* 0x00000009 */
> -	  .control_value = LE_CACHEABILITY(LE_UC) |
> -			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
> -			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> -			   LE_PFM(0) | LE_SCF(0),
>  
> -	  /* 0x0010 */
> -	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> -	},
> -	[I915_MOCS_PTE] = {
> -	  /* 0x00000038 */
> -	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
> -			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
> -			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> -			   LE_PFM(0) | LE_SCF(0),
> -	  /* 0x0030 */
> -	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +#define GEN9_MOCS_TABLE \
> +	[I915_MOCS_UNCACHED] = { \
> +	  /* 0x00000009 */ \
> +	  .control_value = LE_CACHEABILITY(LE_UC) | \
> +			   LE_TGT_CACHE(LE_TC_LLC_ELLC) | \
> +			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
> +			   LE_PFM(0) | LE_SCF(0), \
> +	  /* 0x0010 */ \
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), \
> +	}, \
> +	[I915_MOCS_PTE] = { \
> +	  /* 0x00000038 */ \
> +	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) | \
> +			   LE_TGT_CACHE(LE_TC_LLC_ELLC) | \
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | \
> +			   LE_PFM(0) | LE_SCF(0), \
> +	  /* 0x0030 */ \
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), \
>  	},
> +
> +static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
> +	GEN9_MOCS_TABLE
>  	[I915_MOCS_CACHED] = {
>  	  /* 0x0000003b */
>  	  .control_value = LE_CACHEABILITY(LE_WB) |
> @@ -129,33 +132,13 @@ static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
>  
>  /* NOTE: the LE_TGT_CACHE is not used on Broxton */
>  static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
> -	[I915_MOCS_UNCACHED] = {
> -	  /* 0x00000009 */
> -	  .control_value = LE_CACHEABILITY(LE_UC) |
> -			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
> -			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> -			   LE_PFM(0) | LE_SCF(0),
> -
> -	  /* 0x0010 */
> -	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> -	},
> -	[I915_MOCS_PTE] = {
> -	  /* 0x00000038 */
> -	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
> -			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
> -			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> -			   LE_PFM(0) | LE_SCF(0),
> -
> -	  /* 0x0030 */
> -	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> -	},
> +	GEN9_MOCS_TABLE
>  	[I915_MOCS_CACHED] = {
>  	  /* 0x00000039 */
>  	  .control_value = LE_CACHEABILITY(LE_UC) |
>  			   LE_TGT_CACHE(LE_TC_LLC_ELLC) |
>  			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
>  			   LE_PFM(0) | LE_SCF(0),
> -
>  	  /* 0x0030 */
>  	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
>  	},
> -- 
> 2.7.4
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread
* Re: [PATCH v1] drm/i915/icl: Define MOCS table for Icelake
  2018-10-19 15:19 [PATCH v1] drm/i915/icl: Define MOCS table for Icelake Tomasz Lis
                   ` (6 preceding siblings ...)
  2018-10-26 15:32 ` [PATCH v4 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Tomasz Lis
@ 2018-10-31 21:57 ` Lucas De Marchi
  7 siblings, 0 replies; 18+ messages in thread
From: Lucas De Marchi @ 2018-10-31 21:57 UTC (permalink / raw)
  To: Tomasz Lis; +Cc: intel-gfx, Mika Kuoppala

On Fri, Oct 19, 2018 at 05:19:28PM +0200, Tomasz Lis wrote:
> The table has been unified across OSes to minimize virtualization overhead.
> 
> The MOCS table is now versioned; the patch includes version 1 entries.
> 
> BSpec: 34007
> BSpec: 560
> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> ---

Can you please resubmit this series with only the patches not dropped?
This currently fails CI as CI is adding/dropping patches:
https://patchwork.freedesktop.org/series/51258/

Lucas De Marchi

>  drivers/gpu/drm/i915/intel_mocs.c | 246 +++++++++++++++++++++++++++++++++++++-
>  1 file changed, 244 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index 77e9871..b76d6db 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -44,6 +44,8 @@ struct drm_i915_mocs_table {
>  #define LE_SCC(value)		((value) << 8)
>  #define LE_PFM(value)		((value) << 11)
>  #define LE_SCF(value)		((value) << 14)
> +#define LE_CoS(value)		((value) << 15)
> +#define LE_SSE(value)		((value) << 17)
>  
>  /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
>  #define L3_ESC(value)		((value) << 0)
> @@ -96,6 +98,243 @@ struct drm_i915_mocs_table {
>   *       may only be updated incrementally by adding entries at the
>   *       end.
>   */
> +static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
> +	[0] = {
> +	  /* Base - Uncached (Deprecated) */
> +	  .control_value = LE_CACHEABILITY(LE_UC) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[1] = {
> +	  /* Base - L3 + LeCC:PAT (Deprecated) */
> +	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[2] = {
> +	  /* Base - L3 + LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[3] = {
> +	  /* Base - Uncached */
> +	  .control_value = LE_CACHEABILITY(LE_UC) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[4] = {
> +	  /* Base - L3 */
> +	  .control_value = LE_CACHEABILITY(LE_UC) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[5] = {
> +	  /* Base - LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[6] = {
> +	  /* Age 0 - LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[7] = {
> +	  /* Age 0 - L3 + LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(1) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[8] = {
> +	  /* Age: Don't Chg. - LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[9] = {
> +	  /* Age: Don't Chg. - L3 + LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(2) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[10] = {
> +	  /* No AOM - LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[11] = {
> +	  /* No AOM - L3 + LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[12] = {
> +	  /* No AOM; Age 0 - LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[13] = {
> +	  /* No AOM; Age 0 - L3 + LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(1) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[14] = {
> +	  /* No AOM; Age:DC - LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[15] = {
> +	  /* No AOM; Age:DC - L3 + LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(2) | LE_AOM(1) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[16] = {
> +	  /* Reserved - For future use */
> +	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
> +			   LE_TGT_CACHE(LE_TC_PAGETABLE) |
> +			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT),
> +	},
> +	[17] = {
> +	  /* Reserved - For future use */
> +	  .control_value = LE_CACHEABILITY(LE_PAGETABLE) |
> +			   LE_TGT_CACHE(LE_TC_PAGETABLE) |
> +			   LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_DIRECT),
> +	},
> +	[18] = {
> +	  /* Self-Snoop - L3 + LLC */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(3),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[19] = {
> +	  /* Skip Caching - L3 + LLC(12.5%) */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[20] = {
> +	  /* Skip Caching - L3 + LLC(25%) */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[21] = {
> +	  /* Skip Caching - L3 + LLC(50%) */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[22] = {
> +	  /* Skip Caching - L3 + LLC(75%) */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[23] = {
> +	  /* Skip Caching - L3 + LLC(87.5%) */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(1) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB),
> +	},
> +	[62] = {
> +	  /* HW Reserved - SW program but never use */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +	[63] = {
> +	  /* HW Reserved - SW program but never use */
> +	  .control_value = LE_CACHEABILITY(LE_WB) |
> +			   LE_TGT_CACHE(LE_TC_LLC) |
> +			   LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) |
> +			   LE_PFM(0) | LE_SCF(0) | LE_CoS(0) | LE_SSE(0),
> +
> +	  .l3cc_value =    L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC),
> +	},
> +};
> +
>  static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
>  	[I915_MOCS_UNCACHED] = {
>  	  /* 0x00000009 */
> @@ -178,8 +417,11 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
>  {
>  	bool result = false;
>  
> -	if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) ||
> -	    IS_ICELAKE(dev_priv)) {
> +	if (IS_ICELAKE(dev_priv)) {
> +		table->size  = ARRAY_SIZE(icelake_mocs_table);
> +		table->table = icelake_mocs_table;
> +		result = true;
> +	} else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>  		table->size  = ARRAY_SIZE(skylake_mocs_table);
>  		table->table = skylake_mocs_table;
>  		result = true;
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread
end of thread, other threads:[~2018-10-31 21:58 UTC | newest]

Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-19 15:19 [PATCH v1] drm/i915/icl: Define MOCS table for Icelake Tomasz Lis
2018-10-19 16:19 ` Daniele Ceraolo Spurio
2018-10-19 16:23   ` Lionel Landwerlin
2018-10-22 12:42 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-10-22 15:15 ` ✓ Fi.CI.IGT: " Patchwork
2018-10-22 17:13 ` [PATCH v2 1/2] " Tomasz Lis
2018-10-22 17:13   ` [PATCH v2 2/2] drm/i915/icl: Add IOCTL for getting MOCS table version Tomasz Lis
2018-10-22 18:18     ` Daniele Ceraolo Spurio
2018-10-23 12:02       ` Lis, Tomasz
2018-10-23  9:06     ` Joonas Lahtinen
2018-10-22 17:40   ` [PATCH v2 1/2] drm/i915/icl: Define MOCS table for Icelake Daniele Ceraolo Spurio
2018-10-23 13:07     ` Lis, Tomasz
2018-10-23 13:23 ` [PATCH v3] " Tomasz Lis
2018-10-23 14:02 ` ✗ Fi.CI.BAT: failure for drm/i915/icl: Define MOCS table for Icelake (rev4) Patchwork
2018-10-26 15:32 ` [PATCH v4 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Tomasz Lis
2018-10-26 15:32   ` [PATCH v4 2/2] drm/i915/icl: Define MOCS table for Icelake Tomasz Lis
2018-10-26 16:42   ` [PATCH v4 1/2] drm/i915/skl: Rework MOCS tables to keep common part in a define Lucas De Marchi
2018-10-31 21:57 ` [PATCH v1] drm/i915/icl: Define MOCS table for Icelake Lucas De Marchi

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.