From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DB5AC67863 for ; Wed, 24 Oct 2018 07:53:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2530B20832 for ; Wed, 24 Oct 2018 07:53:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2530B20832 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=topic.nl Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727674AbeJXQUO (ORCPT ); Wed, 24 Oct 2018 12:20:14 -0400 Received: from atl4mhob13.registeredsite.com ([209.17.115.51]:51832 "EHLO atl4mhob13.registeredsite.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726832AbeJXQUO (ORCPT ); Wed, 24 Oct 2018 12:20:14 -0400 Received: from mailpod.hostingplatform.com (atl4qobmail03pod0.registeredsite.com [10.30.71.205]) by atl4mhob13.registeredsite.com (8.14.4/8.14.4) with ESMTP id w9O7rAOV022222 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Wed, 24 Oct 2018 03:53:10 -0400 Received: (qmail 14926 invoked by uid 0); 24 Oct 2018 07:53:09 -0000 X-TCPREMOTEIP: 81.173.50.109 X-Authenticated-UID: mike@milosoftware.com Received: from unknown (HELO mikebuntu.TOPIC.LOCAL) (mike@milosoftware.com@81.173.50.109) by 0 with ESMTPA; 24 Oct 2018 07:53:09 -0000 From: Mike Looijmans To: linux-fpga@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, michal.simek@xilinx.com, mdf@kernel.org, atull@kernel.org, git@xilinx.com, Mike Looijmans Subject: [PATCH v2] zynq-fpga: Only route PR via PCAP when required Date: Wed, 24 Oct 2018 09:53:03 +0200 Message-Id: <1540367583-5413-1-git-send-email-mike.looijmans@topic.nl> X-Mailer: git-send-email 1.9.1 References: <1540276279-2903-1-git-send-email-mike.looijmans@topic.nl> In-Reply-To: <1540276279-2903-1-git-send-email-mike.looijmans@topic.nl> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Xilinx Zynq FPGA driver takes ownership of the PR interface, making it impossible to use the ICAP interface for partial reconfiguration. This patch changes the driver to only activate PR over PCAP while the device is actively being accessed by the driver for programming. This allows both PCAP and ICAP interfaces to be used for PR. Signed-off-by: Mike Looijmans Reviewed-by: Moritz Fischer --- v2: Move the register setting in between the clock enable/disable drivers/fpga/zynq-fpga.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index 3110e00..ff3a427 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -501,6 +501,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, if (err) return err; + /* Release 'PR' control back to the ICAP */ + zynq_fpga_write(priv, CTRL_OFFSET, + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); + err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status, intr_status & IXR_PCFG_DONE_MASK, INIT_POLL_DELAY, -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: mike.looijmans@topic.nl (Mike Looijmans) Date: Wed, 24 Oct 2018 09:53:03 +0200 Subject: [PATCH v2] zynq-fpga: Only route PR via PCAP when required In-Reply-To: <1540276279-2903-1-git-send-email-mike.looijmans@topic.nl> References: <1540276279-2903-1-git-send-email-mike.looijmans@topic.nl> Message-ID: <1540367583-5413-1-git-send-email-mike.looijmans@topic.nl> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org The Xilinx Zynq FPGA driver takes ownership of the PR interface, making it impossible to use the ICAP interface for partial reconfiguration. This patch changes the driver to only activate PR over PCAP while the device is actively being accessed by the driver for programming. This allows both PCAP and ICAP interfaces to be used for PR. Signed-off-by: Mike Looijmans Reviewed-by: Moritz Fischer --- v2: Move the register setting in between the clock enable/disable drivers/fpga/zynq-fpga.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index 3110e00..ff3a427 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -501,6 +501,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, if (err) return err; + /* Release 'PR' control back to the ICAP */ + zynq_fpga_write(priv, CTRL_OFFSET, + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); + err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status, intr_status & IXR_PCFG_DONE_MASK, INIT_POLL_DELAY, -- 1.9.1