[PATCH v6 00/33] staging: mt7621-pci: Parse ports info from DT and other minor cleanups

[PATCH v6 00/33] staging: mt7621-pci: Parse ports info from DT and other minor cleanups

[Sergio Paracuellos]

This patch series parse remaining port info from device tree storing
it in mt7621_pcie_port struct created for this. It also performs a lot
of cleanups to get the driver in a good shape to give it a try to get
mainlined. All of this changes are only compile-tested.

Cleanups performed here:
    - Style cleanups.
    - Use PERST_N instead of GPIO control.
    - Remove not used macros.
    - Use kernel reset_control functions.
    - Remove unused code.

Changes in v6:
    - PATCHES 18-33 added:
        * Review defines and macros and create some news to get code more
          readable.
        * Avoid globals.
        * Factor out new 'mt7621_pcie_enable_port' and 'mt7621_pcie_enable_ports'
          functions.
        * Use PERST_N instead of GPIO control.
        * Use msleep instead of mdelay.
    - Rebased onto staging-next

Changes in v5:
    - Patch 18 removed from the series. Already submited by Mamta Shukla (also applied)
    - Rebased onto staging-next

Changes in v4:
    - Some patches of this series was previously added to staging.
    - Rebased onto staging-next.

Changes in v3:
    - 'mt7621_pcie_enable_port' now returns an error instead of void
      to avoid a layering violation.
    - Delete 'mt7621_pcie_port_free' function and just delete
      port from the list in probe function.
    - Use parent node to get base address registers for each port.

Changes in v2:
    - Rewrite phy part of the driver
    - fix some checkpatch complains
    - make use of sysctl from DT

Hope this helps.

Best regards,
    Sergio Paracuellos

Sergio Paracuellos (33):
  staging: mt7621-pci: parse and init port data from device tree
  staging: mt7621-pci: replace return value if
    devm_pci_alloc_host_bridge call fails
  staging: mt7621-pci: add two helpers for read and write pcie register
    ports
  staging: mt7621-pci: factor out 'mt7621_pcie_enable_port' function
  staging: mt7621-pci: remove [ASSERT|DEASSERT]_SYSRST_PCIE macros
  staging: mt7621-pci: remove GPL2+ text from license header
  staging: mt7621-pci: remove two commented code lines
  staging: mt7621-pci: remove reset related unused macros
  staging: mt7621-pci: reagroup reset related macros all together
  staging: mt7621-pci: rewrite pcie phy related functions
  staging: mt7621-pci: factor out 'mt7621_enable_phy' function
  staging: mt7621-pci: debug port N_FTS inside 'mt7621_pcie_enable_port'
  staging: mt7621-pci: rename 'mt7621_pcie_enable_port' into
    'mt7621_pcie_init_port'
  staging: mt7621-dts: add sysctl registers base address to pcie
  staging: mt7621-pci: remap and use sysctl from device tree
  staging: mt7621-pci: use a trailing */ on a separate line
  staging: mt7621-pci: use dev_* functions instead of printk
  staging: mt7621-pci: factor out 'mt7621_pcie_enable_ports' function
  staging: mt7621-pci: avoid use of global variable 'pcie_link_status'
  staging: mt7621-pci: factor out 'mt7621_pcie_init_ports' function
  staging: mt7621-pci: remove unused preprocessor definitions
  staging: mt7621-pci: reorder preprocessor definitions
  staging: mt7621-pci: remove non sense comment
  staging: mt7621-pci: align function definition style along the code
  staging: mt7621-pci: rewrite RC FTS configuration
  staging: mt7621-pci: rewrite hardcoded code for enabling ports
  staging: mt7621-pci: add some definitions for enabling and disabling
    GEN and GEN1 clocks
  staging: mt7621-pci: use PERST_N instead of gpio control
  staging: mt7621-pci: use PCIE_PORT_LINKUP instead of hardcode value
  staging: mt7621-pci: enable interrupt when port is being enabled
  staging: mt7621-pci: factor out 'mt7621_pcie_enable_port' function
  staging: mt7621-pci: move some code into 'mt7621_pcie_init_ports'
  staging: mt7621-pci: replace 'mdelay()' with 'msleep()'

 drivers/staging/mt7621-dts/mt7621.dtsi  |   4 +-
 drivers/staging/mt7621-pci/pci-mt7621.c | 927 +++++++++++++++++++-------------
 2 files changed, 558 insertions(+), 373 deletions(-)

-- 
2.7.4

[PATCH v6 01/33] staging: mt7621-pci: parse and init port data from device tree

[Sergio Paracuellos]

Add initialization of each PCIe port reading and initializing
data using device tree.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 75 +++++++++++++++++++++++++++++++--
 1 file changed, 71 insertions(+), 4 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 8371a9c..b7cb273 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -126,16 +126,20 @@ static int pcie_link_status;
 
 /**
  * struct mt7621_pcie_port - PCIe port information
- * @base: IO mapped register base
+ * @base: I/O mapped register base
  * @list: port list
  * @pcie: pointer to PCIe host info
- * @reset: pointer to port reset control
+ * @pcie_rst: pointer to port reset control
+ * @pcie_clk: PCIe clock
+ * @slot: port slot
  */
 struct mt7621_pcie_port {
 	void __iomem *base;
 	struct list_head list;
 	struct mt7621_pcie *pcie;
-	struct reset_control *reset;
+	struct reset_control *pcie_rst;
+	struct clk *pcie_clk;
+	u32 slot;
 };
 
 /**
@@ -382,10 +386,57 @@ static int mt7621_pci_parse_request_of_pci_ranges(struct mt7621_pcie *pcie)
 	return 0;
 }
 
+static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
+				  struct device_node *node,
+				  int slot)
+{
+	struct mt7621_pcie_port *port;
+	struct device *dev = pcie->dev;
+	struct device_node *pnode = dev->of_node;
+	struct resource regs;
+	char name[6];
+	int err;
+
+	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
+	if (!port)
+		return -ENOMEM;
+
+	err = of_address_to_resource(pnode, slot + 1, &regs);
+	if (err) {
+		dev_err(dev, "missing \"reg\" property\n");
+		return err;
+	}
+
+	port->base = devm_ioremap_resource(dev, &regs);
+	if (IS_ERR(port->base))
+		return PTR_ERR(port->base);
+
+	snprintf(name, sizeof(name), "pcie%d", slot);
+	port->pcie_clk = devm_clk_get(dev, name);
+	if (IS_ERR(port->pcie_clk)) {
+		dev_err(dev, "failed to get pcie%d clock\n", slot);
+		return PTR_ERR(port->pcie_clk);
+	}
+
+	port->pcie_rst = devm_reset_control_get_exclusive(dev, name);
+	if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
+		dev_err(dev, "failed to get pcie%d reset control\n", slot);
+		return PTR_ERR(port->pcie_rst);
+	}
+
+	port->slot = slot;
+	port->pcie = pcie;
+
+	INIT_LIST_HEAD(&port->list);
+	list_add_tail(&port->list, &pcie->ports);
+
+	return 0;
+}
+
 static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
 {
 	struct device *dev = pcie->dev;
-	struct device_node *node = dev->of_node;
+	struct device_node *node = dev->of_node, *child;
 	struct resource regs;
 	int err;
 
@@ -399,6 +450,22 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
 	if (IS_ERR(pcie->base))
 		return PTR_ERR(pcie->base);
 
+	for_each_available_child_of_node(node, child) {
+		int slot;
+
+		err = of_pci_get_devfn(child);
+		if (err < 0) {
+			dev_err(dev, "failed to parse devfn: %d\n", err);
+			return err;
+		}
+
+		slot = PCI_SLOT(err);
+
+		err = mt7621_pcie_parse_port(pcie, child, slot);
+		if (err)
+			return err;
+	}
+
 	return 0;
 }
 
-- 
2.7.4

[PATCH v6 02/33] staging: mt7621-pci: replace return value if devm_pci_alloc_host_bridge call fails

[Sergio Paracuellos]

Driver probe function calls 'devm_pci_alloc_host_bridge'. If this call fails
it is returning -ENODEV. Return -ENOMEM instead which is more accurate for
this.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index b7cb273..357bbdd 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -516,7 +516,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 
 	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
 	if (!bridge)
-		return -ENODEV;
+		return -ENOMEM;
 
 	pcie = pci_host_bridge_priv(bridge);
 	pcie->dev = dev;
-- 
2.7.4

[PATCH v6 03/33] staging: mt7621-pci: add two helpers for read and write pcie register ports

[Sergio Paracuellos]

mt7621-pcie_port data structure has filed 'base' as the base address for
read and write related port registers. Create two inline functions
'pcie_port_read' and 'pcie_port_write' to make this task easier and
code more readable.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 357bbdd..04e82c3 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -175,6 +175,17 @@ static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
 	writel(val, pcie->base + reg);
 }
 
+static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
+{
+	return readl(port->base + reg);
+}
+
+static inline void pcie_port_write(struct mt7621_pcie_port *port,
+				   u32 val, u32 reg)
+{
+	writel(val, port->base + reg);
+}
+
 static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
 					 unsigned int func, unsigned int where)
 {
-- 
2.7.4

[PATCH v6 04/33] staging: mt7621-pci: factor out 'mt7621_pcie_enable_port' function

[Sergio Paracuellos]

Driver probe function is a mess and shall be refactored a lot. At first
make use of assert and deassert control factoring out a new function
called 'mt7621_pcie_enable_port'.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 88 +++++++++++++++------------------
 1 file changed, 41 insertions(+), 47 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 04e82c3..9be5ca1 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -480,6 +480,39 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
 	return 0;
 }
 
+static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
+{
+	struct mt7621_pcie *pcie = port->pcie;
+	struct device *dev = pcie->dev;
+	u32 slot = port->slot;
+	u32 val = 0;
+	int err;
+
+	err = clk_prepare_enable(port->pcie_clk);
+	if (err) {
+		dev_err(dev, "failed to enable pcie%d clock\n", slot);
+		return err;
+	}
+
+	reset_control_assert(port->pcie_rst);
+	reset_control_deassert(port->pcie_rst);
+
+	if ((pcie_port_read(port, RALINK_PCI_STATUS) & 0x1) == 0) {
+		dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", slot);
+		reset_control_assert(port->pcie_rst);
+		rt_sysc_m32(BIT(24 + slot), 0, RALINK_CLKCFG1);
+		pcie_link_status &= ~(1 << slot);
+	} else {
+		pcie_link_status |= BIT(slot);
+		val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+		/* enable pcie interrupt */
+		val |= BIT(20 + slot);
+		pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
+	}
+
+	return 0;
+}
+
 static int mt7621_pcie_request_resources(struct mt7621_pcie *pcie,
 					 struct list_head *res)
 {
@@ -518,6 +551,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct mt7621_pcie *pcie;
 	struct pci_host_bridge *bridge;
+	struct mt7621_pcie_port *port, *tmp;
 	int err;
 	u32 val = 0;
 	LIST_HEAD(res);
@@ -546,12 +580,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	ioport_resource.start = 0;
 	ioport_resource.end = ~0UL; /* no limit */
 
-	val = RALINK_PCIE0_RST;
-	val |= RALINK_PCIE1_RST;
-	val |= RALINK_PCIE2_RST;
-
-	ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
-
 	*(unsigned int *)(0xbe000060) &= ~(0x3 << 10 | 0x3 << 3);
 	*(unsigned int *)(0xbe000060) |=  BIT(10) | BIT(3);
 	mdelay(100);
@@ -561,11 +589,13 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 
 	mdelay(100);
 
-	val = RALINK_PCIE0_RST;
-	val |= RALINK_PCIE1_RST;
-	val |= RALINK_PCIE2_RST;
-
-	DEASSERT_SYSRST_PCIE(val);
+	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
+		err = mt7621_pcie_enable_port(port);
+		if (err) {
+			dev_err(dev, "enabling port %d failed\n", port->slot);
+			list_del(&port->list);
+		}
+	}
 
 	if ((*(unsigned int *)(0xbe00000c) & 0xFFFF) == 0x0101) // MT7621 E2
 		bypass_pipe_rst(pcie);
@@ -591,42 +621,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	*(unsigned int *)(0xbe000620) |= BIT(19) | BIT(8) | BIT(7);		// set DATA
 	mdelay(1000);
 
-	if ((pcie_read(pcie, RT6855_PCIE0_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
-		printk("PCIE0 no card, disable it(RST&CLK)\n");
-		ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
-		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
-		pcie_link_status &= ~(BIT(0));
-	} else {
-		pcie_link_status |=  BIT(0);
-		val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
-		val |= BIT(20); // enable pcie1 interrupt
-		pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
-	}
-
-	if ((pcie_read(pcie, RT6855_PCIE1_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
-		printk("PCIE1 no card, disable it(RST&CLK)\n");
-		ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
-		rt_sysc_m32(RALINK_PCIE1_CLK_EN, 0, RALINK_CLKCFG1);
-		pcie_link_status &= ~(BIT(1));
-	} else {
-		pcie_link_status |= BIT(1);
-		val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
-		val |= BIT(21); // enable pcie1 interrupt
-		pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
-	}
-
-	if ((pcie_read(pcie, RT6855_PCIE2_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
-		printk("PCIE2 no card, disable it(RST&CLK)\n");
-		ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
-		rt_sysc_m32(RALINK_PCIE2_CLK_EN, 0, RALINK_CLKCFG1);
-		pcie_link_status &= ~(BIT(2));
-	} else {
-		pcie_link_status |=  BIT(2);
-		val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
-		val |= BIT(22); // enable pcie2 interrupt
-		pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
-	}
-
 	if (pcie_link_status == 0)
 		return 0;
 
-- 
2.7.4

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[PATCH v6 05/33] staging: mt7621-pci: remove [ASSERT|DEASSERT]_SYSRST_PCIE macros

[Sergio Paracuellos]

Driver is using reset_control kernel API's to manage this so this
two macros are not needed anymore. Remove them.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 15 ---------------
 1 file changed, 15 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 9be5ca1..d94587e 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -94,21 +94,6 @@
 #define RALINK_PCI_MM_MAP_BASE		0x60000000
 #define RALINK_PCI_IO_MAP_BASE		0x1e160000
 
-#define ASSERT_SYSRST_PCIE(val)		\
-	do {								\
-		if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101)	\
-			rt_sysc_m32(0, val, RALINK_RSTCTRL);		\
-		else							\
-			rt_sysc_m32(val, 0, RALINK_RSTCTRL);		\
-	} while (0)
-#define DEASSERT_SYSRST_PCIE(val)	\
-	do {								\
-		if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101)	\
-			rt_sysc_m32(val, 0, RALINK_RSTCTRL);		\
-		else							\
-			rt_sysc_m32(0, val, RALINK_RSTCTRL);		\
-	} while (0)
-
 #define RALINK_CLKCFG1			0x30
 #define RALINK_RSTCTRL			0x34
 #define RALINK_GPIOMODE			0x60
-- 
2.7.4

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[PATCH v6 06/33] staging: mt7621-pci: remove GPL2+ text from license header

[Sergio Paracuellos]

This file has a valid SPDX license line added so reamining
GPL2+ boilerplate text is not needed at all. Remove it.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 31 +++----------------------------
 1 file changed, 3 insertions(+), 28 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index d94587e..d61b287 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -1,33 +1,10 @@
 // SPDX-License-Identifier: GPL-2.0+
-/**************************************************************************
- *
- *  BRIEF MODULE DESCRIPTION
+/*
+ * BRIEF MODULE DESCRIPTION
  *     PCI init for Ralink RT2880 solution
  *
- *  Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
  *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *
- **************************************************************************
  * May 2007 Bruce Chang
  * Initial Release
  *
@@ -36,8 +13,6 @@
  *
  * May 2011 Bruce Chang
  * support RT6855/MT7620 PCIe
- *
- **************************************************************************
  */
 
 #include <linux/bitops.h>
-- 
2.7.4

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[PATCH v6 07/33] staging: mt7621-pci: remove two commented code lines

[Sergio Paracuellos]

This two lines whch are commented are not needed at all.
Remove them.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index d61b287..c4adf86 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -629,11 +629,6 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 		break;
 	}
 
-/*
-	ioport_resource.start = mt7621_res_pci_io1.start;
-	ioport_resource.end = mt7621_res_pci_io1.end;
-*/
-
 	pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
 	pcie_write(pcie, RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
 
-- 
2.7.4

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[PATCH v6 08/33] staging: mt7621-pci: remove reset related unused macros

[Sergio Paracuellos]

There are three macros which are not being used at all.
Remove them.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index c4adf86..c9ac92e 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -76,10 +76,6 @@
 #define RALINK_PCIE_CLK_GEN1		0x80
 //RALINK_RSTCTRL bit
 #define RALINK_PCIE_RST			BIT(23)
-#define RALINK_PCI_RST			BIT(24)
-//RALINK_CLKCFG1 bit
-#define RALINK_PCI_CLK_EN		BIT(19)
-#define RALINK_PCIE_CLK_EN		BIT(21)
 
 #define MEMORY_BASE 0x0
 static int pcie_link_status;
-- 
2.7.4

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[PATCH v6 09/33] staging: mt7621-pci: reagroup reset related macros all together

[Sergio Paracuellos]

Reset bits related macros are in different parts. Reagroup
all of them together to  improve readability.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index c9ac92e..28c3f0a 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -45,6 +45,9 @@
 #define RALINK_PCI_CONFIG_DATA		0x24
 #define RALINK_PCI_MEMBASE		0x28
 #define RALINK_PCI_IOBASE		0x2C
+
+/* RALINK_RSTCTRL bits */
+#define RALINK_PCIE_RST			BIT(23)
 #define RALINK_PCIE0_RST		BIT(24)
 #define RALINK_PCIE1_RST		BIT(25)
 #define RALINK_PCIE2_RST		BIT(26)
@@ -74,8 +77,6 @@
 #define RALINK_GPIOMODE			0x60
 #define RALINK_PCIE_CLK_GEN		0x7c
 #define RALINK_PCIE_CLK_GEN1		0x80
-//RALINK_RSTCTRL bit
-#define RALINK_PCIE_RST			BIT(23)
 
 #define MEMORY_BASE 0x0
 static int pcie_link_status;
-- 
2.7.4

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[PATCH v6 10/33] staging: mt7621-pci: rewrite pcie phy related functions

[Sergio Paracuellos]

Function 'bypass_pipe_rst' and 'set_phy_for_ssc' can be
written in a cleaner way. Instead of use comments to see which
bits are the ones which are being enabled add new macros with
that information using BIT and GENMASK kernel macros. Avoid the
use of set_pcie_phy which is kind of dark and use new macros also
resetting and adding bits using bitwise operators directly in the
code. Now these function are offset-based on the port to use them
cleaner in driver probe functio and improving readability.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 294 +++++++++++++++++++++-----------
 1 file changed, 195 insertions(+), 99 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 28c3f0a..5dce7af 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -66,9 +66,6 @@
 #define RALINK_PCI_SUBID		0x0038
 #define RALINK_PCI_STATUS		0x0050
 
-#define RALINK_PCIEPHY_P0P1_CTL_OFFSET	0x9000
-#define RALINK_PCIEPHY_P2_CTL_OFFSET	0xA000
-
 #define RALINK_PCI_MM_MAP_BASE		0x60000000
 #define RALINK_PCI_IO_MAP_BASE		0x1e160000
 
@@ -79,13 +76,79 @@
 #define RALINK_PCIE_CLK_GEN1		0x80
 
 #define MEMORY_BASE 0x0
+
 static int pcie_link_status;
 
+/* pcie phy related macros */
+#define RALINK_PCIEPHY_P0P1_CTL_OFFSET	0x9000
+#define RALINK_PCIEPHY_P2_CTL_OFFSET	0xA000
+
+#define RG_P0_TO_P1_WIDTH		0x100
+
+#define RG_PE1_PIPE_REG			0x02c
+#define RG_PE1_PIPE_RST			BIT(12)
+#define RG_PE1_PIPE_CMD_FRC		BIT(4)
+
+#define RG_PE1_H_LCDDS_REG		0x49c
+#define RG_PE1_H_LCDDS_PCW		GENMASK(30, 0)
+#define RG_PE1_H_LCDDS_PCW_VAL(x)	((0x7fffffff & (x)) << 0)
+
+#define RG_PE1_FRC_H_XTAL_REG		0x400
+#define RG_PE1_FRC_H_XTAL_TYPE          BIT(8)
+#define RG_PE1_H_XTAL_TYPE              GENMASK(10, 9)
+#define RG_PE1_H_XTAL_TYPE_VAL(x)       ((0x3 & (x)) << 9)
+
+#define RG_PE1_FRC_PHY_REG		0x000
+#define RG_PE1_FRC_PHY_EN               BIT(4)
+#define RG_PE1_PHY_EN                   BIT(5)
+
+#define RG_PE1_H_PLL_REG		0x490
+#define RG_PE1_H_PLL_BC			GENMASK(23, 22)
+#define RG_PE1_H_PLL_BC_VAL(x)		((0x3 & (x)) << 22)
+#define RG_PE1_H_PLL_BP			GENMASK(21, 18)
+#define RG_PE1_H_PLL_BP_VAL(x)		((0xf & (x)) << 18)
+#define RG_PE1_H_PLL_IR			GENMASK(15, 12)
+#define RG_PE1_H_PLL_IR_VAL(x)		((0xf & (x)) << 12)
+#define RG_PE1_H_PLL_IC			GENMASK(11, 8)
+#define RG_PE1_H_PLL_IC_VAL(x)		((0xf & (x)) << 8)
+#define RG_PE1_H_PLL_PREDIV             GENMASK(7, 6)
+#define RG_PE1_H_PLL_PREDIV_VAL(x)      ((0x3 & (x)) << 6)
+#define RG_PE1_PLL_DIVEN		GENMASK(3, 1)
+#define RG_PE1_PLL_DIVEN_VAL(x)		((0x7 & (x)) << 1)
+
+#define RG_PE1_H_PLL_FBKSEL_REG		0x4bc
+#define RG_PE1_H_PLL_FBKSEL             GENMASK(5, 4)
+#define RG_PE1_H_PLL_FBKSEL_VAL(x)      ((0x3 & (x)) << 4)
+
+#define	RG_PE1_H_LCDDS_SSC_PRD_REG	0x4a4
+#define RG_PE1_H_LCDDS_SSC_PRD          GENMASK(15, 0)
+#define RG_PE1_H_LCDDS_SSC_PRD_VAL(x)   ((0xffff & (x)) << 0)
+
+#define RG_PE1_H_LCDDS_SSC_DELTA_REG	0x4a8
+#define RG_PE1_H_LCDDS_SSC_DELTA        GENMASK(11, 0)
+#define RG_PE1_H_LCDDS_SSC_DELTA_VAL(x) ((0xfff & (x)) << 0)
+#define RG_PE1_H_LCDDS_SSC_DELTA1       GENMASK(27, 16)
+#define RG_PE1_H_LCDDS_SSC_DELTA1_VAL(x) ((0xff & (x)) << 16)
+
+#define RG_PE1_LCDDS_CLK_PH_INV_REG	0x4a0
+#define RG_PE1_LCDDS_CLK_PH_INV		BIT(5)
+
+#define RG_PE1_H_PLL_BR_REG		0x4ac
+#define RG_PE1_H_PLL_BR			GENMASK(18, 16)
+#define RG_PE1_H_PLL_BR_VAL(x)		((0x7 & (x)) << 16)
+
+#define	RG_PE1_MSTCKDIV_REG		0x414
+#define RG_PE1_MSTCKDIV			GENMASK(7, 6)
+#define RG_PE1_MSTCKDIV_VAL(x)		((0x3 & (x)) << 6)
+
+#define RG_PE1_FRC_MSTCKDIV		BIT(5)
+
 /**
  * struct mt7621_pcie_port - PCIe port information
  * @base: I/O mapped register base
  * @list: port list
  * @pcie: pointer to PCIe host info
+ * @phy_reg_offset: offset to related phy registers
  * @pcie_rst: pointer to port reset control
  * @pcie_clk: PCIe clock
  * @slot: port slot
@@ -94,6 +157,7 @@ struct mt7621_pcie_port {
 	void __iomem *base;
 	struct list_head list;
 	struct mt7621_pcie *pcie;
+	u32 phy_reg_offset;
 	struct reset_control *pcie_rst;
 	struct clk *pcie_clk;
 	u32 slot;
@@ -187,109 +251,140 @@ write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val)
 }
 
 static void
-set_pcie_phy(struct mt7621_pcie *pcie, u32 offset,
-	     int start_b, int bits, int val)
+bypass_pipe_rst(struct mt7621_pcie_port *port)
 {
+	struct mt7621_pcie *pcie = port->pcie;
+	u32 phy_offset = port->phy_reg_offset;
+	u32 offset = (port->slot != 1) ?
+		phy_offset + RG_PE1_PIPE_REG :
+		phy_offset + RG_PE1_PIPE_REG + RG_P0_TO_P1_WIDTH;
 	u32 reg = pcie_read(pcie, offset);
 
-	reg &= ~(((1 << bits) - 1) << start_b);
-	reg |= val << start_b;
+	reg &= ~(RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC);
+	reg |= (RG_PE1_PIPE_RST | RG_PE1_PIPE_CMD_FRC);
 	pcie_write(pcie, reg, offset);
 }
 
 static void
-bypass_pipe_rst(struct mt7621_pcie *pcie)
+set_phy_for_ssc(struct mt7621_pcie_port *port)
 {
-	/* PCIe Port 0 */
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
-	/* PCIe Port 1 */
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
-	/* PCIe Port 2 */
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
-}
-
-static void
-set_phy_for_ssc(struct mt7621_pcie *pcie)
-{
-	unsigned long reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
+	struct mt7621_pcie *pcie = port->pcie;
+	struct device *dev = pcie->dev;
+	u32 phy_offset = port->phy_reg_offset;
+	u32 reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
+	u32 offset;
+	u32 val;
 
 	reg = (reg >> 6) & 0x7;
-	/* Set PCIe Port0 & Port1 PHY to disable SSC */
+	/* Set PCIe Port PHY to disable SSC */
 	/* Debug Xtal Type */
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  9, 2, 0x00);	// rg_pe1_h_xtal_type
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 0 enable control
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 1 enable control
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 0 disable
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 1 disable
-	if (reg <= 5 && reg >= 3) {	// 40MHz Xtal
-		set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x01);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
-		printk("***** Xtal 40MHz *****\n");
-	} else {			// 25MHz | 20MHz Xtal
-		set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x00);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
+	offset = phy_offset + RG_PE1_FRC_H_XTAL_REG;
+	val = pcie_read(pcie, offset);
+	val &= ~(RG_PE1_FRC_H_XTAL_TYPE | RG_PE1_H_XTAL_TYPE);
+	val |= RG_PE1_FRC_H_XTAL_TYPE;
+	val |= RG_PE1_H_XTAL_TYPE_VAL(0x00);
+	pcie_write(pcie, val, offset);
+
+	/* disable port */
+	offset = (port->slot != 1) ?
+		phy_offset + RG_PE1_FRC_PHY_REG :
+		phy_offset + RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH;
+	val = pcie_read(pcie, offset);
+	val &= ~(RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN);
+	val |= RG_PE1_FRC_PHY_EN;
+	pcie_write(pcie, val, offset);
+
+	/* Set Pre-divider ratio (for host mode) */
+	offset =  phy_offset + RG_PE1_H_PLL_REG;
+	val = pcie_read(pcie, offset);
+	val &= ~(RG_PE1_H_PLL_PREDIV);
+
+	if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */
+		val |= RG_PE1_H_PLL_PREDIV_VAL(0x01);
+		pcie_write(pcie, val, offset);
+		dev_info(dev, "Xtal is 40MHz\n");
+	} else { /* 25MHz | 20MHz Xtal */
+		val |= RG_PE1_H_PLL_PREDIV_VAL(0x00);
+		pcie_write(pcie, val, offset);
 		if (reg >= 6) {
-			printk("***** Xtal 25MHz *****\n");
-			set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc),  4, 2, 0x01);	// RG_PE1_H_PLL_FBKSEL	//Feedback clock select
-			set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c),  0, 31, 0x18000000);	// RG_PE1_H_LCDDS_PCW_NCPO	//DDS NCPO PCW (for host mode)
-			set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4),  0, 16, 0x18d);	// RG_PE1_H_LCDDS_SSC_PRD	//DDS SSC dither period control
-			set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8),  0, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA	//DDS SSC dither amplitude control
-			set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA1	//DDS SSC dither amplitude control for initial
+			dev_info(dev, "Xtal is 25MHz\n");
+
+			/* Select feedback clock */
+			offset = phy_offset + RG_PE1_H_PLL_FBKSEL_REG;
+			val = pcie_read(pcie, offset);
+			val &= ~(RG_PE1_H_PLL_FBKSEL);
+			val |= RG_PE1_H_PLL_FBKSEL_VAL(0x01);
+			pcie_write(pcie, val, offset);
+
+			/* DDS NCPO PCW (for host mode) */
+			offset = phy_offset + RG_PE1_H_LCDDS_SSC_PRD_REG;
+			val = pcie_read(pcie, offset);
+			val &= ~(RG_PE1_H_LCDDS_SSC_PRD);
+			val |= RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18000000);
+			pcie_write(pcie, val, offset);
+
+			/* DDS SSC dither period control */
+			offset = phy_offset + RG_PE1_H_LCDDS_SSC_PRD_REG;
+			val = pcie_read(pcie, offset);
+			val &= ~(RG_PE1_H_LCDDS_SSC_PRD);
+			val |= RG_PE1_H_LCDDS_SSC_PRD_VAL(0x18d);
+			pcie_write(pcie, val, offset);
+
+			/* DDS SSC dither amplitude control */
+			offset = phy_offset + RG_PE1_H_LCDDS_SSC_DELTA_REG;
+			val = pcie_read(pcie, offset);
+			val &= ~(RG_PE1_H_LCDDS_SSC_DELTA |
+				 RG_PE1_H_LCDDS_SSC_DELTA1);
+			val |= RG_PE1_H_LCDDS_SSC_DELTA_VAL(0x4a);
+			val |= RG_PE1_H_LCDDS_SSC_DELTA1_VAL(0x4a);
+			pcie_write(pcie, val, offset);
 		} else {
-			printk("***** Xtal 20MHz *****\n");
+			dev_info(dev, "Xtal is 20MHz\n");
 		}
 	}
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0),  5, 1, 0x01);	// RG_PE1_LCDDS_CLK_PH_INV	//DDS clock inversion
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02);	// RG_PE1_H_PLL_BC
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06);	// RG_PE1_H_PLL_BP
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02);	// RG_PE1_H_PLL_IR
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  8, 4, 0x01);	// RG_PE1_H_PLL_IC
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00);	// RG_PE1_H_PLL_BR
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  1, 3, 0x02);	// RG_PE1_PLL_DIVEN
-	if (reg <= 5 && reg >= 3) {	// 40MHz Xtal
-		set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  6, 2, 0x01);	// rg_pe1_mstckdiv		//value of da_pe1_mstckdiv when force mode enable
-		set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  5, 1, 0x01);	// rg_pe1_frc_mstckdiv	//force mode enable of da_pe1_mstckdiv
-	}
-	/* Enable PHY and disable force mode */
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 0 enable
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 1 enable
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 1 disable control
 
-	/* Set PCIe Port2 PHY to disable SSC */
-	/* Debug Xtal Type */
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  9, 2, 0x00);	// rg_pe1_h_xtal_type
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 0 enable control
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 0 disable
-	if (reg <= 5 && reg >= 3) {	// 40MHz Xtal
-		set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x01);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
-	} else {			// 25MHz | 20MHz Xtal
-		set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x00);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
-		if (reg >= 6) {		// 25MHz Xtal
-			set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc),  4, 2, 0x01);	// RG_PE1_H_PLL_FBKSEL	//Feedback clock select
-			set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c),  0, 31, 0x18000000);	// RG_PE1_H_LCDDS_PCW_NCPO	//DDS NCPO PCW (for host mode)
-			set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4),  0, 16, 0x18d);	// RG_PE1_H_LCDDS_SSC_PRD	//DDS SSC dither period control
-			set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8),  0, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA	//DDS SSC dither amplitude control
-			set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA1	//DDS SSC dither amplitude control for initial
-		}
-	}
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0),  5, 1, 0x01);	// RG_PE1_LCDDS_CLK_PH_INV	//DDS clock inversion
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02);	// RG_PE1_H_PLL_BC
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06);	// RG_PE1_H_PLL_BP
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02);	// RG_PE1_H_PLL_IR
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  8, 4, 0x01);	// RG_PE1_H_PLL_IC
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00);	// RG_PE1_H_PLL_BR
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  1, 3, 0x02);	// RG_PE1_PLL_DIVEN
-	if (reg <= 5 && reg >= 3) {	// 40MHz Xtal
-		set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  6, 2, 0x01);	// rg_pe1_mstckdiv		//value of da_pe1_mstckdiv when force mode enable
-		set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  5, 1, 0x01);	// rg_pe1_frc_mstckdiv	//force mode enable of da_pe1_mstckdiv
+	/* DDS clock inversion */
+	offset = phy_offset + RG_PE1_LCDDS_CLK_PH_INV_REG;
+	val = pcie_read(pcie, offset);
+	val &= ~(RG_PE1_LCDDS_CLK_PH_INV);
+	val |= RG_PE1_LCDDS_CLK_PH_INV;
+	pcie_write(pcie, val, offset);
+
+	/* Set PLL bits */
+	offset = phy_offset + RG_PE1_H_PLL_REG;
+	val = pcie_read(pcie, offset);
+	val &= ~(RG_PE1_H_PLL_BC | RG_PE1_H_PLL_BP | RG_PE1_H_PLL_IR |
+		 RG_PE1_H_PLL_IC | RG_PE1_PLL_DIVEN);
+	val |= RG_PE1_H_PLL_BC_VAL(0x02);
+	val |= RG_PE1_H_PLL_BP_VAL(0x06);
+	val |= RG_PE1_H_PLL_IR_VAL(0x02);
+	val |= RG_PE1_H_PLL_IC_VAL(0x01);
+	val |= RG_PE1_PLL_DIVEN_VAL(0x02);
+	pcie_write(pcie, val, offset);
+
+	offset = phy_offset + RG_PE1_H_PLL_BR_REG;
+	val = pcie_read(pcie, offset);
+	val &= ~(RG_PE1_H_PLL_BR);
+	val |= RG_PE1_H_PLL_BR_VAL(0x00);
+	pcie_write(pcie, val, offset);
+
+	if (reg <= 5 && reg >= 3) { /* 40MHz Xtal */
+		/* set force mode enable of da_pe1_mstckdiv */
+		offset = phy_offset + RG_PE1_MSTCKDIV_REG;
+		val = pcie_read(pcie, offset);
+		val &= ~(RG_PE1_MSTCKDIV | RG_PE1_FRC_MSTCKDIV);
+		val |= (RG_PE1_MSTCKDIV_VAL(0x01) | RG_PE1_FRC_MSTCKDIV);
+		pcie_write(pcie, val, offset);
 	}
+
 	/* Enable PHY and disable force mode */
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 0 enable
-	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control
+	offset = (port->slot != 1) ?
+		phy_offset + RG_PE1_FRC_PHY_REG :
+		phy_offset + RG_PE1_FRC_PHY_REG + RG_P0_TO_P1_WIDTH;
+	val = pcie_read(pcie, offset);
+	val &= ~(RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN);
+	val |= (RG_PE1_FRC_PHY_EN | RG_PE1_PHY_EN);
+	pcie_write(pcie, val, offset);
 }
 
 static void setup_cm_memory_region(struct resource *mem_resource)
@@ -394,6 +489,9 @@ static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
 
 	port->slot = slot;
 	port->pcie = pcie;
+	port->phy_reg_offset = (slot != 2) ?
+				RALINK_PCIEPHY_P0P1_CTL_OFFSET :
+				RALINK_PCIEPHY_P2_CTL_OFFSET;
 
 	INIT_LIST_HEAD(&port->list);
 	list_add_tail(&port->list, &pcie->ports);
@@ -547,23 +645,21 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	mdelay(100);
 
 	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
+		u32 slot = port->slot;
+
 		err = mt7621_pcie_enable_port(port);
 		if (err) {
-			dev_err(dev, "enabling port %d failed\n", port->slot);
+			dev_err(dev, "enabling port %d failed\n", slot);
 			list_del(&port->list);
+		} else {
+			if ((*(unsigned int *)(0xbe00000c) & 0xFFFF) == 0x0101) // MT7621 E2
+				bypass_pipe_rst(port);
+			set_phy_for_ssc(port);
+			val = read_config(pcie, slot, 0x70c);
+			dev_info(dev, "Port %d N_FTS = %x\n", (unsigned int)val, slot);
 		}
 	}
 
-	if ((*(unsigned int *)(0xbe00000c) & 0xFFFF) == 0x0101) // MT7621 E2
-		bypass_pipe_rst(pcie);
-	set_phy_for_ssc(pcie);
-
-	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
-		u32 slot = port->slot;
-		val = read_config(pcie, slot, 0x70c);
-		dev_info(dev, "Port %d N_FTS = %x\n", (unsigned int)val, slot);
-	}
-
 	rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
 	rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
 
-- 
2.7.4

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[PATCH v6 11/33] staging: mt7621-pci: factor out 'mt7621_enable_phy' function

[Sergio Paracuellos]

Factor out a new function 'mt7621_enable_phy' for enabling the
pcie phy for each port and call it from 'mt7621_pcie_enable_port'.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 5dce7af..7e76d30 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -387,6 +387,14 @@ set_phy_for_ssc(struct mt7621_pcie_port *port)
 	pcie_write(pcie, val, offset);
 }
 
+static void mt7621_enable_phy(struct mt7621_pcie_port *port)
+{
+	/* MT7621 E2 */
+	if ((*(unsigned int *)(0xbe00000c) & 0xFFFF) == 0x0101)
+		bypass_pipe_rst(port);
+	set_phy_for_ssc(port);
+}
+
 static void setup_cm_memory_region(struct resource *mem_resource)
 {
 	resource_size_t mask;
@@ -565,6 +573,8 @@ static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
 		pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
 	}
 
+	mt7621_enable_phy(port);
+
 	return 0;
 }
 
@@ -652,9 +662,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 			dev_err(dev, "enabling port %d failed\n", slot);
 			list_del(&port->list);
 		} else {
-			if ((*(unsigned int *)(0xbe00000c) & 0xFFFF) == 0x0101) // MT7621 E2
-				bypass_pipe_rst(port);
-			set_phy_for_ssc(port);
 			val = read_config(pcie, slot, 0x70c);
 			dev_info(dev, "Port %d N_FTS = %x\n", (unsigned int)val, slot);
 		}
-- 
2.7.4

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[PATCH v6 12/33] staging: mt7621-pci: debug port N_FTS inside 'mt7621_pcie_enable_port'

[Sergio Paracuellos]

Move debug for the port N_FTS from driver probe function to the more
appropiate one 'mt7621_pcie_enable_port'.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 7e76d30..50c7bd7 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -575,6 +575,9 @@ static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
 
 	mt7621_enable_phy(port);
 
+	val = read_config(pcie, slot, 0x70c);
+	dev_info(dev, "Port %d N_FTS = %x\n", (unsigned int)val, slot);
+
 	return 0;
 }
 
@@ -661,9 +664,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		if (err) {
 			dev_err(dev, "enabling port %d failed\n", slot);
 			list_del(&port->list);
-		} else {
-			val = read_config(pcie, slot, 0x70c);
-			dev_info(dev, "Port %d N_FTS = %x\n", (unsigned int)val, slot);
 		}
 	}
 
-- 
2.7.4

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[PATCH v6 13/33] staging: mt7621-pci: rename 'mt7621_pcie_enable_port' into 'mt7621_pcie_init_port'

[Sergio Paracuellos]

Rename function 'mt7621_pcie_enable_port' with a name which is better
for what the function is really doing calling it 'mt7621_pcie_init_port'.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 50c7bd7..11fe9ff 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -543,7 +543,7 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
 	return 0;
 }
 
-static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
+static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
 {
 	struct mt7621_pcie *pcie = port->pcie;
 	struct device *dev = pcie->dev;
@@ -660,7 +660,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
 		u32 slot = port->slot;
 
-		err = mt7621_pcie_enable_port(port);
+		err = mt7621_pcie_init_port(port);
 		if (err) {
 			dev_err(dev, "enabling port %d failed\n", slot);
 			list_del(&port->list);
-- 
2.7.4

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[PATCH v6 14/33] staging: mt7621-dts: add sysctl registers base address to pcie

[Sergio Paracuellos]

Add missing system control registers address in pcie node of
the device tree.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-dts/mt7621.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index 2e837e6..6b4bc43 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -397,8 +397,8 @@
 		reg = <0x1e140000 0x100     /* host-pci bridge registers */
 			0x1e142000 0x100    /* pcie port 0 RC control registers */
 			0x1e143000 0x100    /* pcie port 1 RC control registers */
-			0x1e144000 0x100>;  /* pcie port 2 RC control registers */
-
+			0x1e144000 0x100    /* pcie port 2 RC control registers */
+			0x1e000000 0x100>;  /* sysctl */
 		#address-cells = <3>;
 		#size-cells = <2>;
 
-- 
2.7.4

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[PATCH v6 15/33] staging: mt7621-pci: remap and use sysctl from device tree

[Sergio Paracuellos]

There are some pointer read and writes which can be replaced
properly using sysctl registers readed from device tree. Remap
sysctl registers and replace in proper places.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 38 ++++++++++++++++++++++++++++-----
 1 file changed, 33 insertions(+), 5 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 11fe9ff..0fc98f7 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -37,6 +37,12 @@
  * devices.
  */
 
+/* sysctl */
+#define MT7621_CHIP_REV_ID		0x0c
+#define MT7621_GPIO_MODE		0x60
+#define CHIP_REV_MT7621_E2		0x0101
+
+/* pcie */
 #define RALINK_PCIE0_CLK_EN		BIT(24)
 #define RALINK_PCIE1_CLK_EN		BIT(25)
 #define RALINK_PCIE2_CLK_EN		BIT(26)
@@ -166,6 +172,7 @@ struct mt7621_pcie_port {
 /**
  * struct mt7621_pcie - PCIe host information
  * @base: IO Mapped Register Base
+ * @sysctl: system control mapped register base
  * @io: IO resource
  * @mem: non-prefetchable memory resource
  * @busn: bus range
@@ -175,6 +182,7 @@ struct mt7621_pcie_port {
  */
 struct mt7621_pcie {
 	void __iomem *base;
+	void __iomem *sysctl;
 	struct device *dev;
 	struct resource io;
 	struct resource mem;
@@ -389,8 +397,10 @@ set_phy_for_ssc(struct mt7621_pcie_port *port)
 
 static void mt7621_enable_phy(struct mt7621_pcie_port *port)
 {
-	/* MT7621 E2 */
-	if ((*(unsigned int *)(0xbe00000c) & 0xFFFF) == 0x0101)
+	struct mt7621_pcie *pcie = port->pcie;
+	u32 chip_rev_id = ioread32(pcie->sysctl + MT7621_CHIP_REV_ID);
+
+	if ((chip_rev_id & 0xFFFF) == CHIP_REV_MT7621_E2)
 		bypass_pipe_rst(port);
 	set_phy_for_ssc(port);
 }
@@ -524,6 +534,16 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
 	if (IS_ERR(pcie->base))
 		return PTR_ERR(pcie->base);
 
+	err = of_address_to_resource(node, 4, &regs);
+	if (err) {
+		dev_err(dev, "missing \"reg\" property\n");
+		return err;
+	}
+
+	pcie->sysctl = devm_ioremap_resource(dev, &regs);
+	if (IS_ERR(pcie->sysctl))
+		return PTR_ERR(pcie->sysctl);
+
 	for_each_available_child_of_node(node, child) {
 		int slot;
 
@@ -614,6 +634,16 @@ static int mt7621_pcie_register_host(struct pci_host_bridge *host,
 	return pci_host_probe(host);
 }
 
+static void mt7621_set_gpio_mode(struct mt7621_pcie *pcie)
+{
+	u32 reg = ioread32(pcie->sysctl + MT7621_GPIO_MODE);
+
+	reg &= ~(0x3 << 10 | 0x3 << 3);
+	reg |= (BIT(10) | BIT(3));
+	iowrite32(reg, pcie->sysctl + MT7621_GPIO_MODE);
+	mdelay(100);
+}
+
 static int mt7621_pci_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -648,9 +678,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	ioport_resource.start = 0;
 	ioport_resource.end = ~0UL; /* no limit */
 
-	*(unsigned int *)(0xbe000060) &= ~(0x3 << 10 | 0x3 << 3);
-	*(unsigned int *)(0xbe000060) |=  BIT(10) | BIT(3);
-	mdelay(100);
+	mt7621_set_gpio_mode(pcie);
 	*(unsigned int *)(0xbe000600) |= BIT(19) | BIT(8) | BIT(7); // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
 	mdelay(100);
 	*(unsigned int *)(0xbe000620) &= ~(BIT(19) | BIT(8) | BIT(7));		// clear DATA
-- 
2.7.4

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[PATCH v6 16/33] staging: mt7621-pci: use a trailing */ on a separate line

[Sergio Paracuellos]

Chackpatch script is compalining about one comment which
is not following the kernel style. Fix it.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 0fc98f7..afc8720 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -410,9 +410,11 @@ static void setup_cm_memory_region(struct resource *mem_resource)
 	resource_size_t mask;
 
 	if (mips_cps_numiocu(0)) {
-		/* FIXME: hardware doesn't accept mask values with 1s after
+		/*
+		 * FIXME: hardware doesn't accept mask values with 1s after
 		 * 0s (e.g. 0xffef), so it would be great to warn if that's
-		 * about to happen */
+		 * about to happen
+		 */
 		mask = ~(mem_resource->end - mem_resource->start);
 
 		write_gcr_reg1_base(mem_resource->start);
-- 
2.7.4

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[PATCH v6 17/33] staging: mt7621-pci: use dev_* functions instead of printk

[Sergio Paracuellos]

checkpatch script is complaining about the use of printk instead
of use more proper dev_* kernel functions. Replace all of them
removing warnings.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index afc8720..6d26180 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -405,8 +405,10 @@ static void mt7621_enable_phy(struct mt7621_pcie_port *port)
 	set_phy_for_ssc(port);
 }
 
-static void setup_cm_memory_region(struct resource *mem_resource)
+static void setup_cm_memory_region(struct mt7621_pcie *pcie)
 {
+	struct resource *mem_resource = &pcie->mem;
+	struct device *dev = pcie->dev;
 	resource_size_t mask;
 
 	if (mips_cps_numiocu(0)) {
@@ -419,7 +421,7 @@ static void setup_cm_memory_region(struct resource *mem_resource)
 
 		write_gcr_reg1_base(mem_resource->start);
 		write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
-		printk("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
+		dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
 			(unsigned long long)read_gcr_reg1_base(),
 			(unsigned long long)read_gcr_reg1_mask());
 	}
@@ -771,7 +773,7 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 			   RT6855_PCIE0_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
 		pcie_write(pcie, 0x06040001,
 			   RT6855_PCIE0_OFFSET + RALINK_PCI_CLASS);
-		printk("PCIE0 enabled\n");
+		dev_info(dev, "PCIE0 enabled\n");
 	}
 
 	//PCIe1
@@ -783,7 +785,7 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 			   RT6855_PCIE1_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
 		pcie_write(pcie, 0x06040001,
 			   RT6855_PCIE1_OFFSET + RALINK_PCI_CLASS);
-		printk("PCIE1 enabled\n");
+		dev_info(dev, "PCIE1 enabled\n");
 	}
 
 	//PCIe2
@@ -795,7 +797,7 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 			   RT6855_PCIE2_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
 		pcie_write(pcie, 0x06040001,
 			   RT6855_PCIE2_OFFSET + RALINK_PCI_CLASS);
-		printk("PCIE2 enabled\n");
+		dev_info(dev, "PCIE2 enabled\n");
 	}
 
 	switch (pcie_link_status) {
@@ -830,7 +832,7 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 		return err;
 	}
 
-	setup_cm_memory_region(&pcie->mem);
+	setup_cm_memory_region(pcie);
 
 	err = mt7621_pcie_request_resources(pcie, &res);
 	if (err) {
-- 
2.7.4

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[PATCH v6 18/33] staging: mt7621-pci: factor out 'mt7621_pcie_enable_ports' function

[Sergio Paracuellos]

Driver probe function check for a bit in 'pcie_link_status' for
enabling the pcie port or not. Instead of this add 'enabled' field
in 'mt7621_pcie_port' structure and check its value to achieve this
inside a new 'mt7621_pcie_enable_ports' function. The offsets for
the correct port are derived from the slot of the port. This field
'enabled' is properly initilized in 'mt7621_pcie_init_port'. Also
depending of the number of ports enabled we have to properly init
its registers taking into account that we will use virtual bridges
from zero to num_slots_enabled as follows:
    - Only one enabled -> only enable virtual bridge 0.
    - Two enabled -> enable virtual bridges 0 and 1.
    - Three enabled -> enable virtual bridges 0, 1 and 2.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 106 +++++++++++++-------------------
 1 file changed, 42 insertions(+), 64 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 6d26180..5f07b53 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -61,9 +61,8 @@
 #define RALINK_PCI_PCICFG_ADDR		0x0000
 #define RALINK_PCI_PCIMSK_ADDR		0x000C
 
-#define RT6855_PCIE0_OFFSET		0x2000
-#define RT6855_PCIE1_OFFSET		0x3000
-#define RT6855_PCIE2_OFFSET		0x4000
+#define MT7621_PCIE_OFFSET		0x2000
+#define MT7621_NEXT_PORT		0x1000
 
 #define RALINK_PCI_BAR0SETUP_ADDR	0x0010
 #define RALINK_PCI_IMBASEBAR0_ADDR	0x0018
@@ -158,6 +157,7 @@ static int pcie_link_status;
  * @pcie_rst: pointer to port reset control
  * @pcie_clk: PCIe clock
  * @slot: port slot
+ * @enabled: indicates if port is enabled
  */
 struct mt7621_pcie_port {
 	void __iomem *base;
@@ -167,6 +167,7 @@ struct mt7621_pcie_port {
 	struct reset_control *pcie_rst;
 	struct clk *pcie_clk;
 	u32 slot;
+	bool enabled;
 };
 
 /**
@@ -589,8 +590,10 @@ static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
 		reset_control_assert(port->pcie_rst);
 		rt_sysc_m32(BIT(24 + slot), 0, RALINK_CLKCFG1);
 		pcie_link_status &= ~(1 << slot);
+		port->enabled = false;
 	} else {
 		pcie_link_status |= BIT(slot);
+		port->enabled = true;
 		val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
 		/* enable pcie interrupt */
 		val |= BIT(20 + slot);
@@ -605,6 +608,41 @@ static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
 	return 0;
 }
 
+static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
+{
+	struct device *dev = pcie->dev;
+	struct mt7621_pcie_port *port;
+	u8 num_slots_enabled = 0;
+	u32 offset;
+	u32 slot;
+	u32 val;
+
+	list_for_each_entry(port, &pcie->ports, list) {
+		slot = port->slot;
+		offset = MT7621_PCIE_OFFSET + (slot * MT7621_NEXT_PORT);
+
+		if (port->enabled) {
+			/* open 7FFF:2G; ENABLE */
+			pcie_write(pcie, 0x7FFF0001,
+				   offset + RALINK_PCI_BAR0SETUP_ADDR);
+			pcie_write(pcie, MEMORY_BASE,
+				   offset + RALINK_PCI_IMBASEBAR0_ADDR);
+			pcie_write(pcie, 0x06040001, offset + RALINK_PCI_CLASS);
+			dev_info(dev, "PCIE%d enabled\n", slot);
+			num_slots_enabled++;
+		}
+	}
+
+	for (slot = 0; slot < num_slots_enabled; slot++) {
+		val = read_config(pcie, slot, 0x4);
+		write_config(pcie, slot, 0x4, val | 0x4);
+		val = read_config(pcie, slot, 0x70c);
+		val &= ~(0xff) << 8;
+		val |= 0x50 << 8;
+		write_config(pcie, slot, 0x70c, val);
+	}
+}
+
 static int mt7621_pcie_request_resources(struct mt7621_pcie *pcie,
 					 struct list_head *res)
 {
@@ -764,67 +802,7 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 	pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
 	pcie_write(pcie, RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
 
-	//PCIe0
-	if ((pcie_link_status & 0x1) != 0) {
-		/* open 7FFF:2G; ENABLE */
-		pcie_write(pcie, 0x7FFF0001,
-			   RT6855_PCIE0_OFFSET + RALINK_PCI_BAR0SETUP_ADDR);
-		pcie_write(pcie, MEMORY_BASE,
-			   RT6855_PCIE0_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
-		pcie_write(pcie, 0x06040001,
-			   RT6855_PCIE0_OFFSET + RALINK_PCI_CLASS);
-		dev_info(dev, "PCIE0 enabled\n");
-	}
-
-	//PCIe1
-	if ((pcie_link_status & 0x2) != 0) {
-		/* open 7FFF:2G; ENABLE */
-		pcie_write(pcie, 0x7FFF0001,
-			   RT6855_PCIE1_OFFSET + RALINK_PCI_BAR0SETUP_ADDR);
-		pcie_write(pcie, MEMORY_BASE,
-			   RT6855_PCIE1_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
-		pcie_write(pcie, 0x06040001,
-			   RT6855_PCIE1_OFFSET + RALINK_PCI_CLASS);
-		dev_info(dev, "PCIE1 enabled\n");
-	}
-
-	//PCIe2
-	if ((pcie_link_status & 0x4) != 0) {
-		/* open 7FFF:2G; ENABLE */
-		pcie_write(pcie, 0x7FFF0001,
-			   RT6855_PCIE2_OFFSET + RALINK_PCI_BAR0SETUP_ADDR);
-		pcie_write(pcie, MEMORY_BASE,
-			   RT6855_PCIE2_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
-		pcie_write(pcie, 0x06040001,
-			   RT6855_PCIE2_OFFSET + RALINK_PCI_CLASS);
-		dev_info(dev, "PCIE2 enabled\n");
-	}
-
-	switch (pcie_link_status) {
-	case 7:
-		val = read_config(pcie, 2, 0x4);
-		write_config(pcie, 2, 0x4, val | 0x4);
-		val = read_config(pcie, 2, 0x70c);
-		val &= ~(0xff) << 8;
-		val |= 0x50 << 8;
-		write_config(pcie, 2, 0x70c, val);
-	case 3:
-	case 5:
-	case 6:
-		val = read_config(pcie, 1, 0x4);
-		write_config(pcie, 1, 0x4, val | 0x4);
-		val = read_config(pcie, 1, 0x70c);
-		val &= ~(0xff) << 8;
-		val |= 0x50 << 8;
-		write_config(pcie, 1, 0x70c, val);
-	default:
-		val = read_config(pcie, 0, 0x4);
-		write_config(pcie, 0, 0x4, val | 0x4); //bus master enable
-		val = read_config(pcie, 0, 0x70c);
-		val &= ~(0xff) << 8;
-		val |= 0x50 << 8;
-		write_config(pcie, 0, 0x70c, val);
-	}
+	mt7621_pcie_enable_ports(pcie);
 
 	err = mt7621_pci_parse_request_of_pci_ranges(pcie);
 	if (err) {
-- 
2.7.4

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[PATCH v6 19/33] staging: mt7621-pci: avoid use of global variable 'pcie_link_status'

[Sergio Paracuellos]

'pcie_link_status' is a global variable which is being used as a
mask to know which virtual bridges are or not enabled. Instead of
this extract a new 'mt7621_pcie_init_virtual_bridges' function where
a similar local variable is used for the same task. This allow us to
properly configure the virtual PCI-PCI bridges in configuration
registers of the mt7621 pci controller. For a correct initiation of
which is connected use 'enabled' field of 'mt7621_pcie_port' struct.
With this change driver probe function gets a bit cleaner and readable.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 125 +++++++++++++++++++-------------
 1 file changed, 75 insertions(+), 50 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 5f07b53..50c439b 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -64,6 +64,14 @@
 #define MT7621_PCIE_OFFSET		0x2000
 #define MT7621_NEXT_PORT		0x1000
 
+#define MT7621_BR0_MASK			GENMASK(19, 16)
+#define MT7621_BR1_MASK			GENMASK(23, 20)
+#define MT7621_BR2_MASK			GENMASK(27, 24)
+#define MT7621_BR_ALL_MASK		GENMASK(27, 16)
+#define MT7621_BR0_SHIFT		16
+#define MT7621_BR1_SHIFT		20
+#define MT7621_BR2_SHIFT		24
+
 #define RALINK_PCI_BAR0SETUP_ADDR	0x0010
 #define RALINK_PCI_IMBASEBAR0_ADDR	0x0018
 #define RALINK_PCI_ID			0x0030
@@ -82,8 +90,6 @@
 
 #define MEMORY_BASE 0x0
 
-static int pcie_link_status;
-
 /* pcie phy related macros */
 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET	0x9000
 #define RALINK_PCIEPHY_P2_CTL_OFFSET	0xA000
@@ -589,10 +595,8 @@ static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
 		dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", slot);
 		reset_control_assert(port->pcie_rst);
 		rt_sysc_m32(BIT(24 + slot), 0, RALINK_CLKCFG1);
-		pcie_link_status &= ~(1 << slot);
 		port->enabled = false;
 	} else {
-		pcie_link_status |= BIT(slot);
 		port->enabled = true;
 		val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
 		/* enable pcie interrupt */
@@ -643,6 +647,70 @@ static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
 	}
 }
 
+static int mt7621_pcie_init_virtual_bridges(struct mt7621_pcie *pcie)
+{
+	u32 pcie_link_status = 0;
+	u32 val= 0;
+	struct mt7621_pcie_port *port;
+
+	list_for_each_entry(port, &pcie->ports, list) {
+		u32 slot = port->slot;
+
+		if (port->enabled)
+			pcie_link_status |= BIT(slot);
+	}
+
+	if (pcie_link_status == 0)
+		return -1;
+
+	/*
+	 * pcie(2/1/0) link status pcie2_num	pcie1_num	pcie0_num
+	 * 3'b000		   x	        x		x
+	 * 3'b001		   x	        x		0
+	 * 3'b010		   x	        0		x
+	 * 3'b011		   x	        1		0
+	 * 3'b100		   0	        x		x
+	 * 3'b101	           1 	        x		0
+	 * 3'b110	           1	        0		x
+	 * 3'b111		   2	        1		0
+	 */
+	switch (pcie_link_status) {
+	case 2:
+		val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+		val &= ~(MT7621_BR0_MASK | MT7621_BR1_MASK);
+		val |= 0x1 << MT7621_BR0_SHIFT;
+		val |= 0x0 << MT7621_BR1_SHIFT;
+		pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
+		break;
+	case 4:
+		val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+		val &= ~MT7621_BR_ALL_MASK;
+		val |= 0x1 << MT7621_BR0_SHIFT;
+		val |= 0x2 << MT7621_BR1_SHIFT;
+		val |= 0x0 << MT7621_BR2_SHIFT;
+		pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
+		break;
+	case 5:
+		val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+		val &= ~MT7621_BR_ALL_MASK;
+		val |= 0x0 << MT7621_BR0_SHIFT;
+		val |= 0x2 << MT7621_BR1_SHIFT;
+		val |= 0x1 << MT7621_BR2_SHIFT;
+		pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
+		break;
+	case 6:
+		val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+		val &= ~MT7621_BR_ALL_MASK;
+		val |= 0x2 << MT7621_BR0_SHIFT;
+		val |= 0x0 << MT7621_BR1_SHIFT;
+		val |= 0x1 << MT7621_BR2_SHIFT;
+		pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
+		break;
+	}
+
+	return 0;
+}
+
 static int mt7621_pcie_request_resources(struct mt7621_pcie *pcie,
 					 struct list_head *res)
 {
@@ -693,7 +761,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	struct pci_host_bridge *bridge;
 	struct mt7621_pcie_port *port, *tmp;
 	int err;
-	u32 val = 0;
 	LIST_HEAD(res);
 
 	if (!dev->of_node)
@@ -751,52 +818,10 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	*(unsigned int *)(0xbe000620) |= BIT(19) | BIT(8) | BIT(7);		// set DATA
 	mdelay(1000);
 
-	if (pcie_link_status == 0)
+	err = mt7621_pcie_init_virtual_bridges(pcie);
+	if (err) {
+		dev_err(dev, "Nothing is connected in virtual bridges. Exiting...");
 		return 0;
-
-/*
-pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
-3'b000			x		x		x
-3'b001			x		x		0
-3'b010			x		0		x
-3'b011			x		1		0
-3'b100			0		x		x
-3'b101			1		x		0
-3'b110			1		0		x
-3'b111			2		1		0
-*/
-	switch (pcie_link_status) {
-	case 2:
-		val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
-		val &= ~0x00ff0000;
-		val |= 0x1 << 16;	// port 0
-		val |= 0x0 << 20;	// port 1
-		pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
-		break;
-	case 4:
-		val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
-		val &= ~0x0fff0000;
-		val |= 0x1 << 16;	//port0
-		val |= 0x2 << 20;	//port1
-		val |= 0x0 << 24;	//port2
-		pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
-		break;
-	case 5:
-		val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
-		val &= ~0x0fff0000;
-		val |= 0x0 << 16;	//port0
-		val |= 0x2 << 20;	//port1
-		val |= 0x1 << 24;	//port2
-		pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
-		break;
-	case 6:
-		val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
-		val &= ~0x0fff0000;
-		val |= 0x2 << 16;	//port0
-		val |= 0x0 << 20;	//port1
-		val |= 0x1 << 24;	//port2
-		pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
-		break;
 	}
 
 	pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
-- 
2.7.4

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[PATCH v6 20/33] staging: mt7621-pci: factor out 'mt7621_pcie_init_ports' function

[Sergio Paracuellos]

Instead of just inline this code in the probe driver function factor
out a new 'mt7621_pcie_init_ports' function to achieve this.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 50c439b..cb677cd 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -612,6 +612,23 @@ static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
 	return 0;
 }
 
+static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
+{
+	struct device *dev = pcie->dev;
+	struct mt7621_pcie_port *port, *tmp;
+	int err;
+
+	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
+		u32 slot = port->slot;
+
+		err = mt7621_pcie_init_port(port);
+		if (err) {
+			dev_err(dev, "Initiating port %d failed\n", slot);
+			list_del(&port->list);
+		}
+	}
+}
+
 static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
 {
 	struct device *dev = pcie->dev;
@@ -759,7 +776,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct mt7621_pcie *pcie;
 	struct pci_host_bridge *bridge;
-	struct mt7621_pcie_port *port, *tmp;
 	int err;
 	LIST_HEAD(res);
 
@@ -794,15 +810,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 
 	mdelay(100);
 
-	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
-		u32 slot = port->slot;
-
-		err = mt7621_pcie_init_port(port);
-		if (err) {
-			dev_err(dev, "enabling port %d failed\n", slot);
-			list_del(&port->list);
-		}
-	}
+	mt7621_pcie_init_ports(pcie);
 
 	rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
 	rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
-- 
2.7.4

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[PATCH v6 21/33] staging: mt7621-pci: remove unused preprocessor definitions

[Sergio Paracuellos]

There are some preprocessor definition which are not being used at
all. Remove them cleaning the code a bit.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index cb677cd..36436b1 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -43,10 +43,6 @@
 #define CHIP_REV_MT7621_E2		0x0101
 
 /* pcie */
-#define RALINK_PCIE0_CLK_EN		BIT(24)
-#define RALINK_PCIE1_CLK_EN		BIT(25)
-#define RALINK_PCIE2_CLK_EN		BIT(26)
-
 #define RALINK_PCI_CONFIG_ADDR		0x20
 #define RALINK_PCI_CONFIG_DATA		0x24
 #define RALINK_PCI_MEMBASE		0x28
@@ -54,9 +50,6 @@
 
 /* RALINK_RSTCTRL bits */
 #define RALINK_PCIE_RST			BIT(23)
-#define RALINK_PCIE0_RST		BIT(24)
-#define RALINK_PCIE1_RST		BIT(25)
-#define RALINK_PCIE2_RST		BIT(26)
 
 #define RALINK_PCI_PCICFG_ADDR		0x0000
 #define RALINK_PCI_PCIMSK_ADDR		0x000C
@@ -79,12 +72,10 @@
 #define RALINK_PCI_SUBID		0x0038
 #define RALINK_PCI_STATUS		0x0050
 
-#define RALINK_PCI_MM_MAP_BASE		0x60000000
 #define RALINK_PCI_IO_MAP_BASE		0x1e160000
 
 #define RALINK_CLKCFG1			0x30
 #define RALINK_RSTCTRL			0x34
-#define RALINK_GPIOMODE			0x60
 #define RALINK_PCIE_CLK_GEN		0x7c
 #define RALINK_PCIE_CLK_GEN1		0x80
 
-- 
2.7.4

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[PATCH v6 22/33] staging: mt7621-pci: reorder preprocessor definitions

[Sergio Paracuellos]

Reorder a bit register definitions and some values into
logical groups adding some comments for each group. Also
unify all of register to use 16 bit in definitions instead
of having some with 16 bits and some with 8 bits.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 34 +++++++++++++++++----------------
 1 file changed, 18 insertions(+), 16 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 36436b1..1f764ad 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -39,24 +39,27 @@
 
 /* sysctl */
 #define MT7621_CHIP_REV_ID		0x0c
+#define RALINK_CLKCFG1			0x30
+#define RALINK_RSTCTRL			0x34
 #define MT7621_GPIO_MODE		0x60
 #define CHIP_REV_MT7621_E2		0x0101
 
-/* pcie */
-#define RALINK_PCI_CONFIG_ADDR		0x20
-#define RALINK_PCI_CONFIG_DATA		0x24
-#define RALINK_PCI_MEMBASE		0x28
-#define RALINK_PCI_IOBASE		0x2C
-
 /* RALINK_RSTCTRL bits */
 #define RALINK_PCIE_RST			BIT(23)
 
+/* rt_sysc_membase relative registers */
+#define RALINK_PCIE_CLK_GEN		0x7c
+#define RALINK_PCIE_CLK_GEN1		0x80
+
+/* Host-PCI bridge registers */
 #define RALINK_PCI_PCICFG_ADDR		0x0000
 #define RALINK_PCI_PCIMSK_ADDR		0x000C
+#define RALINK_PCI_CONFIG_ADDR		0x0020
+#define RALINK_PCI_CONFIG_DATA		0x0024
+#define RALINK_PCI_MEMBASE		0x0028
+#define RALINK_PCI_IOBASE		0x002C
 
-#define MT7621_PCIE_OFFSET		0x2000
-#define MT7621_NEXT_PORT		0x1000
-
+/* PCICFG virtual bridges */
 #define MT7621_BR0_MASK			GENMASK(19, 16)
 #define MT7621_BR1_MASK			GENMASK(23, 20)
 #define MT7621_BR2_MASK			GENMASK(27, 24)
@@ -65,6 +68,10 @@
 #define MT7621_BR1_SHIFT		20
 #define MT7621_BR2_SHIFT		24
 
+/* PCIe RC control registers */
+#define MT7621_PCIE_OFFSET		0x2000
+#define MT7621_NEXT_PORT		0x1000
+
 #define RALINK_PCI_BAR0SETUP_ADDR	0x0010
 #define RALINK_PCI_IMBASEBAR0_ADDR	0x0018
 #define RALINK_PCI_ID			0x0030
@@ -72,14 +79,9 @@
 #define RALINK_PCI_SUBID		0x0038
 #define RALINK_PCI_STATUS		0x0050
 
+/* Some definition values */
 #define RALINK_PCI_IO_MAP_BASE		0x1e160000
-
-#define RALINK_CLKCFG1			0x30
-#define RALINK_RSTCTRL			0x34
-#define RALINK_PCIE_CLK_GEN		0x7c
-#define RALINK_PCIE_CLK_GEN1		0x80
-
-#define MEMORY_BASE 0x0
+#define MEMORY_BASE			0x0
 
 /* pcie phy related macros */
 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET	0x9000
-- 
2.7.4

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[PATCH v6 23/33] staging: mt7621-pci: remove non sense comment

[Sergio Paracuellos]

There is a comment at the beggining which has no sense at all.
Remove it.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 1f764ad..5d15129 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -32,11 +32,6 @@
 
 #include "../../pci/pci.h"
 
-/*
- * These functions and structures provide the BIOS scan and mapping of the PCI
- * devices.
- */
-
 /* sysctl */
 #define MT7621_CHIP_REV_ID		0x0c
 #define RALINK_CLKCFG1			0x30
-- 
2.7.4

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[PATCH v6 24/33] staging: mt7621-pci: align function definition style along the code

[Sergio Paracuellos]

Make some function definition changes in order to get all the
functions in the code with the same style.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 5d15129..cca9a82 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -235,8 +235,7 @@ struct pci_ops mt7621_pci_ops = {
 	.write		= pci_generic_config_write,
 };
 
-static u32
-read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
+static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
 {
 	u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
 
@@ -244,8 +243,8 @@ read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
 	return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
 }
 
-static void
-write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val)
+static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
+			 u32 reg, u32 val)
 {
 	u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
 
@@ -253,8 +252,7 @@ write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val)
 	pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
 }
 
-static void
-bypass_pipe_rst(struct mt7621_pcie_port *port)
+static void bypass_pipe_rst(struct mt7621_pcie_port *port)
 {
 	struct mt7621_pcie *pcie = port->pcie;
 	u32 phy_offset = port->phy_reg_offset;
@@ -268,8 +266,7 @@ bypass_pipe_rst(struct mt7621_pcie_port *port)
 	pcie_write(pcie, reg, offset);
 }
 
-static void
-set_phy_for_ssc(struct mt7621_pcie_port *port)
+static void set_phy_for_ssc(struct mt7621_pcie_port *port)
 {
 	struct mt7621_pcie *pcie = port->pcie;
 	struct device *dev = pcie->dev;
-- 
2.7.4

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[PATCH v6 25/33] staging: mt7621-pci: rewrite RC FTS configuration

[Sergio Paracuellos]

The RC FTS configuration is done using hardcoded registers
and bitshift operations. Make it a bit clean defining some
prepocessor definitions and simple macros.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index cca9a82..604b287 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -42,6 +42,11 @@
 /* RALINK_RSTCTRL bits */
 #define RALINK_PCIE_RST			BIT(23)
 
+/* MediaTek specific configuration registers */
+#define PCIE_FTS_NUM			0x70c
+#define PCIE_FTS_NUM_MASK		GENMASK(15, 8)
+#define PCIE_FTS_NUM_L0(x)		((x) & 0xff << 8)
+
 /* rt_sysc_membase relative registers */
 #define RALINK_PCIE_CLK_GEN		0x7c
 #define RALINK_PCIE_CLK_GEN1		0x80
@@ -591,7 +596,7 @@ static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
 
 	mt7621_enable_phy(port);
 
-	val = read_config(pcie, slot, 0x70c);
+	val = read_config(pcie, slot, PCIE_FTS_NUM);
 	dev_info(dev, "Port %d N_FTS = %x\n", (unsigned int)val, slot);
 
 	return 0;
@@ -642,10 +647,11 @@ static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
 	for (slot = 0; slot < num_slots_enabled; slot++) {
 		val = read_config(pcie, slot, 0x4);
 		write_config(pcie, slot, 0x4, val | 0x4);
-		val = read_config(pcie, slot, 0x70c);
-		val &= ~(0xff) << 8;
-		val |= 0x50 << 8;
-		write_config(pcie, slot, 0x70c, val);
+		/* configure RC FTS number to 250 when it leaves L0s */
+		val = read_config(pcie, slot, PCIE_FTS_NUM);
+		val &= ~PCIE_FTS_NUM_MASK;
+		val |= PCIE_FTS_NUM_L0(0x50);
+		write_config(pcie, slot, PCIE_FTS_NUM, val);
 	}
 }
 
-- 
2.7.4

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[PATCH v6 26/33] staging: mt7621-pci: rewrite hardcoded code for enabling ports

[Sergio Paracuellos]

There are some hardcoded values in the process for enabling and
disabling some stuff inside 'mt7621_pcie_enable_ports' function.
Create some preprocessor definitions to make code more readable.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 604b287..0e898a4 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -80,6 +80,13 @@
 #define RALINK_PCI_STATUS		0x0050
 
 /* Some definition values */
+#define PCIE_REVISION_ID		BIT(0)
+#define PCIE_CLASS_CODE			(0x60400 << 8)
+#define PCIE_BAR_MAP_MAX		GENMASK(30, 16)
+#define PCIE_BAR_ENABLE			BIT(0)
+#define PCIE_PORT_INT_EN(x)		BIT(20 + (x))
+#define PCIE_PORT_CLK_EN(x)		BIT(24 + (x))
+
 #define RALINK_PCI_IO_MAP_BASE		0x1e160000
 #define MEMORY_BASE			0x0
 
@@ -584,13 +591,13 @@ static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
 	if ((pcie_port_read(port, RALINK_PCI_STATUS) & 0x1) == 0) {
 		dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", slot);
 		reset_control_assert(port->pcie_rst);
-		rt_sysc_m32(BIT(24 + slot), 0, RALINK_CLKCFG1);
+		rt_sysc_m32(PCIE_PORT_CLK_EN(slot), 0, RALINK_CLKCFG1);
 		port->enabled = false;
 	} else {
 		port->enabled = true;
-		val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
 		/* enable pcie interrupt */
-		val |= BIT(20 + slot);
+		val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+		val |= PCIE_PORT_INT_EN(slot);
 		pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
 	}
 
@@ -633,12 +640,14 @@ static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
 		offset = MT7621_PCIE_OFFSET + (slot * MT7621_NEXT_PORT);
 
 		if (port->enabled) {
-			/* open 7FFF:2G; ENABLE */
-			pcie_write(pcie, 0x7FFF0001,
+			/* map 2G DDR region */
+			pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
 				   offset + RALINK_PCI_BAR0SETUP_ADDR);
 			pcie_write(pcie, MEMORY_BASE,
 				   offset + RALINK_PCI_IMBASEBAR0_ADDR);
-			pcie_write(pcie, 0x06040001, offset + RALINK_PCI_CLASS);
+			/* configure class code and revision ID */
+			pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID,
+				   offset + RALINK_PCI_CLASS);
 			dev_info(dev, "PCIE%d enabled\n", slot);
 			num_slots_enabled++;
 		}
-- 
2.7.4

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[PATCH v6 27/33] staging: mt7621-pci: add some definitions for enabling and disabling GEN and GEN1 clocks

[Sergio Paracuellos]

Instead of use hardcoded values when calling 'rt_sysc_m32' for enabling
and disabling RALINK_PCIE_CLK_GEN and RALINK_PCIE_CLK_GEN1 create
some preprocessor definitions.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 0e898a4..0c78cc2 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -87,6 +87,10 @@
 #define PCIE_PORT_INT_EN(x)		BIT(20 + (x))
 #define PCIE_PORT_CLK_EN(x)		BIT(24 + (x))
 
+#define PCIE_CLK_GEN_EN			BIT(31)
+#define PCIE_CLK_GEN_DIS		0
+#define PCIE_CLK_GEN1_DIS		GENMASK(30,24)
+#define PCIE_CLK_GEN1_EN		(BIT(27) | BIT(25))
 #define RALINK_PCI_IO_MAP_BASE		0x1e160000
 #define MEMORY_BASE			0x0
 
@@ -815,9 +819,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
 	rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
 
-	rt_sysc_m32(0x80000000, 0, RALINK_PCIE_CLK_GEN);
-	rt_sysc_m32(0x7f000000, 0xa << 24, RALINK_PCIE_CLK_GEN1);
-	rt_sysc_m32(0, 0x80000000, RALINK_PCIE_CLK_GEN);
+	rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN);
+	rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1);
+	rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN);
 
 	mdelay(50);
 	rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL);
-- 
2.7.4

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[PATCH v6 28/33] staging: mt7621-pci: use PERST_N instead of gpio control

[Sergio Paracuellos]

Driver is using gpio control instead of each port PERST_N
bit. Use PERST_N bit of each port cleaning all the ugly
gpio code in driver probe function.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 46 +++++++++++++++++----------------
 1 file changed, 24 insertions(+), 22 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 0c78cc2..7fa37b6 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -18,6 +18,7 @@
 #include <linux/bitops.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
+#include <linux/iopoll.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
@@ -36,7 +37,6 @@
 #define MT7621_CHIP_REV_ID		0x0c
 #define RALINK_CLKCFG1			0x30
 #define RALINK_RSTCTRL			0x34
-#define MT7621_GPIO_MODE		0x60
 #define CHIP_REV_MT7621_E2		0x0101
 
 /* RALINK_RSTCTRL bits */
@@ -86,6 +86,8 @@
 #define PCIE_BAR_ENABLE			BIT(0)
 #define PCIE_PORT_INT_EN(x)		BIT(20 + (x))
 #define PCIE_PORT_CLK_EN(x)		BIT(24 + (x))
+#define PCIE_PORT_PERST(x)		BIT(1 + (x))
+#define PCIE_PORT_LINKUP		BIT(0)
 
 #define PCIE_CLK_GEN_EN			BIT(31)
 #define PCIE_CLK_GEN_DIS		0
@@ -638,12 +640,33 @@ static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
 	u32 offset;
 	u32 slot;
 	u32 val;
+	int err;
 
 	list_for_each_entry(port, &pcie->ports, list) {
 		slot = port->slot;
 		offset = MT7621_PCIE_OFFSET + (slot * MT7621_NEXT_PORT);
 
 		if (port->enabled) {
+			/* assert port PERST_N */
+			val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+			val |= PCIE_PORT_PERST(slot);
+			pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
+
+			/* de-assert port PERST_N */
+			val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+			val &= ~PCIE_PORT_PERST(slot);
+			pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
+
+			/* 100ms timeout value should be enough for Gen1 training */
+			err = readl_poll_timeout(port->base + RALINK_PCI_STATUS,
+						 val,!!(val & PCIE_PORT_LINKUP),
+						 20, 100 * USEC_PER_MSEC);
+			if (err) {
+				dev_err(dev, "de-assert port %d PERST_N\n",
+					slot);
+				continue;
+			}
+
 			/* map 2G DDR region */
 			pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
 				   offset + RALINK_PCI_BAR0SETUP_ADDR);
@@ -765,16 +788,6 @@ static int mt7621_pcie_register_host(struct pci_host_bridge *host,
 	return pci_host_probe(host);
 }
 
-static void mt7621_set_gpio_mode(struct mt7621_pcie *pcie)
-{
-	u32 reg = ioread32(pcie->sysctl + MT7621_GPIO_MODE);
-
-	reg &= ~(0x3 << 10 | 0x3 << 3);
-	reg |= (BIT(10) | BIT(3));
-	iowrite32(reg, pcie->sysctl + MT7621_GPIO_MODE);
-	mdelay(100);
-}
-
 static int mt7621_pci_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -807,13 +820,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	ioport_resource.start = 0;
 	ioport_resource.end = ~0UL; /* no limit */
 
-	mt7621_set_gpio_mode(pcie);
-	*(unsigned int *)(0xbe000600) |= BIT(19) | BIT(8) | BIT(7); // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
-	mdelay(100);
-	*(unsigned int *)(0xbe000620) &= ~(BIT(19) | BIT(8) | BIT(7));		// clear DATA
-
-	mdelay(100);
-
 	mt7621_pcie_init_ports(pcie);
 
 	rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
@@ -826,10 +832,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	mdelay(50);
 	rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL);
 
-	/* Use GPIO control instead of PERST_N */
-	*(unsigned int *)(0xbe000620) |= BIT(19) | BIT(8) | BIT(7);		// set DATA
-	mdelay(1000);
-
 	err = mt7621_pcie_init_virtual_bridges(pcie);
 	if (err) {
 		dev_err(dev, "Nothing is connected in virtual bridges. Exiting...");
-- 
2.7.4

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[PATCH v6 29/33] staging: mt7621-pci: use PCIE_PORT_LINKUP instead of hardcode value

[Sergio Paracuellos]

PCIE_PORT_LINKUP is defined and can be used to check if link is up
for each controller. Use it instead of use a hardcode value.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 7fa37b6..8b7c63d 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -594,7 +594,7 @@ static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
 	reset_control_assert(port->pcie_rst);
 	reset_control_deassert(port->pcie_rst);
 
-	if ((pcie_port_read(port, RALINK_PCI_STATUS) & 0x1) == 0) {
+	if ((pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) == 0) {
 		dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", slot);
 		reset_control_assert(port->pcie_rst);
 		rt_sysc_m32(PCIE_PORT_CLK_EN(slot), 0, RALINK_CLKCFG1);
-- 
2.7.4

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[PATCH v6 30/33] staging: mt7621-pci: enable interrupt when port is being enabled

[Sergio Paracuellos]

Interrupt is being enabled in port initialization when the port phy
has not been initialized yet. Just enable the interrupt when the port
is being enabled which is a more accurate place for this.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 8b7c63d..5f7ff70 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -601,10 +601,6 @@ static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
 		port->enabled = false;
 	} else {
 		port->enabled = true;
-		/* enable pcie interrupt */
-		val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
-		val |= PCIE_PORT_INT_EN(slot);
-		pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
 	}
 
 	mt7621_enable_phy(port);
@@ -667,6 +663,11 @@ static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
 				continue;
 			}
 
+			/* enable pcie interrupt */
+			val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+			val |= PCIE_PORT_INT_EN(slot);
+			pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
+
 			/* map 2G DDR region */
 			pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
 				   offset + RALINK_PCI_BAR0SETUP_ADDR);
-- 
2.7.4

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[PATCH v6 31/33] staging: mt7621-pci: factor out 'mt7621_pcie_enable_port' function

[Sergio Paracuellos]

Function 'mt7621_pcie_enable_ports' tries to enable all PCI ports.
To make it more readable the single port initialization part has
been factor out into a new 'mt7621_pcie_enable_port' function.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 80 ++++++++++++++++++---------------
 1 file changed, 45 insertions(+), 35 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 5f7ff70..a069d7f 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -628,54 +628,64 @@ static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
 	}
 }
 
+static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
+{
+	struct mt7621_pcie *pcie = port->pcie;
+	u32 slot = port->slot;
+	u32 offset = MT7621_PCIE_OFFSET + (slot * MT7621_NEXT_PORT);
+	u32 val;
+	int err;
+
+	/* assert port PERST_N */
+	val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+	val |= PCIE_PORT_PERST(slot);
+	pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
+
+	/* de-assert port PERST_N */
+	val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+	val &= ~PCIE_PORT_PERST(slot);
+	pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
+
+	/* 100ms timeout value should be enough for Gen1 training */
+	err = readl_poll_timeout(port->base + RALINK_PCI_STATUS,
+				 val, !!(val & PCIE_PORT_LINKUP),
+				 20, 100 * USEC_PER_MSEC);
+	if (err)
+		return -ETIMEDOUT;
+
+	/* enable pcie interrupt */
+	val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+	val |= PCIE_PORT_INT_EN(slot);
+	pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
+
+	/* map 2G DDR region */
+	pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
+		   offset + RALINK_PCI_BAR0SETUP_ADDR);
+	pcie_write(pcie, MEMORY_BASE,
+		   offset + RALINK_PCI_IMBASEBAR0_ADDR);
+
+	/* configure class code and revision ID */
+	pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID,
+		   offset + RALINK_PCI_CLASS);
+
+	return 0;
+}
+
 static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
 {
 	struct device *dev = pcie->dev;
 	struct mt7621_pcie_port *port;
 	u8 num_slots_enabled = 0;
-	u32 offset;
 	u32 slot;
 	u32 val;
-	int err;
 
 	list_for_each_entry(port, &pcie->ports, list) {
-		slot = port->slot;
-		offset = MT7621_PCIE_OFFSET + (slot * MT7621_NEXT_PORT);
-
 		if (port->enabled) {
-			/* assert port PERST_N */
-			val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
-			val |= PCIE_PORT_PERST(slot);
-			pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
-
-			/* de-assert port PERST_N */
-			val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
-			val &= ~PCIE_PORT_PERST(slot);
-			pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
-
-			/* 100ms timeout value should be enough for Gen1 training */
-			err = readl_poll_timeout(port->base + RALINK_PCI_STATUS,
-						 val,!!(val & PCIE_PORT_LINKUP),
-						 20, 100 * USEC_PER_MSEC);
-			if (err) {
+			if (!mt7621_pcie_enable_port(port)) {
 				dev_err(dev, "de-assert port %d PERST_N\n",
-					slot);
+					port->slot);
 				continue;
 			}
-
-			/* enable pcie interrupt */
-			val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
-			val |= PCIE_PORT_INT_EN(slot);
-			pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
-
-			/* map 2G DDR region */
-			pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
-				   offset + RALINK_PCI_BAR0SETUP_ADDR);
-			pcie_write(pcie, MEMORY_BASE,
-				   offset + RALINK_PCI_IMBASEBAR0_ADDR);
-			/* configure class code and revision ID */
-			pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID,
-				   offset + RALINK_PCI_CLASS);
 			dev_info(dev, "PCIE%d enabled\n", slot);
 			num_slots_enabled++;
 		}
-- 
2.7.4

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[PATCH v6 32/33] staging: mt7621-pci: move some code into 'mt7621_pcie_init_ports'

[Sergio Paracuellos]

Some clocks bits related code is in driver probe function and can
perfectly be moved into 'mt7621_pcie_init_ports' function which is
a more accurate place for it.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index a069d7f..fb9aa6b 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -626,6 +626,14 @@ static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
 			list_del(&port->list);
 		}
 	}
+
+	rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
+	rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
+	rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN);
+	rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1);
+	rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN);
+	mdelay(50);
+	rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL);
 }
 
 static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
@@ -833,16 +841,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 
 	mt7621_pcie_init_ports(pcie);
 
-	rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
-	rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
-
-	rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN);
-	rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1);
-	rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN);
-
-	mdelay(50);
-	rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL);
-
 	err = mt7621_pcie_init_virtual_bridges(pcie);
 	if (err) {
 		dev_err(dev, "Nothing is connected in virtual bridges. Exiting...");
-- 
2.7.4

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[PATCH v6 33/33] staging: mt7621-pci: replace 'mdelay()' with 'msleep()'

[Sergio Paracuellos]

Function 'mt7621_pcie_init_ports' is never called in atomic context.
It calls mdelay() to busily wait, which is not necessary. mdelay()
can be replaced with msleep().

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index fb9aa6b..14cec23 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -632,7 +632,7 @@ static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
 	rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN);
 	rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1);
 	rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN);
-	mdelay(50);
+	msleep(50);
 	rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL);
 }
 
-- 
2.7.4

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Re: [PATCH v6 33/33] staging: mt7621-pci: replace 'mdelay()' with 'msleep()'

[Frans Klaver]

On Sun, Nov 4, 2018 at 11:51 AM Sergio Paracuellos
<sergio.paracuellos@gmail.com> wrote:
>
> Function 'mt7621_pcie_init_ports' is never called in atomic context.
> It calls mdelay() to busily wait, which is not necessary. mdelay()
> can be replaced with msleep().
>
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---
>  drivers/staging/mt7621-pci/pci-mt7621.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
> index fb9aa6b..14cec23 100644
> --- a/drivers/staging/mt7621-pci/pci-mt7621.c
> +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
> @@ -632,7 +632,7 @@ static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
>         rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN);
>         rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1);
>         rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN);
> -       mdelay(50);
> +       msleep(50);
>         rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL);

>From a software point of view it makes sense to remove the busy-wait.
>From a hardware perspective it may still make sense to keep it. Can
you guarantee that the PCIE_RST is done at the correct time. I haven't
looked thoroughly at the datasheet yet, but I can imagine the level
has to shift within a certain time frame? Or doesn't that make too
much of a difference? Perhaps mention that in your commit message?
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Re: [PATCH v6 33/33] staging: mt7621-pci: replace 'mdelay()' with 'msleep()'

[Sergio Paracuellos]

On Mon, Nov 05, 2018 at 09:09:39AM +0100, Frans Klaver wrote:
> On Sun, Nov 4, 2018 at 11:51 AM Sergio Paracuellos
> <sergio.paracuellos@gmail.com> wrote:
> >
> > Function 'mt7621_pcie_init_ports' is never called in atomic context.
> > It calls mdelay() to busily wait, which is not necessary. mdelay()
> > can be replaced with msleep().
> >
> > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> > ---
> >  drivers/staging/mt7621-pci/pci-mt7621.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
> > index fb9aa6b..14cec23 100644
> > --- a/drivers/staging/mt7621-pci/pci-mt7621.c
> > +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
> > @@ -632,7 +632,7 @@ static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
> >         rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN);
> >         rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1);
> >         rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN);
> > -       mdelay(50);
> > +       msleep(50);
> >         rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL);

Hi Frans,
> 
> From a software point of view it makes sense to remove the busy-wait.
> From a hardware perspective it may still make sense to keep it. Can
> you guarantee that the PCIE_RST is done at the correct time. I haven't
> looked thoroughly at the datasheet yet, but I can imagine the level
> has to shift within a certain time frame? Or doesn't that make too
> much of a difference? Perhaps mention that in your commit message?

Thanks for the feedback. I agree with you that from a hardware point of
view keep this could make sense. The fact is that after reading the 
datasheet for me is not clear at all that in this concrete case it make
sense. I cannot also test this because I don't have the hardware to be able
to do (all the patches, as I said are only compile-tested). This is also
a reason to keep this patch as the last in this series to just skip it if
this fails when is tested.

Best regards,
    Sergio Paracuellos
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Re: [PATCH v6 00/33] staging: mt7621-pci: Parse ports info from DT and other minor cleanups

[Greg KH]

On Sun, Nov 04, 2018 at 11:49:26AM +0100, Sergio Paracuellos wrote:
> This patch series parse remaining port info from device tree storing
> it in mt7621_pcie_port struct created for this. It also performs a lot
> of cleanups to get the driver in a good shape to give it a try to get
> mainlined. All of this changes are only compile-tested.

Given the lack of responses here, I guess I'll just merge this and see
what happens :)

thanks,

greg k-h
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Re: [PATCH v6 00/33] staging: mt7621-pci: Parse ports info from DT and other minor cleanups

[NeilBrown]

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On Sun, Nov 11 2018, Greg KH wrote:

> On Sun, Nov 04, 2018 at 11:49:26AM +0100, Sergio Paracuellos wrote:
>> This patch series parse remaining port info from device tree storing
>> it in mt7621_pcie_port struct created for this. It also performs a lot
>> of cleanups to get the driver in a good shape to give it a try to get
>> mainlined. All of this changes are only compile-tested.
>
> Given the lack of responses here, I guess I'll just merge this and see
> what happens :)

Sounds like a good plan.
I had meant to look at it this past weekend, but ran out of time.
It is a bit awkward for me to test on mainline at the moment as

# first bad commit: [f8c55dc6e828324fc58c0bb32d72a5a4041d1c3b] MIPS: use generic dma noncoherent ops for simple noncoherent platforms

breaks mmc on my hardware, and my root filesystem is on mmc.

But I should still be able to get it tested sometime in the next couple
of weeks, and will provide feedback once I have it.

Thanks,
NeilBrown

>
> thanks,
>
> greg k-h

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Re: [PATCH v6 00/33] staging: mt7621-pci: Parse ports info from DT and other minor cleanups

[Sergio Paracuellos]

On Mon, Nov 12, 2018 at 08:40:10AM +1100, NeilBrown wrote:
> On Sun, Nov 11 2018, Greg KH wrote:
> 
> > On Sun, Nov 04, 2018 at 11:49:26AM +0100, Sergio Paracuellos wrote:
> >> This patch series parse remaining port info from device tree storing
> >> it in mt7621_pcie_port struct created for this. It also performs a lot
> >> of cleanups to get the driver in a good shape to give it a try to get
> >> mainlined. All of this changes are only compile-tested.
> >
> > Given the lack of responses here, I guess I'll just merge this and see
> > what happens :)
> 
> Sounds like a good plan.
> I had meant to look at it this past weekend, but ran out of time.
> It is a bit awkward for me to test on mainline at the moment as
> 
> # first bad commit: [f8c55dc6e828324fc58c0bb32d72a5a4041d1c3b] MIPS: use generic dma noncoherent ops for simple noncoherent platforms
> 
> breaks mmc on my hardware, and my root filesystem is on mmc.
> 
> But I should still be able to get it tested sometime in the next couple
> of weeks, and will provide feedback once I have it.

Thanks, Neil. Please, let me know if I can help in any way.

> 
> Thanks,
> NeilBrown

Best regards,
    Sergio Paracuellos
> 
> >
> > thanks,
> >
> > greg k-h


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Re: [PATCH v6 01/33] staging: mt7621-pci: parse and init port data from device tree

[NeilBrown]

[-- Attachment #1.1: Type: text/plain, Size: 4361 bytes --]

On Sun, Nov 04 2018, Sergio Paracuellos wrote:

> Add initialization of each PCIe port reading and initializing
> data using device tree.
>
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---
>  drivers/staging/mt7621-pci/pci-mt7621.c | 75 +++++++++++++++++++++++++++++++--
>  1 file changed, 71 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
> index 8371a9c..b7cb273 100644
> --- a/drivers/staging/mt7621-pci/pci-mt7621.c
> +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
> @@ -126,16 +126,20 @@ static int pcie_link_status;
>  
>  /**
>   * struct mt7621_pcie_port - PCIe port information
> - * @base: IO mapped register base
> + * @base: I/O mapped register base
>   * @list: port list
>   * @pcie: pointer to PCIe host info
> - * @reset: pointer to port reset control
> + * @pcie_rst: pointer to port reset control
> + * @pcie_clk: PCIe clock
> + * @slot: port slot
>   */
>  struct mt7621_pcie_port {
>  	void __iomem *base;
>  	struct list_head list;
>  	struct mt7621_pcie *pcie;
> -	struct reset_control *reset;
> +	struct reset_control *pcie_rst;
> +	struct clk *pcie_clk;
> +	u32 slot;
>  };
>  
>  /**
> @@ -382,10 +386,57 @@ static int mt7621_pci_parse_request_of_pci_ranges(struct mt7621_pcie *pcie)
>  	return 0;
>  }
>  
> +static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
> +				  struct device_node *node,
> +				  int slot)
> +{
> +	struct mt7621_pcie_port *port;
> +	struct device *dev = pcie->dev;
> +	struct device_node *pnode = dev->of_node;
> +	struct resource regs;
> +	char name[6];
> +	int err;
> +
> +	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
> +	if (!port)
> +		return -ENOMEM;
> +
> +	err = of_address_to_resource(pnode, slot + 1, &regs);
> +	if (err) {
> +		dev_err(dev, "missing \"reg\" property\n");
> +		return err;
> +	}
> +
> +	port->base = devm_ioremap_resource(dev, &regs);
> +	if (IS_ERR(port->base))
> +		return PTR_ERR(port->base);
> +
> +	snprintf(name, sizeof(name), "pcie%d", slot);
> +	port->pcie_clk = devm_clk_get(dev, name);
> +	if (IS_ERR(port->pcie_clk)) {
> +		dev_err(dev, "failed to get pcie%d clock\n", slot);
> +		return PTR_ERR(port->pcie_clk);
> +	}

This is problematic.
The clocks are defined in the dtsi as:

		clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
		clock-names = "pcie0", "pcie1", "pcie2";
and clkctrl is
	clkctrl: clkctrl {
		compatible = "ralink,rt2880-clock";
		#clock-cells = <1>;
	};

but there is no driver that declares compatibility with
ralink,rt2880-clock.
So devm_clk_get() cannot find any clocks, and returns an error.
I worked around this by just ignoring the error, but then something
else went wrong in a subsequent patch - haven't worked out what yet.

Probably the *right* way to fix this is to add a driver for
ralink,rt2880-clock but I don't know what such a driver would do.

In any case, I don't plan to pursue this particular issue further until
I understand the other things that are happening with this patch set.

Thanks,
NeilBrown



> +
> +	port->pcie_rst = devm_reset_control_get_exclusive(dev, name);
> +	if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
> +		dev_err(dev, "failed to get pcie%d reset control\n", slot);
> +		return PTR_ERR(port->pcie_rst);
> +	}
> +
> +	port->slot = slot;
> +	port->pcie = pcie;
> +
> +	INIT_LIST_HEAD(&port->list);
> +	list_add_tail(&port->list, &pcie->ports);
> +
> +	return 0;
> +}
> +
>  static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
>  {
>  	struct device *dev = pcie->dev;
> -	struct device_node *node = dev->of_node;
> +	struct device_node *node = dev->of_node, *child;
>  	struct resource regs;
>  	int err;
>  
> @@ -399,6 +450,22 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
>  	if (IS_ERR(pcie->base))
>  		return PTR_ERR(pcie->base);
>  
> +	for_each_available_child_of_node(node, child) {
> +		int slot;
> +
> +		err = of_pci_get_devfn(child);
> +		if (err < 0) {
> +			dev_err(dev, "failed to parse devfn: %d\n", err);
> +			return err;
> +		}
> +
> +		slot = PCI_SLOT(err);
> +
> +		err = mt7621_pcie_parse_port(pcie, child, slot);
> +		if (err)
> +			return err;
> +	}
> +
>  	return 0;
>  }
>  
> -- 
> 2.7.4

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Re: [PATCH v6 01/33] staging: mt7621-pci: parse and init port data from device tree

[Sergio Paracuellos]

On Sun, Nov 18, 2018 at 10:52 PM NeilBrown <neil@brown.name> wrote:
>
> On Sun, Nov 04 2018, Sergio Paracuellos wrote:
>
> > Add initialization of each PCIe port reading and initializing
> > data using device tree.
> >
> > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> > ---
> >  drivers/staging/mt7621-pci/pci-mt7621.c | 75 +++++++++++++++++++++++++++++++--
> >  1 file changed, 71 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
> > index 8371a9c..b7cb273 100644
> > --- a/drivers/staging/mt7621-pci/pci-mt7621.c
> > +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
> > @@ -126,16 +126,20 @@ static int pcie_link_status;
> >
> >  /**
> >   * struct mt7621_pcie_port - PCIe port information
> > - * @base: IO mapped register base
> > + * @base: I/O mapped register base
> >   * @list: port list
> >   * @pcie: pointer to PCIe host info
> > - * @reset: pointer to port reset control
> > + * @pcie_rst: pointer to port reset control
> > + * @pcie_clk: PCIe clock
> > + * @slot: port slot
> >   */
> >  struct mt7621_pcie_port {
> >       void __iomem *base;
> >       struct list_head list;
> >       struct mt7621_pcie *pcie;
> > -     struct reset_control *reset;
> > +     struct reset_control *pcie_rst;
> > +     struct clk *pcie_clk;
> > +     u32 slot;
> >  };
> >
> >  /**
> > @@ -382,10 +386,57 @@ static int mt7621_pci_parse_request_of_pci_ranges(struct mt7621_pcie *pcie)
> >       return 0;
> >  }
> >
> > +static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
> > +                               struct device_node *node,
> > +                               int slot)
> > +{
> > +     struct mt7621_pcie_port *port;
> > +     struct device *dev = pcie->dev;
> > +     struct device_node *pnode = dev->of_node;
> > +     struct resource regs;
> > +     char name[6];
> > +     int err;
> > +
> > +     port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
> > +     if (!port)
> > +             return -ENOMEM;
> > +
> > +     err = of_address_to_resource(pnode, slot + 1, &regs);
> > +     if (err) {
> > +             dev_err(dev, "missing \"reg\" property\n");
> > +             return err;
> > +     }
> > +
> > +     port->base = devm_ioremap_resource(dev, &regs);
> > +     if (IS_ERR(port->base))
> > +             return PTR_ERR(port->base);
> > +
> > +     snprintf(name, sizeof(name), "pcie%d", slot);
> > +     port->pcie_clk = devm_clk_get(dev, name);
> > +     if (IS_ERR(port->pcie_clk)) {
> > +             dev_err(dev, "failed to get pcie%d clock\n", slot);
> > +             return PTR_ERR(port->pcie_clk);
> > +     }
>
> This is problematic.
> The clocks are defined in the dtsi as:
>
>                 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
>                 clock-names = "pcie0", "pcie1", "pcie2";
> and clkctrl is
>         clkctrl: clkctrl {
>                 compatible = "ralink,rt2880-clock";
>                 #clock-cells = <1>;
>         };
>
> but there is no driver that declares compatibility with
> ralink,rt2880-clock.
> So devm_clk_get() cannot find any clocks, and returns an error.
> I worked around this by just ignoring the error, but then something
> else went wrong in a subsequent patch - haven't worked out what yet.
>
> Probably the *right* way to fix this is to add a driver for
> ralink,rt2880-clock but I don't know what such a driver would do.
>
> In any case, I don't plan to pursue this particular issue further until
> I understand the other things that are happening with this patch set.

Thanks for your time Neil in testing this.

If getting the clocks fail then we cannot get enable any port so I suspect the
next thing that gets wrong should be in 'mt7621_pcie_enable_port' when we try to
enable the clock for the port with the call to 'clk_prepare_enable'.

I though the ralink clock driver exists because of its references in
the dtsi file but
I didn't check for a compatible string in the sources. So I think is
my bad here.

Let me know any other thing you want to understand from this patchset
but I think the
actual code should be a clean way to go with this driver (maybe
separating also the phy
part to a phy-pci driver to get all cleaner). Let me know your opinion in this.

>
> Thanks,
> NeilBrown

Best regards,
    Sergio Paracuellos
>
>
>
> > +
> > +     port->pcie_rst = devm_reset_control_get_exclusive(dev, name);
> > +     if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
> > +             dev_err(dev, "failed to get pcie%d reset control\n", slot);
> > +             return PTR_ERR(port->pcie_rst);
> > +     }
> > +
> > +     port->slot = slot;
> > +     port->pcie = pcie;
> > +
> > +     INIT_LIST_HEAD(&port->list);
> > +     list_add_tail(&port->list, &pcie->ports);
> > +
> > +     return 0;
> > +}
> > +
> >  static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
> >  {
> >       struct device *dev = pcie->dev;
> > -     struct device_node *node = dev->of_node;
> > +     struct device_node *node = dev->of_node, *child;
> >       struct resource regs;
> >       int err;
> >
> > @@ -399,6 +450,22 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
> >       if (IS_ERR(pcie->base))
> >               return PTR_ERR(pcie->base);
> >
> > +     for_each_available_child_of_node(node, child) {
> > +             int slot;
> > +
> > +             err = of_pci_get_devfn(child);
> > +             if (err < 0) {
> > +                     dev_err(dev, "failed to parse devfn: %d\n", err);
> > +                     return err;
> > +             }
> > +
> > +             slot = PCI_SLOT(err);
> > +
> > +             err = mt7621_pcie_parse_port(pcie, child, slot);
> > +             if (err)
> > +                     return err;
> > +     }
> > +
> >       return 0;
> >  }
> >
> > --
> > 2.7.4

Re: [PATCH v6 04/33] staging: mt7621-pci: factor out 'mt7621_pcie_enable_port' function

[NeilBrown]

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On Sun, Nov 04 2018, Sergio Paracuellos wrote:

> Driver probe function is a mess and shall be refactored a lot. At first
> make use of assert and deassert control factoring out a new function
> called 'mt7621_pcie_enable_port'.

Testing continues....

there are 2.5 problems with this patch.

Firstly you changed the asserting of reset from

> -	ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);

to
> +	reset_control_assert(port->pcie_rst);
(for each port).
This looks reasonable, but doesn't work.

#define ASSERT_SYSRST_PCIE(val)		\
	do {								\
		if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101)	\
			rt_sysc_m32(0, val, RALINK_RSTCTRL);		\
		else							\
			rt_sysc_m32(val, 0, RALINK_RSTCTRL);		\
	} while (0)

If the CHIP_REV is 0x30101, then we set the bit to assert (and clear to
deassert).
This is what reset_control_assert() does - it maps through to
ralink_assert_device().
My CHIP_REV is 0x30103 - so this does the wrong thing.

Secondly you have moved the updating of RALINK_PCI_PCIMSK_ADDR (I'm
guess that is the import piece) to before the
 read_config(pcie, slot, 0x70c);
This seems to break things.
If I move the read_config/dev_info() inside the new
mt7621_pcie_enable_port(), just after the reset(), it starts working
again.

Finally, the 1/2 problem is that there was previously a 300 msec delay
between asserting reset and deasserting it - you've removed that.
It still seems to work, so maybe it is OK.  But often hardware prefers
the reset to be held down for some minimum time.  So I'd feel more
comfortable having a msleep(100) while the port is in reset.

Below is my current fix-up patch which make the board work again after
this patch.  Swapping 'assert' and 'deassert' is obviously just a hack -
some more proper solution is required.

Thanks,
NeilBrown


diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 9be5ca109a1b..6e32fbef9441 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -494,12 +494,16 @@ static int mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
 		return err;
 	}
 
-	reset_control_assert(port->pcie_rst);
 	reset_control_deassert(port->pcie_rst);
+	msleep(100);
+	reset_control_assert(port->pcie_rst);
+
+	val = read_config(pcie, slot, 0x70c);
+	dev_info(dev, "Port %d N_FTS = %x\n", (unsigned int)val, slot);
 
 	if ((pcie_port_read(port, RALINK_PCI_STATUS) & 0x1) == 0) {
 		dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n", slot);
-		reset_control_assert(port->pcie_rst);
+		reset_control_deassert(port->pcie_rst);
 		rt_sysc_m32(BIT(24 + slot), 0, RALINK_CLKCFG1);
 		pcie_link_status &= ~(1 << slot);
 	} else {
@@ -601,12 +605,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		bypass_pipe_rst(pcie);
 	set_phy_for_ssc(pcie);
 
-	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
-		u32 slot = port->slot;
-		val = read_config(pcie, slot, 0x70c);
-		dev_info(dev, "Port %d N_FTS = %x\n", (unsigned int)val, slot);
-	}
-
 	rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
 	rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
 

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Re: [PATCH v6 14/33] staging: mt7621-dts: add sysctl registers base address to pcie

[NeilBrown]

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On Sun, Nov 04 2018, Sergio Paracuellos wrote:

> Add missing system control registers address in pcie node of
> the device tree.
>
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---
>  drivers/staging/mt7621-dts/mt7621.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
> index 2e837e6..6b4bc43 100644
> --- a/drivers/staging/mt7621-dts/mt7621.dtsi
> +++ b/drivers/staging/mt7621-dts/mt7621.dtsi
> @@ -397,8 +397,8 @@
>  		reg = <0x1e140000 0x100     /* host-pci bridge registers */
>  			0x1e142000 0x100    /* pcie port 0 RC control registers */
>  			0x1e143000 0x100    /* pcie port 1 RC control registers */
> -			0x1e144000 0x100>;  /* pcie port 2 RC control registers */
> -
> +			0x1e144000 0x100    /* pcie port 2 RC control registers */
> +			0x1e000000 0x100>;  /* sysctl */

This is no good.  The sysctl register are already claimed by palmbus, so
pci fails to claim it.
The best way to access the sysc registers is to use
 rt_sysc_[rwm]32().

Below is my current fix-up patch to deal with this.

Thanks,
NeilBrown


diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index 6b4bc43d8eb6..e1000690bef2 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -398,7 +398,7 @@
 			0x1e142000 0x100    /* pcie port 0 RC control registers */
 			0x1e143000 0x100    /* pcie port 1 RC control registers */
 			0x1e144000 0x100    /* pcie port 2 RC control registers */
-			0x1e000000 0x100>;  /* sysctl */
+			>;
 		#address-cells = <3>;
 		#size-cells = <2>;
 
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index aa9baa776923..be4680f9b43a 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -172,7 +172,6 @@ struct mt7621_pcie_port {
 /**
  * struct mt7621_pcie - PCIe host information
  * @base: IO Mapped Register Base
- * @sysctl: system control mapped register base
  * @io: IO resource
  * @mem: non-prefetchable memory resource
  * @busn: bus range
@@ -182,7 +181,6 @@ struct mt7621_pcie_port {
  */
 struct mt7621_pcie {
 	void __iomem *base;
-	void __iomem *sysctl;
 	struct device *dev;
 	struct resource io;
 	struct resource mem;
@@ -397,8 +395,7 @@ set_phy_for_ssc(struct mt7621_pcie_port *port)
 
 static void mt7621_enable_phy(struct mt7621_pcie_port *port)
 {
-	struct mt7621_pcie *pcie = port->pcie;
-	u32 chip_rev_id = ioread32(pcie->sysctl + MT7621_CHIP_REV_ID);
+	u32 chip_rev_id = rt_sysc_r32(MT7621_CHIP_REV_ID);
 
 	if ((chip_rev_id & 0xFFFF) == CHIP_REV_MT7621_E2)
 		bypass_pipe_rst(port);
@@ -534,16 +531,6 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
 	if (IS_ERR(pcie->base))
 		return PTR_ERR(pcie->base);
 
-	err = of_address_to_resource(node, 4, &regs);
-	if (err) {
-		dev_err(dev, "missing \"reg\" property\n");
-		return err;
-	}
-
-	pcie->sysctl = devm_ioremap_resource(dev, &regs);
-	if (IS_ERR(pcie->sysctl))
-		return PTR_ERR(pcie->sysctl);
-
 	for_each_available_child_of_node(node, child) {
 		int slot;
 
@@ -637,11 +624,9 @@ static int mt7621_pcie_register_host(struct pci_host_bridge *host,
 
 static void mt7621_set_gpio_mode(struct mt7621_pcie *pcie)
 {
-	u32 reg = ioread32(pcie->sysctl + MT7621_GPIO_MODE);
-
-	reg &= ~(0x3 << 10 | 0x3 << 3);
-	reg |= (BIT(10) | BIT(3));
-	iowrite32(reg, pcie->sysctl + MT7621_GPIO_MODE);
+	rt_sysc_m32(0x3 << 10 | 0x3 << 3,
+		    BIT(10) | BIT(3),
+		    MT7621_GPIO_MODE);
 	mdelay(100);
 }
 

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Re: [PATCH v6 00/33] staging: mt7621-pci: Parse ports info from DT and other minor cleanups

[NeilBrown]

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On Mon, Nov 12 2018, Sergio Paracuellos wrote:

> On Mon, Nov 12, 2018 at 08:40:10AM +1100, NeilBrown wrote:
>> On Sun, Nov 11 2018, Greg KH wrote:
>> 
>> > On Sun, Nov 04, 2018 at 11:49:26AM +0100, Sergio Paracuellos wrote:
>> >> This patch series parse remaining port info from device tree storing
>> >> it in mt7621_pcie_port struct created for this. It also performs a lot
>> >> of cleanups to get the driver in a good shape to give it a try to get
>> >> mainlined. All of this changes are only compile-tested.
>> >
>> > Given the lack of responses here, I guess I'll just merge this and see
>> > what happens :)
>> 
>> Sounds like a good plan.
>> I had meant to look at it this past weekend, but ran out of time.
>> It is a bit awkward for me to test on mainline at the moment as
>> 
>> # first bad commit: [f8c55dc6e828324fc58c0bb32d72a5a4041d1c3b] MIPS: use generic dma noncoherent ops for simple noncoherent platforms
>> 
>> breaks mmc on my hardware, and my root filesystem is on mmc.
>> 
>> But I should still be able to get it tested sometime in the next couple
>> of weeks, and will provide feedback once I have it.
>
> Thanks, Neil. Please, let me know if I can help in any way.

I've got all the way to the end of the series and with the fixes that
I've already posted, my device still works.
There are lots of nice clean-ups in there - thanks!  I didn't review
them very closely as I was mostly focused on testing but what I saw
generally looked nice.

For the clock issue, I would just make a missing driver non-fatal.
clk_enable() is a no-op on ralink-mips, and I'm not sure that
clk_prepare does much either.

Handling the reset issue is a bit harder.
It seems that most bits in the reset register are
 1=assert  0=deassert
but that on some chips, the three PCI reset lines are inverted.
It would be easiest to put a quirk in  arch/mips/ralink/reset.c 
to check the CHIP_REV for the three lines and invert.

It might be cleaner to add some information to devicetree, but I cannot
easily find any precedent for that.

BTW, rather than calling
	reset_control_deassert(port->pcie_rst);
	reset_control_assert(port->pcie_rst);

maybe we should
	reset_control_reset(port->pcie_rst);
and not worry about a delay.

Are you OK to submit patches to address the various issues that I found?

Thanks a lot,
NeilBrown

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Re: [PATCH v6 14/33] staging: mt7621-dts: add sysctl registers base address to pcie

[Sergio Paracuellos]

On Sat, Nov 24, 2018 at 12:07 AM NeilBrown <neil@brown.name> wrote:
>
> On Sun, Nov 04 2018, Sergio Paracuellos wrote:
>
> > Add missing system control registers address in pcie node of
> > the device tree.
> >
> > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> > ---
> >  drivers/staging/mt7621-dts/mt7621.dtsi | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
> > index 2e837e6..6b4bc43 100644
> > --- a/drivers/staging/mt7621-dts/mt7621.dtsi
> > +++ b/drivers/staging/mt7621-dts/mt7621.dtsi
> > @@ -397,8 +397,8 @@
> >               reg = <0x1e140000 0x100     /* host-pci bridge registers */
> >                       0x1e142000 0x100    /* pcie port 0 RC control registers */
> >                       0x1e143000 0x100    /* pcie port 1 RC control registers */
> > -                     0x1e144000 0x100>;  /* pcie port 2 RC control registers */
> > -
> > +                     0x1e144000 0x100    /* pcie port 2 RC control registers */
> > +                     0x1e000000 0x100>;  /* sysctl */
>
> This is no good.  The sysctl register are already claimed by palmbus, so
> pci fails to claim it.
> The best way to access the sysc registers is to use
>  rt_sysc_[rwm]32().
>
> Below is my current fix-up patch to deal with this.
>
> Thanks,
> NeilBrown

Yes, It has more sense now. I was wondering the real need to do this
mapping from pcie bindings
and the best way to access the sys control registers and I ended up
with that. I'll fix this up.

Thanks for testing, Neil.

Best regards,
    Sergio Paracuellos
>
>
> diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
> index 6b4bc43d8eb6..e1000690bef2 100644
> --- a/drivers/staging/mt7621-dts/mt7621.dtsi
> +++ b/drivers/staging/mt7621-dts/mt7621.dtsi
> @@ -398,7 +398,7 @@
>                         0x1e142000 0x100    /* pcie port 0 RC control registers */
>                         0x1e143000 0x100    /* pcie port 1 RC control registers */
>                         0x1e144000 0x100    /* pcie port 2 RC control registers */
> -                       0x1e000000 0x100>;  /* sysctl */
> +                       >;
>                 #address-cells = <3>;
>                 #size-cells = <2>;
>
> diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
> index aa9baa776923..be4680f9b43a 100644
> --- a/drivers/staging/mt7621-pci/pci-mt7621.c
> +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
> @@ -172,7 +172,6 @@ struct mt7621_pcie_port {
>  /**
>   * struct mt7621_pcie - PCIe host information
>   * @base: IO Mapped Register Base
> - * @sysctl: system control mapped register base
>   * @io: IO resource
>   * @mem: non-prefetchable memory resource
>   * @busn: bus range
> @@ -182,7 +181,6 @@ struct mt7621_pcie_port {
>   */
>  struct mt7621_pcie {
>         void __iomem *base;
> -       void __iomem *sysctl;
>         struct device *dev;
>         struct resource io;
>         struct resource mem;
> @@ -397,8 +395,7 @@ set_phy_for_ssc(struct mt7621_pcie_port *port)
>
>  static void mt7621_enable_phy(struct mt7621_pcie_port *port)
>  {
> -       struct mt7621_pcie *pcie = port->pcie;
> -       u32 chip_rev_id = ioread32(pcie->sysctl + MT7621_CHIP_REV_ID);
> +       u32 chip_rev_id = rt_sysc_r32(MT7621_CHIP_REV_ID);
>
>         if ((chip_rev_id & 0xFFFF) == CHIP_REV_MT7621_E2)
>                 bypass_pipe_rst(port);
> @@ -534,16 +531,6 @@ static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
>         if (IS_ERR(pcie->base))
>                 return PTR_ERR(pcie->base);
>
> -       err = of_address_to_resource(node, 4, &regs);
> -       if (err) {
> -               dev_err(dev, "missing \"reg\" property\n");
> -               return err;
> -       }
> -
> -       pcie->sysctl = devm_ioremap_resource(dev, &regs);
> -       if (IS_ERR(pcie->sysctl))
> -               return PTR_ERR(pcie->sysctl);
> -
>         for_each_available_child_of_node(node, child) {
>                 int slot;
>
> @@ -637,11 +624,9 @@ static int mt7621_pcie_register_host(struct pci_host_bridge *host,
>
>  static void mt7621_set_gpio_mode(struct mt7621_pcie *pcie)
>  {
> -       u32 reg = ioread32(pcie->sysctl + MT7621_GPIO_MODE);
> -
> -       reg &= ~(0x3 << 10 | 0x3 << 3);
> -       reg |= (BIT(10) | BIT(3));
> -       iowrite32(reg, pcie->sysctl + MT7621_GPIO_MODE);
> +       rt_sysc_m32(0x3 << 10 | 0x3 << 3,
> +                   BIT(10) | BIT(3),
> +                   MT7621_GPIO_MODE);
>         mdelay(100);
>  }
>
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Re: [PATCH v6 00/33] staging: mt7621-pci: Parse ports info from DT and other minor cleanups

[Sergio Paracuellos]

On Sat, Nov 24, 2018 at 1:21 AM NeilBrown <neil@brown.name> wrote:
>
> On Mon, Nov 12 2018, Sergio Paracuellos wrote:
>
> > On Mon, Nov 12, 2018 at 08:40:10AM +1100, NeilBrown wrote:
> >> On Sun, Nov 11 2018, Greg KH wrote:
> >>
> >> > On Sun, Nov 04, 2018 at 11:49:26AM +0100, Sergio Paracuellos wrote:
> >> >> This patch series parse remaining port info from device tree storing
> >> >> it in mt7621_pcie_port struct created for this. It also performs a lot
> >> >> of cleanups to get the driver in a good shape to give it a try to get
> >> >> mainlined. All of this changes are only compile-tested.
> >> >
> >> > Given the lack of responses here, I guess I'll just merge this and see
> >> > what happens :)
> >>
> >> Sounds like a good plan.
> >> I had meant to look at it this past weekend, but ran out of time.
> >> It is a bit awkward for me to test on mainline at the moment as
> >>
> >> # first bad commit: [f8c55dc6e828324fc58c0bb32d72a5a4041d1c3b] MIPS: use generic dma noncoherent ops for simple noncoherent platforms
> >>
> >> breaks mmc on my hardware, and my root filesystem is on mmc.
> >>
> >> But I should still be able to get it tested sometime in the next couple
> >> of weeks, and will provide feedback once I have it.
> >
> > Thanks, Neil. Please, let me know if I can help in any way.
>
> I've got all the way to the end of the series and with the fixes that
> I've already posted, my device still works.
> There are lots of nice clean-ups in there - thanks!  I didn't review
> them very closely as I was mostly focused on testing but what I saw
> generally looked nice.

Thanks for your effort in reviewing and testing this series. There
were a bit long
and with lots of changes and cleanups.

>
> For the clock issue, I would just make a missing driver non-fatal.
> clk_enable() is a no-op on ralink-mips, and I'm not sure that
> clk_prepare does much either.

Do you mean just remove clocks from bindings and its clk_* references in
code?

>
> Handling the reset issue is a bit harder.
> It seems that most bits in the reset register are
>  1=assert  0=deassert
> but that on some chips, the three PCI reset lines are inverted.
> It would be easiest to put a quirk in  arch/mips/ralink/reset.c
> to check the CHIP_REV for the three lines and invert.

I'll see how to achieve this issue. Is it ok to submit the patch to staging
if I add a quirk in the mainlined reset.c file? Include linux-mips
mail list in the
CC is enough?

>
> It might be cleaner to add some information to devicetree, but I cannot
> easily find any precedent for that.
>
> BTW, rather than calling
>         reset_control_deassert(port->pcie_rst);
>         reset_control_assert(port->pcie_rst);
>
> maybe we should
>         reset_control_reset(port->pcie_rst);
> and not worry about a delay.

I'll also check this.

>
> Are you OK to submit patches to address the various issues that I found?

I'll do my best to try to fix this up.

>
> Thanks a lot,
> NeilBrown

Best regards,
    Sergio Paracuellos
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