From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138]) by ash.osuosl.org (Postfix) with ESMTP id 4DF7B1C0F07 for ; Sun, 4 Nov 2018 10:50:27 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id 446DA8713E for ; Sun, 4 Nov 2018 10:50:27 +0000 (UTC) Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id W1hWKptblKgm for ; Sun, 4 Nov 2018 10:50:26 +0000 (UTC) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by whitealder.osuosl.org (Postfix) with ESMTPS id 7D82487156 for ; Sun, 4 Nov 2018 10:50:26 +0000 (UTC) Received: by mail-wr1-f67.google.com with SMTP id d10-v6so6304096wrs.5 for ; Sun, 04 Nov 2018 02:50:26 -0800 (PST) From: Sergio Paracuellos Subject: [PATCH v6 27/33] staging: mt7621-pci: add some definitions for enabling and disabling GEN and GEN1 clocks Date: Sun, 4 Nov 2018 11:49:53 +0100 Message-Id: <1541328599-18396-28-git-send-email-sergio.paracuellos@gmail.com> In-Reply-To: <1541328599-18396-1-git-send-email-sergio.paracuellos@gmail.com> References: <1541328599-18396-1-git-send-email-sergio.paracuellos@gmail.com> List-Id: Linux Driver Project Developer List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: driverdev-devel-bounces@linuxdriverproject.org Sender: "devel" To: gregkh@linuxfoundation.org Cc: neil@brown.name, driverdev-devel@linuxdriverproject.org Instead of use hardcoded values when calling 'rt_sysc_m32' for enabling and disabling RALINK_PCIE_CLK_GEN and RALINK_PCIE_CLK_GEN1 create some preprocessor definitions. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-pci/pci-mt7621.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index 0e898a4..0c78cc2 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -87,6 +87,10 @@ #define PCIE_PORT_INT_EN(x) BIT(20 + (x)) #define PCIE_PORT_CLK_EN(x) BIT(24 + (x)) +#define PCIE_CLK_GEN_EN BIT(31) +#define PCIE_CLK_GEN_DIS 0 +#define PCIE_CLK_GEN1_DIS GENMASK(30,24) +#define PCIE_CLK_GEN1_EN (BIT(27) | BIT(25)) #define RALINK_PCI_IO_MAP_BASE 0x1e160000 #define MEMORY_BASE 0x0 @@ -815,9 +819,9 @@ static int mt7621_pci_probe(struct platform_device *pdev) rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL); rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1); - rt_sysc_m32(0x80000000, 0, RALINK_PCIE_CLK_GEN); - rt_sysc_m32(0x7f000000, 0xa << 24, RALINK_PCIE_CLK_GEN1); - rt_sysc_m32(0, 0x80000000, RALINK_PCIE_CLK_GEN); + rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN); + rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1); + rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN); mdelay(50); rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL); -- 2.7.4 _______________________________________________ devel mailing list devel@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel