From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73CA1C43441 for ; Mon, 26 Nov 2018 11:15:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4604320672 for ; Mon, 26 Nov 2018 11:15:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4604320672 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731017AbeKZWIs (ORCPT ); Mon, 26 Nov 2018 17:08:48 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:33244 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727952AbeKZWIr (ORCPT ); Mon, 26 Nov 2018 17:08:47 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 19806356D; Mon, 26 Nov 2018 03:15:00 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.11]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 629F53F5AF; Mon, 26 Nov 2018 03:14:55 -0800 (PST) From: Andrew Murray To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Shawn Guo , Sascha Hauer , Will Deacon , Mark Rutland , Benjamin Herrenschmidt , Thomas Gleixner , Borislav Petkov , x86@kernel.org, Ralf Baechle , Paul Burton , James Hogan , Martin Schwidefsky , Heiko Carstens , "David S . Miller" , sparclinux@vger.kernel.org, Michael Ellerman Cc: linux-s390@vger.kernel.org, linux-mips@linux-mips.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-alpha@vger.kernel.org Subject: [PATCH v2 19/20] x86: perf/core: advertise PMU exclusion capability Date: Mon, 26 Nov 2018 11:12:35 +0000 Message-Id: <1543230756-15319-20-git-send-email-andrew.murray@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1543230756-15319-1-git-send-email-andrew.murray@arm.com> References: <1543230756-15319-1-git-send-email-andrew.murray@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For PMUs that have the capability to exclude events based on context. Let's advertise that we support the PERF_PMU_CAP_EXCLUDE capability to ensure that perf doesn't prevent us from handling events where any exclusion flags are set. Signed-off-by: Andrew Murray --- arch/x86/events/core.c | 2 ++ arch/x86/events/intel/bts.c | 2 +- arch/x86/events/intel/pt.c | 4 +++- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index dfb2f7c..3f51916 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -2297,6 +2297,8 @@ static struct pmu pmu = { .event_idx = x86_pmu_event_idx, .sched_task = x86_pmu_sched_task, .task_ctx_size = sizeof(struct x86_perf_task_context), + + .capabilities = PERF_PMU_CAP_EXCLUDE, }; void arch_perf_update_userpage(struct perf_event *event, diff --git a/arch/x86/events/intel/bts.c b/arch/x86/events/intel/bts.c index 24ffa1e..4976695 100644 --- a/arch/x86/events/intel/bts.c +++ b/arch/x86/events/intel/bts.c @@ -601,7 +601,7 @@ static __init int bts_init(void) } bts_pmu.capabilities = PERF_PMU_CAP_AUX_NO_SG | PERF_PMU_CAP_ITRACE | - PERF_PMU_CAP_EXCLUSIVE; + PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_EXCLUDE; bts_pmu.task_ctx_nr = perf_sw_context; bts_pmu.event_init = bts_event_init; bts_pmu.add = bts_event_add; diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c index 8d016ce..2d811f8 100644 --- a/arch/x86/events/intel/pt.c +++ b/arch/x86/events/intel/pt.c @@ -1516,7 +1516,9 @@ static __init int pt_init(void) pt_pmu.pmu.capabilities = PERF_PMU_CAP_AUX_NO_SG | PERF_PMU_CAP_AUX_SW_DOUBLEBUF; - pt_pmu.pmu.capabilities |= PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE; + pt_pmu.pmu.capabilities = PERF_PMU_CAP_EXCLUSIVE | + PERF_PMU_CAP_ITRACE | + PERF_PMU_CAP_EXCLUDE; pt_pmu.pmu.attr_groups = pt_attr_groups; pt_pmu.pmu.task_ctx_nr = perf_sw_context; pt_pmu.pmu.event_init = pt_event_init; -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Murray Date: Mon, 26 Nov 2018 11:12:35 +0000 Subject: [PATCH v2 19/20] x86: perf/core: advertise PMU exclusion capability Message-Id: <1543230756-15319-20-git-send-email-andrew.murray@arm.com> List-Id: References: <1543230756-15319-1-git-send-email-andrew.murray@arm.com> In-Reply-To: <1543230756-15319-1-git-send-email-andrew.murray@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: linux-arm-kernel@lists.infradead.org For PMUs that have the capability to exclude events based on context. Let's advertise that we support the PERF_PMU_CAP_EXCLUDE capability to ensure that perf doesn't prevent us from handling events where any exclusion flags are set. Signed-off-by: Andrew Murray --- arch/x86/events/core.c | 2 ++ arch/x86/events/intel/bts.c | 2 +- arch/x86/events/intel/pt.c | 4 +++- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index dfb2f7c..3f51916 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -2297,6 +2297,8 @@ static struct pmu pmu = { .event_idx = x86_pmu_event_idx, .sched_task = x86_pmu_sched_task, .task_ctx_size = sizeof(struct x86_perf_task_context), + + .capabilities = PERF_PMU_CAP_EXCLUDE, }; void arch_perf_update_userpage(struct perf_event *event, diff --git a/arch/x86/events/intel/bts.c b/arch/x86/events/intel/bts.c index 24ffa1e..4976695 100644 --- a/arch/x86/events/intel/bts.c +++ b/arch/x86/events/intel/bts.c @@ -601,7 +601,7 @@ static __init int bts_init(void) } bts_pmu.capabilities = PERF_PMU_CAP_AUX_NO_SG | PERF_PMU_CAP_ITRACE | - PERF_PMU_CAP_EXCLUSIVE; + PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_EXCLUDE; bts_pmu.task_ctx_nr = perf_sw_context; bts_pmu.event_init = bts_event_init; bts_pmu.add = bts_event_add; diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c index 8d016ce..2d811f8 100644 --- a/arch/x86/events/intel/pt.c +++ b/arch/x86/events/intel/pt.c @@ -1516,7 +1516,9 @@ static __init int pt_init(void) pt_pmu.pmu.capabilities PERF_PMU_CAP_AUX_NO_SG | PERF_PMU_CAP_AUX_SW_DOUBLEBUF; - pt_pmu.pmu.capabilities |= PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE; + pt_pmu.pmu.capabilities = PERF_PMU_CAP_EXCLUSIVE | + PERF_PMU_CAP_ITRACE | + PERF_PMU_CAP_EXCLUDE; pt_pmu.pmu.attr_groups = pt_attr_groups; pt_pmu.pmu.task_ctx_nr = perf_sw_context; pt_pmu.pmu.event_init = pt_event_init; -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0E38C43441 for ; Mon, 26 Nov 2018 12:14:12 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4F77820817 for ; Mon, 26 Nov 2018 12:14:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4F77820817 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 433QnZ0D6gzDqVT for ; Mon, 26 Nov 2018 23:14:10 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=arm.com (client-ip=217.140.101.70; helo=foss.arm.com; envelope-from=andrew.murray@arm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by lists.ozlabs.org (Postfix) with ESMTP id 433PTK661BzDqQT for ; Mon, 26 Nov 2018 22:15:00 +1100 (AEDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 19806356D; Mon, 26 Nov 2018 03:15:00 -0800 (PST) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.11]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 629F53F5AF; Mon, 26 Nov 2018 03:14:55 -0800 (PST) From: Andrew Murray To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Shawn Guo , Sascha Hauer , Will Deacon , Mark Rutland , Benjamin Herrenschmidt , Thomas Gleixner , Borislav Petkov , x86@kernel.org, Ralf Baechle , Paul Burton , James Hogan , Martin Schwidefsky , Heiko Carstens , "David S . Miller" , sparclinux@vger.kernel.org, Michael Ellerman Subject: [PATCH v2 19/20] x86: perf/core: advertise PMU exclusion capability Date: Mon, 26 Nov 2018 11:12:35 +0000 Message-Id: <1543230756-15319-20-git-send-email-andrew.murray@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1543230756-15319-1-git-send-email-andrew.murray@arm.com> References: <1543230756-15319-1-git-send-email-andrew.murray@arm.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-s390@vger.kernel.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" For PMUs that have the capability to exclude events based on context. Let's advertise that we support the PERF_PMU_CAP_EXCLUDE capability to ensure that perf doesn't prevent us from handling events where any exclusion flags are set. Signed-off-by: Andrew Murray --- arch/x86/events/core.c | 2 ++ arch/x86/events/intel/bts.c | 2 +- arch/x86/events/intel/pt.c | 4 +++- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index dfb2f7c..3f51916 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -2297,6 +2297,8 @@ static struct pmu pmu = { .event_idx = x86_pmu_event_idx, .sched_task = x86_pmu_sched_task, .task_ctx_size = sizeof(struct x86_perf_task_context), + + .capabilities = PERF_PMU_CAP_EXCLUDE, }; void arch_perf_update_userpage(struct perf_event *event, diff --git a/arch/x86/events/intel/bts.c b/arch/x86/events/intel/bts.c index 24ffa1e..4976695 100644 --- a/arch/x86/events/intel/bts.c +++ b/arch/x86/events/intel/bts.c @@ -601,7 +601,7 @@ static __init int bts_init(void) } bts_pmu.capabilities = PERF_PMU_CAP_AUX_NO_SG | PERF_PMU_CAP_ITRACE | - PERF_PMU_CAP_EXCLUSIVE; + PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_EXCLUDE; bts_pmu.task_ctx_nr = perf_sw_context; bts_pmu.event_init = bts_event_init; bts_pmu.add = bts_event_add; diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c index 8d016ce..2d811f8 100644 --- a/arch/x86/events/intel/pt.c +++ b/arch/x86/events/intel/pt.c @@ -1516,7 +1516,9 @@ static __init int pt_init(void) pt_pmu.pmu.capabilities = PERF_PMU_CAP_AUX_NO_SG | PERF_PMU_CAP_AUX_SW_DOUBLEBUF; - pt_pmu.pmu.capabilities |= PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE; + pt_pmu.pmu.capabilities = PERF_PMU_CAP_EXCLUSIVE | + PERF_PMU_CAP_ITRACE | + PERF_PMU_CAP_EXCLUDE; pt_pmu.pmu.attr_groups = pt_attr_groups; pt_pmu.pmu.task_ctx_nr = perf_sw_context; pt_pmu.pmu.event_init = pt_event_init; -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: andrew.murray@arm.com (Andrew Murray) Date: Mon, 26 Nov 2018 11:12:35 +0000 Subject: [PATCH v2 19/20] x86: perf/core: advertise PMU exclusion capability In-Reply-To: <1543230756-15319-1-git-send-email-andrew.murray@arm.com> References: <1543230756-15319-1-git-send-email-andrew.murray@arm.com> Message-ID: <1543230756-15319-20-git-send-email-andrew.murray@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org For PMUs that have the capability to exclude events based on context. Let's advertise that we support the PERF_PMU_CAP_EXCLUDE capability to ensure that perf doesn't prevent us from handling events where any exclusion flags are set. Signed-off-by: Andrew Murray --- arch/x86/events/core.c | 2 ++ arch/x86/events/intel/bts.c | 2 +- arch/x86/events/intel/pt.c | 4 +++- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index dfb2f7c..3f51916 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -2297,6 +2297,8 @@ static struct pmu pmu = { .event_idx = x86_pmu_event_idx, .sched_task = x86_pmu_sched_task, .task_ctx_size = sizeof(struct x86_perf_task_context), + + .capabilities = PERF_PMU_CAP_EXCLUDE, }; void arch_perf_update_userpage(struct perf_event *event, diff --git a/arch/x86/events/intel/bts.c b/arch/x86/events/intel/bts.c index 24ffa1e..4976695 100644 --- a/arch/x86/events/intel/bts.c +++ b/arch/x86/events/intel/bts.c @@ -601,7 +601,7 @@ static __init int bts_init(void) } bts_pmu.capabilities = PERF_PMU_CAP_AUX_NO_SG | PERF_PMU_CAP_ITRACE | - PERF_PMU_CAP_EXCLUSIVE; + PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_EXCLUDE; bts_pmu.task_ctx_nr = perf_sw_context; bts_pmu.event_init = bts_event_init; bts_pmu.add = bts_event_add; diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c index 8d016ce..2d811f8 100644 --- a/arch/x86/events/intel/pt.c +++ b/arch/x86/events/intel/pt.c @@ -1516,7 +1516,9 @@ static __init int pt_init(void) pt_pmu.pmu.capabilities = PERF_PMU_CAP_AUX_NO_SG | PERF_PMU_CAP_AUX_SW_DOUBLEBUF; - pt_pmu.pmu.capabilities |= PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE; + pt_pmu.pmu.capabilities = PERF_PMU_CAP_EXCLUSIVE | + PERF_PMU_CAP_ITRACE | + PERF_PMU_CAP_EXCLUDE; pt_pmu.pmu.attr_groups = pt_attr_groups; pt_pmu.pmu.task_ctx_nr = perf_sw_context; pt_pmu.pmu.event_init = pt_event_init; -- 2.7.4