* [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC
@ 2018-11-30 22:58 clinton.a.taylor
2018-11-30 23:08 ` ✗ Fi.CI.BAT: failure for " Patchwork
` (13 more replies)
0 siblings, 14 replies; 26+ messages in thread
From: clinton.a.taylor @ 2018-11-30 22:58 UTC (permalink / raw)
To: Intel-gfx; +Cc: Rodrigo Vivi
From: Clint Taylor <clinton.a.taylor@intel.com>
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence.
BSpec: 21257
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 +
drivers/gpu/drm/i915/intel_ddi.c | 223 +++++++++++++----------------------
drivers/gpu/drm/i915/intel_display.c | 3 -
3 files changed, 86 insertions(+), 144 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d3ef979..e632e99 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1866,6 +1866,10 @@ enum i915_power_well_id {
#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
+#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
+#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
+#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
+#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
#define N_SCALAR(x) ((x) << 24)
#define N_SCALAR_MASK (0x7F << 24)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 61d7145..219464e9 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -493,103 +493,63 @@ struct cnl_ddi_buf_trans {
{ 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
};
-struct icl_combo_phy_ddi_buf_trans {
- u32 dw2_swing_select;
- u32 dw2_swing_scalar;
- u32 dw4_scaling;
-};
-
-/* Voltage Swing Programming for VccIO 0.85V for DP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
- /* Voltage mV db */
- { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
- { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
- { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
- { 0x2, 0x98, 0x900F }, /* 400 9.5 */
- { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
- { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
- { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
- { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
- { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
- { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
-};
-
-/* FIXME - After table is updated in Bspec */
-/* Voltage Swing Programming for VccIO 0.85V for eDP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
- /* Voltage mV db */
- { 0x0, 0x00, 0x00 }, /* 200 0.0 */
- { 0x0, 0x00, 0x00 }, /* 200 1.5 */
- { 0x0, 0x00, 0x00 }, /* 200 4.0 */
- { 0x0, 0x00, 0x00 }, /* 200 6.0 */
- { 0x0, 0x00, 0x00 }, /* 250 0.0 */
- { 0x0, 0x00, 0x00 }, /* 250 1.5 */
- { 0x0, 0x00, 0x00 }, /* 250 4.0 */
- { 0x0, 0x00, 0x00 }, /* 300 0.0 */
- { 0x0, 0x00, 0x00 }, /* 300 1.5 */
- { 0x0, 0x00, 0x00 }, /* 350 0.0 */
+/* icl_combo_phy_ddi_translations */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
+ { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
+ { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
+ { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 705 0.6 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
};
-/* Voltage Swing Programming for VccIO 0.95V for DP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
- /* Voltage mV db */
- { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
- { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
- { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
- { 0x2, 0x98, 0x900F }, /* 400 9.5 */
- { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
- { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
- { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
- { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
- { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
- { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_lowswing[] = {
+ /* NT mV Trans mV db */
+ { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
+ { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
+ { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
+ { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
+ { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
+ { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
+ { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
+ { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
+ { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
+ { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
};
-/* FIXME - After table is updated in Bspec */
-/* Voltage Swing Programming for VccIO 0.95V for eDP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
- /* Voltage mV db */
- { 0x0, 0x00, 0x00 }, /* 200 0.0 */
- { 0x0, 0x00, 0x00 }, /* 200 1.5 */
- { 0x0, 0x00, 0x00 }, /* 200 4.0 */
- { 0x0, 0x00, 0x00 }, /* 200 6.0 */
- { 0x0, 0x00, 0x00 }, /* 250 0.0 */
- { 0x0, 0x00, 0x00 }, /* 250 1.5 */
- { 0x0, 0x00, 0x00 }, /* 250 4.0 */
- { 0x0, 0x00, 0x00 }, /* 300 0.0 */
- { 0x0, 0x00, 0x00 }, /* 300 1.5 */
- { 0x0, 0x00, 0x00 }, /* 350 0.0 */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
+ { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
+ { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
+ { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
};
-/* Voltage Swing Programming for VccIO 1.05V for DP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
- /* Voltage mV db */
- { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
- { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
- { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
- { 0x2, 0x98, 0x900F }, /* 400 9.5 */
- { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
- { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
- { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
- { 0x5, 0x71, 0x0018 }, /* 800 0.0 */
- { 0x5, 0x71, 0x3015 }, /* 800 3.5 */
- { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
+ { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
+ { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
+ { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
+ { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
};
-/* FIXME - After table is updated in Bspec */
-/* Voltage Swing Programming for VccIO 1.05V for eDP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
- /* Voltage mV db */
- { 0x0, 0x00, 0x00 }, /* 200 0.0 */
- { 0x0, 0x00, 0x00 }, /* 200 1.5 */
- { 0x0, 0x00, 0x00 }, /* 200 4.0 */
- { 0x0, 0x00, 0x00 }, /* 200 6.0 */
- { 0x0, 0x00, 0x00 }, /* 250 0.0 */
- { 0x0, 0x00, 0x00 }, /* 250 1.5 */
- { 0x0, 0x00, 0x00 }, /* 250 4.0 */
- { 0x0, 0x00, 0x00 }, /* 300 0.0 */
- { 0x0, 0x00, 0x00 }, /* 300 1.5 */
- { 0x0, 0x00, 0x00 }, /* 350 0.0 */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_mipi[] = {
+ /* NT mV Trans mV db */
+ { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
};
struct icl_mg_phy_ddi_buf_trans {
@@ -870,43 +830,27 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries)
}
}
-static const struct icl_combo_phy_ddi_buf_trans *
+static const struct cnl_ddi_buf_trans *
icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
int type, int *n_entries)
{
- u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
- switch (voltage) {
- case VOLTAGE_INFO_0_85V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
- return icl_combo_phy_ddi_translations_edp_0_85V;
- case VOLTAGE_INFO_0_95V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
- return icl_combo_phy_ddi_translations_edp_0_95V;
- case VOLTAGE_INFO_1_05V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
- return icl_combo_phy_ddi_translations_edp_1_05V;
- default:
- MISSING_CASE(voltage);
- return NULL;
- }
- } else {
- switch (voltage) {
- case VOLTAGE_INFO_0_85V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
- return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
- case VOLTAGE_INFO_0_95V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
- return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
- case VOLTAGE_INFO_1_05V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
- return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
- default:
- MISSING_CASE(voltage);
- return NULL;
- }
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_lowswing);
+ return icl_combo_phy_ddi_translations_edp_lowswing;
+ } else if (type == INTEL_OUTPUT_EDP) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
+ return icl_combo_phy_ddi_translations_edp_hbr3;
+ } else if ((type == INTEL_OUTPUT_DP) || (type == INTEL_OUTPUT_DDI) ||
+ (type == INTEL_OUTPUT_DP_MST)) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp);
+ return icl_combo_phy_ddi_translations_dp;
+ } else if (type == INTEL_OUTPUT_HDMI) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+ return icl_combo_phy_ddi_translations_hdmi;
}
+
+ return NULL;
}
static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
@@ -2463,7 +2407,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
u32 level, enum port port, int type)
{
- const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
+ const struct cnl_ddi_buf_trans *ddi_translations = NULL;
u32 n_entries, val;
int ln;
@@ -2477,34 +2421,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
level = n_entries - 1;
}
- /* Set PORT_TX_DW5 Rterm Sel to 110b. */
+ /* Set PORT_TX_DW5 */
val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
- val &= ~RTERM_SELECT_MASK;
+ val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
+ TAP2_DISABLE | TAP3_DISABLE);
+ val |= SCALING_MODE_SEL(0x2);
val |= RTERM_SELECT(0x6);
- I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
-
- /* Program PORT_TX_DW5 */
- val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
- /* Set DisableTap2 and DisableTap3 if MIPI DSI
- * Clear DisableTap2 and DisableTap3 for all other Ports
- */
- if (type == INTEL_OUTPUT_DSI) {
- val |= TAP2_DISABLE;
- val |= TAP3_DISABLE;
- } else {
- val &= ~TAP2_DISABLE;
- val &= ~TAP3_DISABLE;
- }
+ val |= TAP3_DISABLE;
I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
/* Program PORT_TX_DW2 */
val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
RCOMP_SCALAR_MASK);
- val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
- val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
+ val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
+ val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
/* Program Rcomp scalar for every table entry */
- val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
+ val |= RCOMP_SCALAR(0x98);
I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
/* Program PORT_TX_DW4 */
@@ -2513,9 +2446,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
CURSOR_COEFF_MASK);
- val |= ddi_translations[level].dw4_scaling;
+ val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
+ val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
+ val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
}
+
+ /* Program PORT_TX_DW7 */
+ val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
+ val &= ~N_SCALAR_MASK;
+ val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
+ I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
}
static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 789f647bd..6c125ae 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15435,9 +15435,6 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
/* notify opregion of the sanitized encoder state */
intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
-
- if (INTEL_GEN(dev_priv) >= 11)
- icl_sanitize_encoder_pll_mapping(encoder);
}
void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/icl: combo port vswing programming changes per BSPEC
2018-11-30 22:58 [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC clinton.a.taylor
@ 2018-11-30 23:08 ` Patchwork
2018-11-30 23:15 ` [PATCH] " Imre Deak
` (12 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2018-11-30 23:08 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: combo port vswing programming changes per BSPEC
URL : https://patchwork.freedesktop.org/series/53340/
State : failure
== Summary ==
CALL scripts/checksyscalls.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/intel_display.o
drivers/gpu/drm/i915/intel_display.c: In function ‘intel_sanitize_encoder’:
drivers/gpu/drm/i915/intel_display.c:15396:27: error: unused variable ‘dev_priv’ [-Werror=unused-variable]
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
^~~~~~~~
cc1: all warnings being treated as errors
scripts/Makefile.build:293: recipe for target 'drivers/gpu/drm/i915/intel_display.o' failed
make[4]: *** [drivers/gpu/drm/i915/intel_display.o] Error 1
scripts/Makefile.build:518: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:518: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:518: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1060: recipe for target 'drivers' failed
make: *** [drivers] Error 2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC
2018-11-30 22:58 [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC clinton.a.taylor
2018-11-30 23:08 ` ✗ Fi.CI.BAT: failure for " Patchwork
@ 2018-11-30 23:15 ` Imre Deak
2018-11-30 23:22 ` Clint Taylor
2018-11-30 23:46 ` [PATCH v2] " clinton.a.taylor
` (11 subsequent siblings)
13 siblings, 1 reply; 26+ messages in thread
From: Imre Deak @ 2018-11-30 23:15 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: Intel-gfx, Rodrigo Vivi
On Fri, Nov 30, 2018 at 02:58:01PM -0800, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> In August 2018 the BSPEC changed the ICL port programming sequence to
> closely resemble earlier gen programming sequence.
>
> BSpec: 21257
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 +
> drivers/gpu/drm/i915/intel_ddi.c | 223 +++++++++++++----------------------
> drivers/gpu/drm/i915/intel_display.c | 3 -
> 3 files changed, 86 insertions(+), 144 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d3ef979..e632e99 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1866,6 +1866,10 @@ enum i915_power_well_id {
>
> #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
> #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
> +#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
> +#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
> +#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
> +#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
> #define N_SCALAR(x) ((x) << 24)
> #define N_SCALAR_MASK (0x7F << 24)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 61d7145..219464e9 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -493,103 +493,63 @@ struct cnl_ddi_buf_trans {
> { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
> };
>
> -struct icl_combo_phy_ddi_buf_trans {
> - u32 dw2_swing_select;
> - u32 dw2_swing_scalar;
> - u32 dw4_scaling;
> -};
> -
> -/* Voltage Swing Programming for VccIO 0.85V for DP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
> - /* Voltage mV db */
> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> - { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
> - { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
> - { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
> - { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
> - { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> -};
> -
> -/* FIXME - After table is updated in Bspec */
> -/* Voltage Swing Programming for VccIO 0.85V for eDP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
> - /* Voltage mV db */
> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> +/* icl_combo_phy_ddi_translations */
> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp[] = {
> + /* NT mV Trans mV db */
> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 705 0.6 */
> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> };
>
> -/* Voltage Swing Programming for VccIO 0.95V for DP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
> - /* Voltage mV db */
> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
> - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
> - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
> - { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
> - { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_lowswing[] = {
> + /* NT mV Trans mV db */
> + { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
> + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
> + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
> + { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
> + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
> + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
> + { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
> + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
> + { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
> + { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> };
>
> -/* FIXME - After table is updated in Bspec */
> -/* Voltage Swing Programming for VccIO 0.95V for eDP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
> - /* Voltage mV db */
> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
> + /* NT mV Trans mV db */
> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> };
>
> -/* Voltage Swing Programming for VccIO 1.05V for DP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
> - /* Voltage mV db */
> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
> - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
> - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
> - { 0x5, 0x71, 0x0018 }, /* 800 0.0 */
> - { 0x5, 0x71, 0x3015 }, /* 800 3.5 */
> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
> + /* NT mV Trans mV db */
> + { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
> + { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
> + { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
> + { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
> + { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
> };
>
> -/* FIXME - After table is updated in Bspec */
> -/* Voltage Swing Programming for VccIO 1.05V for eDP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
> - /* Voltage mV db */
> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_mipi[] = {
> + /* NT mV Trans mV db */
> + { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
> };
>
> struct icl_mg_phy_ddi_buf_trans {
> @@ -870,43 +830,27 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries)
> }
> }
>
> -static const struct icl_combo_phy_ddi_buf_trans *
> +static const struct cnl_ddi_buf_trans *
> icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
> int type, int *n_entries)
> {
> - u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
>
> if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
> - switch (voltage) {
> - case VOLTAGE_INFO_0_85V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
> - return icl_combo_phy_ddi_translations_edp_0_85V;
> - case VOLTAGE_INFO_0_95V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
> - return icl_combo_phy_ddi_translations_edp_0_95V;
> - case VOLTAGE_INFO_1_05V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
> - return icl_combo_phy_ddi_translations_edp_1_05V;
> - default:
> - MISSING_CASE(voltage);
> - return NULL;
> - }
> - } else {
> - switch (voltage) {
> - case VOLTAGE_INFO_0_85V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
> - return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
> - case VOLTAGE_INFO_0_95V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
> - return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
> - case VOLTAGE_INFO_1_05V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
> - return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
> - default:
> - MISSING_CASE(voltage);
> - return NULL;
> - }
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_lowswing);
> + return icl_combo_phy_ddi_translations_edp_lowswing;
> + } else if (type == INTEL_OUTPUT_EDP) {
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> + return icl_combo_phy_ddi_translations_edp_hbr3;
> + } else if ((type == INTEL_OUTPUT_DP) || (type == INTEL_OUTPUT_DDI) ||
> + (type == INTEL_OUTPUT_DP_MST)) {
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp);
> + return icl_combo_phy_ddi_translations_dp;
> + } else if (type == INTEL_OUTPUT_HDMI) {
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> + return icl_combo_phy_ddi_translations_hdmi;
> }
> +
> + return NULL;
> }
>
> static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
> @@ -2463,7 +2407,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
> static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> u32 level, enum port port, int type)
> {
> - const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
> + const struct cnl_ddi_buf_trans *ddi_translations = NULL;
> u32 n_entries, val;
> int ln;
>
> @@ -2477,34 +2421,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> level = n_entries - 1;
> }
>
> - /* Set PORT_TX_DW5 Rterm Sel to 110b. */
> + /* Set PORT_TX_DW5 */
> val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> - val &= ~RTERM_SELECT_MASK;
> + val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
> + TAP2_DISABLE | TAP3_DISABLE);
> + val |= SCALING_MODE_SEL(0x2);
> val |= RTERM_SELECT(0x6);
> - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
> -
> - /* Program PORT_TX_DW5 */
> - val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> - /* Set DisableTap2 and DisableTap3 if MIPI DSI
> - * Clear DisableTap2 and DisableTap3 for all other Ports
> - */
> - if (type == INTEL_OUTPUT_DSI) {
> - val |= TAP2_DISABLE;
> - val |= TAP3_DISABLE;
> - } else {
> - val &= ~TAP2_DISABLE;
> - val &= ~TAP3_DISABLE;
> - }
> + val |= TAP3_DISABLE;
> I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
>
> /* Program PORT_TX_DW2 */
> val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> RCOMP_SCALAR_MASK);
> - val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
> - val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
> + val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
> + val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
> /* Program Rcomp scalar for every table entry */
> - val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
> + val |= RCOMP_SCALAR(0x98);
> I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
>
> /* Program PORT_TX_DW4 */
> @@ -2513,9 +2446,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
> val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> CURSOR_COEFF_MASK);
> - val |= ddi_translations[level].dw4_scaling;
> + val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
> + val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
> + val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
> I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
> }
> +
> + /* Program PORT_TX_DW7 */
> + val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
> + val &= ~N_SCALAR_MASK;
> + val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
> + I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
> }
>
> static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 789f647bd..6c125ae 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15435,9 +15435,6 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
>
> /* notify opregion of the sanitized encoder state */
> intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
> -
> - if (INTEL_GEN(dev_priv) >= 11)
> - icl_sanitize_encoder_pll_mapping(encoder);
This looks unrelated/not explained in the commit message. The port
clocking programming looks still the same, so I don't understand why we
wouldn't need the above.
> }
>
> void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
> --
> 1.9.1
>
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^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC
2018-11-30 23:15 ` [PATCH] " Imre Deak
@ 2018-11-30 23:22 ` Clint Taylor
0 siblings, 0 replies; 26+ messages in thread
From: Clint Taylor @ 2018-11-30 23:22 UTC (permalink / raw)
To: imre.deak; +Cc: Intel-gfx, Rodrigo Vivi
On 11/30/2018 03:15 PM, Imre Deak wrote:
> On Fri, Nov 30, 2018 at 02:58:01PM -0800, clinton.a.taylor@intel.com wrote:
>> From: Clint Taylor <clinton.a.taylor@intel.com>
>>
>> In August 2018 the BSPEC changed the ICL port programming sequence to
>> closely resemble earlier gen programming sequence.
>>
>> BSpec: 21257
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 4 +
>> drivers/gpu/drm/i915/intel_ddi.c | 223 +++++++++++++----------------------
>> drivers/gpu/drm/i915/intel_display.c | 3 -
>> 3 files changed, 86 insertions(+), 144 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index d3ef979..e632e99 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -1866,6 +1866,10 @@ enum i915_power_well_id {
>>
>> #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
>> #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
>> +#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
>> +#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
>> +#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
>> +#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
>> #define N_SCALAR(x) ((x) << 24)
>> #define N_SCALAR_MASK (0x7F << 24)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index 61d7145..219464e9 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -493,103 +493,63 @@ struct cnl_ddi_buf_trans {
>> { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
>> };
>>
>> -struct icl_combo_phy_ddi_buf_trans {
>> - u32 dw2_swing_select;
>> - u32 dw2_swing_scalar;
>> - u32 dw4_scaling;
>> -};
>> -
>> -/* Voltage Swing Programming for VccIO 0.85V for DP */
>> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
>> - /* Voltage mV db */
>> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
>> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
>> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
>> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
>> - { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
>> - { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
>> - { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
>> - { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
>> - { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
>> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
>> -};
>> -
>> -/* FIXME - After table is updated in Bspec */
>> -/* Voltage Swing Programming for VccIO 0.85V for eDP */
>> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
>> - /* Voltage mV db */
>> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
>> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
>> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
>> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
>> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
>> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
>> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
>> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
>> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
>> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
>> +/* icl_combo_phy_ddi_translations */
>> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp[] = {
>> + /* NT mV Trans mV db */
>> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
>> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
>> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
>> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
>> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
>> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
>> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
>> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 705 0.6 */
>> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
>> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
>> };
>>
>> -/* Voltage Swing Programming for VccIO 0.95V for DP */
>> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
>> - /* Voltage mV db */
>> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
>> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
>> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
>> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
>> - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
>> - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
>> - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
>> - { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
>> - { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
>> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
>> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_lowswing[] = {
>> + /* NT mV Trans mV db */
>> + { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
>> + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
>> + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
>> + { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
>> + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
>> + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
>> + { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
>> + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
>> + { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
>> + { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
>> };
>>
>> -/* FIXME - After table is updated in Bspec */
>> -/* Voltage Swing Programming for VccIO 0.95V for eDP */
>> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
>> - /* Voltage mV db */
>> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
>> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
>> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
>> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
>> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
>> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
>> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
>> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
>> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
>> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
>> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
>> + /* NT mV Trans mV db */
>> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
>> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
>> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
>> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
>> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
>> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
>> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
>> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
>> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
>> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
>> };
>>
>> -/* Voltage Swing Programming for VccIO 1.05V for DP */
>> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
>> - /* Voltage mV db */
>> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
>> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
>> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
>> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
>> - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
>> - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
>> - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
>> - { 0x5, 0x71, 0x0018 }, /* 800 0.0 */
>> - { 0x5, 0x71, 0x3015 }, /* 800 3.5 */
>> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
>> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
>> + /* NT mV Trans mV db */
>> + { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
>> + { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
>> + { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
>> + { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
>> + { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
>> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
>> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
>> };
>>
>> -/* FIXME - After table is updated in Bspec */
>> -/* Voltage Swing Programming for VccIO 1.05V for eDP */
>> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
>> - /* Voltage mV db */
>> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
>> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
>> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
>> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
>> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
>> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
>> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
>> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
>> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
>> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
>> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_mipi[] = {
>> + /* NT mV Trans mV db */
>> + { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
>> };
>>
>> struct icl_mg_phy_ddi_buf_trans {
>> @@ -870,43 +830,27 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries)
>> }
>> }
>>
>> -static const struct icl_combo_phy_ddi_buf_trans *
>> +static const struct cnl_ddi_buf_trans *
>> icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
>> int type, int *n_entries)
>> {
>> - u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
>>
>> if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
>> - switch (voltage) {
>> - case VOLTAGE_INFO_0_85V:
>> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
>> - return icl_combo_phy_ddi_translations_edp_0_85V;
>> - case VOLTAGE_INFO_0_95V:
>> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
>> - return icl_combo_phy_ddi_translations_edp_0_95V;
>> - case VOLTAGE_INFO_1_05V:
>> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
>> - return icl_combo_phy_ddi_translations_edp_1_05V;
>> - default:
>> - MISSING_CASE(voltage);
>> - return NULL;
>> - }
>> - } else {
>> - switch (voltage) {
>> - case VOLTAGE_INFO_0_85V:
>> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
>> - return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
>> - case VOLTAGE_INFO_0_95V:
>> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
>> - return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
>> - case VOLTAGE_INFO_1_05V:
>> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
>> - return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
>> - default:
>> - MISSING_CASE(voltage);
>> - return NULL;
>> - }
>> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_lowswing);
>> + return icl_combo_phy_ddi_translations_edp_lowswing;
>> + } else if (type == INTEL_OUTPUT_EDP) {
>> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
>> + return icl_combo_phy_ddi_translations_edp_hbr3;
>> + } else if ((type == INTEL_OUTPUT_DP) || (type == INTEL_OUTPUT_DDI) ||
>> + (type == INTEL_OUTPUT_DP_MST)) {
>> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp);
>> + return icl_combo_phy_ddi_translations_dp;
>> + } else if (type == INTEL_OUTPUT_HDMI) {
>> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
>> + return icl_combo_phy_ddi_translations_hdmi;
>> }
>> +
>> + return NULL;
>> }
>>
>> static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
>> @@ -2463,7 +2407,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
>> static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
>> u32 level, enum port port, int type)
>> {
>> - const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
>> + const struct cnl_ddi_buf_trans *ddi_translations = NULL;
>> u32 n_entries, val;
>> int ln;
>>
>> @@ -2477,34 +2421,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
>> level = n_entries - 1;
>> }
>>
>> - /* Set PORT_TX_DW5 Rterm Sel to 110b. */
>> + /* Set PORT_TX_DW5 */
>> val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>> - val &= ~RTERM_SELECT_MASK;
>> + val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
>> + TAP2_DISABLE | TAP3_DISABLE);
>> + val |= SCALING_MODE_SEL(0x2);
>> val |= RTERM_SELECT(0x6);
>> - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
>> -
>> - /* Program PORT_TX_DW5 */
>> - val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>> - /* Set DisableTap2 and DisableTap3 if MIPI DSI
>> - * Clear DisableTap2 and DisableTap3 for all other Ports
>> - */
>> - if (type == INTEL_OUTPUT_DSI) {
>> - val |= TAP2_DISABLE;
>> - val |= TAP3_DISABLE;
>> - } else {
>> - val &= ~TAP2_DISABLE;
>> - val &= ~TAP3_DISABLE;
>> - }
>> + val |= TAP3_DISABLE;
>> I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
>>
>> /* Program PORT_TX_DW2 */
>> val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
>> val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
>> RCOMP_SCALAR_MASK);
>> - val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
>> - val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
>> + val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
>> + val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
>> /* Program Rcomp scalar for every table entry */
>> - val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
>> + val |= RCOMP_SCALAR(0x98);
>> I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
>>
>> /* Program PORT_TX_DW4 */
>> @@ -2513,9 +2446,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
>> val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
>> val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
>> CURSOR_COEFF_MASK);
>> - val |= ddi_translations[level].dw4_scaling;
>> + val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
>> + val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
>> + val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
>> I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
>> }
>> +
>> + /* Program PORT_TX_DW7 */
>> + val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
>> + val &= ~N_SCALAR_MASK;
>> + val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
>> + I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
>> }
>>
>> static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 789f647bd..6c125ae 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -15435,9 +15435,6 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
>>
>> /* notify opregion of the sanitized encoder state */
>> intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
>> -
>> - if (INTEL_GEN(dev_priv) >= 11)
>> - icl_sanitize_encoder_pll_mapping(encoder);
> This looks unrelated/not explained in the commit message. The port
> clocking programming looks still the same, so I don't understand why we
> wouldn't need the above.
Oops, forgot to remove this debug code.
-Clint
>> }
>>
>> void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
>> --
>> 1.9.1
>>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v2] drm/i915/icl: combo port vswing programming changes per BSPEC
2018-11-30 22:58 [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC clinton.a.taylor
2018-11-30 23:08 ` ✗ Fi.CI.BAT: failure for " Patchwork
2018-11-30 23:15 ` [PATCH] " Imre Deak
@ 2018-11-30 23:46 ` clinton.a.taylor
2018-12-01 0:33 ` ✓ Fi.CI.BAT: success for drm/i915/icl: combo port vswing programming changes per BSPEC (rev2) Patchwork
` (10 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: clinton.a.taylor @ 2018-11-30 23:46 UTC (permalink / raw)
To: Intel-gfx; +Cc: Rodrigo Vivi
From: Clint Taylor <clinton.a.taylor@intel.com>
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence.
v2: remove debug code that Imre found
BSpec: 21257
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 +
drivers/gpu/drm/i915/intel_ddi.c | 223 ++++++++++++++-------------------------
2 files changed, 86 insertions(+), 141 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d3ef979..e632e99 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1866,6 +1866,10 @@ enum i915_power_well_id {
#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
+#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
+#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
+#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
+#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
#define N_SCALAR(x) ((x) << 24)
#define N_SCALAR_MASK (0x7F << 24)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 61d7145..219464e9 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -493,103 +493,63 @@ struct cnl_ddi_buf_trans {
{ 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
};
-struct icl_combo_phy_ddi_buf_trans {
- u32 dw2_swing_select;
- u32 dw2_swing_scalar;
- u32 dw4_scaling;
-};
-
-/* Voltage Swing Programming for VccIO 0.85V for DP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
- /* Voltage mV db */
- { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
- { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
- { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
- { 0x2, 0x98, 0x900F }, /* 400 9.5 */
- { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
- { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
- { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
- { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
- { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
- { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
-};
-
-/* FIXME - After table is updated in Bspec */
-/* Voltage Swing Programming for VccIO 0.85V for eDP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
- /* Voltage mV db */
- { 0x0, 0x00, 0x00 }, /* 200 0.0 */
- { 0x0, 0x00, 0x00 }, /* 200 1.5 */
- { 0x0, 0x00, 0x00 }, /* 200 4.0 */
- { 0x0, 0x00, 0x00 }, /* 200 6.0 */
- { 0x0, 0x00, 0x00 }, /* 250 0.0 */
- { 0x0, 0x00, 0x00 }, /* 250 1.5 */
- { 0x0, 0x00, 0x00 }, /* 250 4.0 */
- { 0x0, 0x00, 0x00 }, /* 300 0.0 */
- { 0x0, 0x00, 0x00 }, /* 300 1.5 */
- { 0x0, 0x00, 0x00 }, /* 350 0.0 */
+/* icl_combo_phy_ddi_translations */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
+ { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
+ { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
+ { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 705 0.6 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
};
-/* Voltage Swing Programming for VccIO 0.95V for DP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
- /* Voltage mV db */
- { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
- { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
- { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
- { 0x2, 0x98, 0x900F }, /* 400 9.5 */
- { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
- { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
- { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
- { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
- { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
- { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_lowswing[] = {
+ /* NT mV Trans mV db */
+ { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
+ { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
+ { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
+ { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
+ { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
+ { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
+ { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
+ { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
+ { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
+ { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
};
-/* FIXME - After table is updated in Bspec */
-/* Voltage Swing Programming for VccIO 0.95V for eDP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
- /* Voltage mV db */
- { 0x0, 0x00, 0x00 }, /* 200 0.0 */
- { 0x0, 0x00, 0x00 }, /* 200 1.5 */
- { 0x0, 0x00, 0x00 }, /* 200 4.0 */
- { 0x0, 0x00, 0x00 }, /* 200 6.0 */
- { 0x0, 0x00, 0x00 }, /* 250 0.0 */
- { 0x0, 0x00, 0x00 }, /* 250 1.5 */
- { 0x0, 0x00, 0x00 }, /* 250 4.0 */
- { 0x0, 0x00, 0x00 }, /* 300 0.0 */
- { 0x0, 0x00, 0x00 }, /* 300 1.5 */
- { 0x0, 0x00, 0x00 }, /* 350 0.0 */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
+ { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
+ { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
+ { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
};
-/* Voltage Swing Programming for VccIO 1.05V for DP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
- /* Voltage mV db */
- { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
- { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
- { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
- { 0x2, 0x98, 0x900F }, /* 400 9.5 */
- { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
- { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
- { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
- { 0x5, 0x71, 0x0018 }, /* 800 0.0 */
- { 0x5, 0x71, 0x3015 }, /* 800 3.5 */
- { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
+ { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
+ { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
+ { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
+ { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
};
-/* FIXME - After table is updated in Bspec */
-/* Voltage Swing Programming for VccIO 1.05V for eDP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
- /* Voltage mV db */
- { 0x0, 0x00, 0x00 }, /* 200 0.0 */
- { 0x0, 0x00, 0x00 }, /* 200 1.5 */
- { 0x0, 0x00, 0x00 }, /* 200 4.0 */
- { 0x0, 0x00, 0x00 }, /* 200 6.0 */
- { 0x0, 0x00, 0x00 }, /* 250 0.0 */
- { 0x0, 0x00, 0x00 }, /* 250 1.5 */
- { 0x0, 0x00, 0x00 }, /* 250 4.0 */
- { 0x0, 0x00, 0x00 }, /* 300 0.0 */
- { 0x0, 0x00, 0x00 }, /* 300 1.5 */
- { 0x0, 0x00, 0x00 }, /* 350 0.0 */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_mipi[] = {
+ /* NT mV Trans mV db */
+ { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
};
struct icl_mg_phy_ddi_buf_trans {
@@ -870,43 +830,27 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries)
}
}
-static const struct icl_combo_phy_ddi_buf_trans *
+static const struct cnl_ddi_buf_trans *
icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
int type, int *n_entries)
{
- u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
- switch (voltage) {
- case VOLTAGE_INFO_0_85V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
- return icl_combo_phy_ddi_translations_edp_0_85V;
- case VOLTAGE_INFO_0_95V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
- return icl_combo_phy_ddi_translations_edp_0_95V;
- case VOLTAGE_INFO_1_05V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
- return icl_combo_phy_ddi_translations_edp_1_05V;
- default:
- MISSING_CASE(voltage);
- return NULL;
- }
- } else {
- switch (voltage) {
- case VOLTAGE_INFO_0_85V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
- return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
- case VOLTAGE_INFO_0_95V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
- return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
- case VOLTAGE_INFO_1_05V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
- return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
- default:
- MISSING_CASE(voltage);
- return NULL;
- }
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_lowswing);
+ return icl_combo_phy_ddi_translations_edp_lowswing;
+ } else if (type == INTEL_OUTPUT_EDP) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
+ return icl_combo_phy_ddi_translations_edp_hbr3;
+ } else if ((type == INTEL_OUTPUT_DP) || (type == INTEL_OUTPUT_DDI) ||
+ (type == INTEL_OUTPUT_DP_MST)) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp);
+ return icl_combo_phy_ddi_translations_dp;
+ } else if (type == INTEL_OUTPUT_HDMI) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+ return icl_combo_phy_ddi_translations_hdmi;
}
+
+ return NULL;
}
static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
@@ -2463,7 +2407,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
u32 level, enum port port, int type)
{
- const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
+ const struct cnl_ddi_buf_trans *ddi_translations = NULL;
u32 n_entries, val;
int ln;
@@ -2477,34 +2421,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
level = n_entries - 1;
}
- /* Set PORT_TX_DW5 Rterm Sel to 110b. */
+ /* Set PORT_TX_DW5 */
val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
- val &= ~RTERM_SELECT_MASK;
+ val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
+ TAP2_DISABLE | TAP3_DISABLE);
+ val |= SCALING_MODE_SEL(0x2);
val |= RTERM_SELECT(0x6);
- I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
-
- /* Program PORT_TX_DW5 */
- val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
- /* Set DisableTap2 and DisableTap3 if MIPI DSI
- * Clear DisableTap2 and DisableTap3 for all other Ports
- */
- if (type == INTEL_OUTPUT_DSI) {
- val |= TAP2_DISABLE;
- val |= TAP3_DISABLE;
- } else {
- val &= ~TAP2_DISABLE;
- val &= ~TAP3_DISABLE;
- }
+ val |= TAP3_DISABLE;
I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
/* Program PORT_TX_DW2 */
val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
RCOMP_SCALAR_MASK);
- val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
- val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
+ val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
+ val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
/* Program Rcomp scalar for every table entry */
- val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
+ val |= RCOMP_SCALAR(0x98);
I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
/* Program PORT_TX_DW4 */
@@ -2513,9 +2446,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
CURSOR_COEFF_MASK);
- val |= ddi_translations[level].dw4_scaling;
+ val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
+ val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
+ val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
}
+
+ /* Program PORT_TX_DW7 */
+ val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
+ val &= ~N_SCALAR_MASK;
+ val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
+ I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
}
static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/icl: combo port vswing programming changes per BSPEC (rev2)
2018-11-30 22:58 [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC clinton.a.taylor
` (2 preceding siblings ...)
2018-11-30 23:46 ` [PATCH v2] " clinton.a.taylor
@ 2018-12-01 0:33 ` Patchwork
2018-12-01 20:09 ` ✗ Fi.CI.IGT: failure " Patchwork
` (9 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2018-12-01 0:33 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: combo port vswing programming changes per BSPEC (rev2)
URL : https://patchwork.freedesktop.org/series/53340/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5237 -> Patchwork_10987
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/53340/revisions/2/mbox/
Known issues
------------
Here are the changes found in Patchwork_10987 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: PASS -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] +1
#### Possible fixes ####
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
Participating hosts (49 -> 43)
------------------------------
Missing (6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600
Build changes
-------------
* Linux: CI_DRM_5237 -> Patchwork_10987
CI_DRM_5237: 2f99c4889e4124f9cf50b745d037f432318c4bb4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4736: 285ebfb3b7adc56586031afa5150c4e5ad40c229 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10987: 3e2cd1bcd69757f7e348f3d008213e1f2f7ff2f6 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3e2cd1bcd697 drm/i915/icl: combo port vswing programming changes per BSPEC
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10987/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915/icl: combo port vswing programming changes per BSPEC (rev2)
2018-11-30 22:58 [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC clinton.a.taylor
` (3 preceding siblings ...)
2018-12-01 0:33 ` ✓ Fi.CI.BAT: success for drm/i915/icl: combo port vswing programming changes per BSPEC (rev2) Patchwork
@ 2018-12-01 20:09 ` Patchwork
2018-12-03 12:19 ` [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC Ville Syrjälä
` (8 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2018-12-01 20:09 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: combo port vswing programming changes per BSPEC (rev2)
URL : https://patchwork.freedesktop.org/series/53340/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5237_full -> Patchwork_10987_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_10987_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10987_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_10987_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_crc@cursor-128x128-offscreen:
- shard-kbl: PASS -> FAIL
Known issues
------------
Here are the changes found in Patchwork_10987_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_schedule@pi-ringfull-bsd:
- shard-skl: NOTRUN -> FAIL [fdo#103158]
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-skl: PASS -> TIMEOUT [fdo#108039]
* igt@i915_suspend@shrink:
- shard-hsw: NOTRUN -> DMESG-WARN [fdo#108784]
- {shard-iclb}: NOTRUN -> DMESG-WARN [fdo#108784]
* igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-kbl: PASS -> DMESG-WARN [fdo#103313] / [fdo#103558] / [fdo#105602]
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-snb: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_cursor_crc@cursor-128x128-offscreen:
- shard-skl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x21-sliding:
- {shard-iclb}: NOTRUN -> FAIL [fdo#103232] +2
* igt@kms_cursor_crc@cursor-size-change:
- shard-glk: PASS -> FAIL [fdo#103232] +2
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled:
- shard-skl: PASS -> FAIL [fdo#103184]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
- shard-glk: PASS -> FAIL [fdo#103167] +2
- {shard-iclb}: NOTRUN -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-skl: NOTRUN -> FAIL [fdo#105683]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
- {shard-iclb}: PASS -> FAIL [fdo#103167] +4
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] +1
* igt@kms_plane@pixel-format-pipe-a-planes:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885]
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- {shard-iclb}: PASS -> INCOMPLETE [fdo#107713]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
- {shard-iclb}: PASS -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
- shard-apl: PASS -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- {shard-iclb}: NOTRUN -> FAIL [fdo#103166]
* igt@kms_setmode@basic:
- shard-apl: PASS -> FAIL [fdo#99912]
* igt@kms_universal_plane@cursor-fb-leak-pipe-b:
- shard-kbl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +14
* igt@pm_rpm@sysfs-read:
- shard-skl: PASS -> INCOMPLETE [fdo#107807] +1
* igt@pm_rpm@system-suspend-modeset:
- {shard-iclb}: PASS -> INCOMPLETE [fdo#107713] / [fdo#108840]
#### Possible fixes ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-snb: DMESG-WARN [fdo#102365] -> PASS
* igt@kms_busy@extended-pageflip-hang-newfb-render-a:
- shard-apl: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-glk: FAIL [fdo#103167] -> PASS +3
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff:
- {shard-iclb}: FAIL [fdo#103167] -> PASS +2
* igt@kms_plane@plane-position-covered-pipe-c-planes:
- shard-glk: FAIL [fdo#103166] -> PASS +1
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: FAIL [fdo#107815] / [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: FAIL [fdo#107815] -> PASS
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-apl: FAIL [fdo#103166] -> PASS +2
* igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
- {shard-iclb}: FAIL [fdo#103166] -> PASS +1
* igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
- {shard-iclb}: DMESG-WARN [fdo#107724] -> PASS
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- {shard-iclb}: INCOMPLETE [fdo#107713] -> PASS
* igt@pm_rpm@legacy-planes:
- {shard-iclb}: DMESG-WARN [fdo#108654] -> PASS
#### Warnings ####
* igt@i915_suspend@shrink:
- shard-snb: INCOMPLETE [fdo#105411] / [fdo#106886] -> DMESG-WARN [fdo#108784]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102365]: https://bugs.freedesktop.org/show_bug.cgi?id=102365
[fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#105683]: https://bugs.freedesktop.org/show_bug.cgi?id=105683
[fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
[fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108039]: https://bugs.freedesktop.org/show_bug.cgi?id=108039
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
[fdo#108784]: https://bugs.freedesktop.org/show_bug.cgi?id=108784
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_5237 -> Patchwork_10987
CI_DRM_5237: 2f99c4889e4124f9cf50b745d037f432318c4bb4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4736: 285ebfb3b7adc56586031afa5150c4e5ad40c229 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10987: 3e2cd1bcd69757f7e348f3d008213e1f2f7ff2f6 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10987/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC
2018-11-30 22:58 [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC clinton.a.taylor
` (4 preceding siblings ...)
2018-12-01 20:09 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2018-12-03 12:19 ` Ville Syrjälä
2018-12-03 19:34 ` Clint Taylor
2018-12-04 23:41 ` [PATCH v3] " clinton.a.taylor
` (7 subsequent siblings)
13 siblings, 1 reply; 26+ messages in thread
From: Ville Syrjälä @ 2018-12-03 12:19 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: Intel-gfx, Rodrigo Vivi
On Fri, Nov 30, 2018 at 02:58:01PM -0800, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> In August 2018 the BSPEC changed the ICL port programming sequence to
> closely resemble earlier gen programming sequence.
>
> BSpec: 21257
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 +
> drivers/gpu/drm/i915/intel_ddi.c | 223 +++++++++++++----------------------
> drivers/gpu/drm/i915/intel_display.c | 3 -
> 3 files changed, 86 insertions(+), 144 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d3ef979..e632e99 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1866,6 +1866,10 @@ enum i915_power_well_id {
>
> #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
> #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
> +#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
> +#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
> +#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
> +#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
> #define N_SCALAR(x) ((x) << 24)
> #define N_SCALAR_MASK (0x7F << 24)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 61d7145..219464e9 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -493,103 +493,63 @@ struct cnl_ddi_buf_trans {
> { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
> };
>
> -struct icl_combo_phy_ddi_buf_trans {
> - u32 dw2_swing_select;
> - u32 dw2_swing_scalar;
> - u32 dw4_scaling;
> -};
> -
> -/* Voltage Swing Programming for VccIO 0.85V for DP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
> - /* Voltage mV db */
> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> - { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
> - { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
> - { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
> - { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
> - { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> -};
> -
> -/* FIXME - After table is updated in Bspec */
> -/* Voltage Swing Programming for VccIO 0.85V for eDP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
> - /* Voltage mV db */
> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> +/* icl_combo_phy_ddi_translations */
> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp[] = {
> + /* NT mV Trans mV db */
> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 705 0.6 */
> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> };
>
> -/* Voltage Swing Programming for VccIO 0.95V for DP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
> - /* Voltage mV db */
> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
> - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
> - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
> - { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
> - { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_lowswing[] = {
> + /* NT mV Trans mV db */
> + { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
> + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
> + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
> + { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
> + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
> + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
> + { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
> + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
> + { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
> + { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> };
>
> -/* FIXME - After table is updated in Bspec */
> -/* Voltage Swing Programming for VccIO 0.95V for eDP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
> - /* Voltage mV db */
> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
> + /* NT mV Trans mV db */
> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> };
>
> -/* Voltage Swing Programming for VccIO 1.05V for DP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
> - /* Voltage mV db */
> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
> - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
> - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
> - { 0x5, 0x71, 0x0018 }, /* 800 0.0 */
> - { 0x5, 0x71, 0x3015 }, /* 800 3.5 */
> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
> + /* NT mV Trans mV db */
> + { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
> + { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
> + { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
> + { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
> + { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
> };
>
> -/* FIXME - After table is updated in Bspec */
> -/* Voltage Swing Programming for VccIO 1.05V for eDP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
> - /* Voltage mV db */
> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_mipi[] = {
> + /* NT mV Trans mV db */
> + { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
> };
>
> struct icl_mg_phy_ddi_buf_trans {
> @@ -870,43 +830,27 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries)
> }
> }
>
> -static const struct icl_combo_phy_ddi_buf_trans *
> +static const struct cnl_ddi_buf_trans *
> icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
> int type, int *n_entries)
> {
> - u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
>
> if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
> - switch (voltage) {
> - case VOLTAGE_INFO_0_85V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
> - return icl_combo_phy_ddi_translations_edp_0_85V;
> - case VOLTAGE_INFO_0_95V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
> - return icl_combo_phy_ddi_translations_edp_0_95V;
> - case VOLTAGE_INFO_1_05V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
> - return icl_combo_phy_ddi_translations_edp_1_05V;
> - default:
> - MISSING_CASE(voltage);
> - return NULL;
> - }
> - } else {
> - switch (voltage) {
> - case VOLTAGE_INFO_0_85V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
> - return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
> - case VOLTAGE_INFO_0_95V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
> - return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
> - case VOLTAGE_INFO_1_05V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
> - return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
> - default:
> - MISSING_CASE(voltage);
> - return NULL;
> - }
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_lowswing);
> + return icl_combo_phy_ddi_translations_edp_lowswing;
> + } else if (type == INTEL_OUTPUT_EDP) {
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> + return icl_combo_phy_ddi_translations_edp_hbr3;
> + } else if ((type == INTEL_OUTPUT_DP) || (type == INTEL_OUTPUT_DDI) ||
> + (type == INTEL_OUTPUT_DP_MST)) {
I would move the hdmi case first to match how most other platforms do
it, and to eliminate this complicated DP check.
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp);
> + return icl_combo_phy_ddi_translations_dp;
> + } else if (type == INTEL_OUTPUT_HDMI) {
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> + return icl_combo_phy_ddi_translations_hdmi;
> }
> +
> + return NULL;
> }
>
> static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
> @@ -2463,7 +2407,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
> static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> u32 level, enum port port, int type)
> {
> - const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
> + const struct cnl_ddi_buf_trans *ddi_translations = NULL;
> u32 n_entries, val;
> int ln;
>
> @@ -2477,34 +2421,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> level = n_entries - 1;
> }
>
> - /* Set PORT_TX_DW5 Rterm Sel to 110b. */
> + /* Set PORT_TX_DW5 */
> val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> - val &= ~RTERM_SELECT_MASK;
> + val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
> + TAP2_DISABLE | TAP3_DISABLE);
> + val |= SCALING_MODE_SEL(0x2);
> val |= RTERM_SELECT(0x6);
> - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
> -
> - /* Program PORT_TX_DW5 */
> - val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> - /* Set DisableTap2 and DisableTap3 if MIPI DSI
> - * Clear DisableTap2 and DisableTap3 for all other Ports
> - */
> - if (type == INTEL_OUTPUT_DSI) {
> - val |= TAP2_DISABLE;
> - val |= TAP3_DISABLE;
> - } else {
> - val &= ~TAP2_DISABLE;
> - val &= ~TAP3_DISABLE;
> - }
> + val |= TAP3_DISABLE;
> I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
>
> /* Program PORT_TX_DW2 */
> val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> RCOMP_SCALAR_MASK);
> - val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
> - val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
> + val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
> + val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
> /* Program Rcomp scalar for every table entry */
> - val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
> + val |= RCOMP_SCALAR(0x98);
> I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
>
> /* Program PORT_TX_DW4 */
> @@ -2513,9 +2446,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
> val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> CURSOR_COEFF_MASK);
> - val |= ddi_translations[level].dw4_scaling;
> + val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
> + val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
> + val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
> I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
> }
> +
> + /* Program PORT_TX_DW7 */
The comment is redundant.
> + val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
> + val &= ~N_SCALAR_MASK;
> + val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
> + I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
> }
>
> static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 789f647bd..6c125ae 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15435,9 +15435,6 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
>
> /* notify opregion of the sanitized encoder state */
> intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
> -
> - if (INTEL_GEN(dev_priv) >= 11)
> - icl_sanitize_encoder_pll_mapping(encoder);
> }
>
> void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
> --
> 1.9.1
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC
2018-12-03 12:19 ` [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC Ville Syrjälä
@ 2018-12-03 19:34 ` Clint Taylor
2018-12-03 19:53 ` Ville Syrjälä
0 siblings, 1 reply; 26+ messages in thread
From: Clint Taylor @ 2018-12-03 19:34 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Intel-gfx, Rodrigo Vivi
On 12/03/2018 04:19 AM, Ville Syrjälä wrote:
> On Fri, Nov 30, 2018 at 02:58:01PM -0800, clinton.a.taylor@intel.com wrote:
>> From: Clint Taylor <clinton.a.taylor@intel.com>
>>
>> In August 2018 the BSPEC changed the ICL port programming sequence to
>> closely resemble earlier gen programming sequence.
>>
>> BSpec: 21257
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 4 +
>> drivers/gpu/drm/i915/intel_ddi.c | 223 +++++++++++++----------------------
>> drivers/gpu/drm/i915/intel_display.c | 3 -
>> 3 files changed, 86 insertions(+), 144 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index d3ef979..e632e99 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -1866,6 +1866,10 @@ enum i915_power_well_id {
>>
>> #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
>> #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
>> +#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
>> +#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
>> +#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
>> +#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
>> #define N_SCALAR(x) ((x) << 24)
>> #define N_SCALAR_MASK (0x7F << 24)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index 61d7145..219464e9 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -493,103 +493,63 @@ struct cnl_ddi_buf_trans {
>> { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
>> };
>>
>> -struct icl_combo_phy_ddi_buf_trans {
>> - u32 dw2_swing_select;
>> - u32 dw2_swing_scalar;
>> - u32 dw4_scaling;
>> -};
>> -
>> -/* Voltage Swing Programming for VccIO 0.85V for DP */
>> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
>> - /* Voltage mV db */
>> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
>> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
>> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
>> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
>> - { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
>> - { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
>> - { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
>> - { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
>> - { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
>> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
>> -};
>> -
>> -/* FIXME - After table is updated in Bspec */
>> -/* Voltage Swing Programming for VccIO 0.85V for eDP */
>> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
>> - /* Voltage mV db */
>> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
>> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
>> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
>> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
>> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
>> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
>> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
>> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
>> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
>> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
>> +/* icl_combo_phy_ddi_translations */
>> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp[] = {
>> + /* NT mV Trans mV db */
>> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
>> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
>> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
>> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
>> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
>> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
>> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
>> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 705 0.6 */
>> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
>> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
>> };
>>
>> -/* Voltage Swing Programming for VccIO 0.95V for DP */
>> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
>> - /* Voltage mV db */
>> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
>> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
>> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
>> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
>> - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
>> - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
>> - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
>> - { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
>> - { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
>> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
>> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_lowswing[] = {
>> + /* NT mV Trans mV db */
>> + { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
>> + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
>> + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
>> + { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
>> + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
>> + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
>> + { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
>> + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
>> + { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
>> + { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
>> };
>>
>> -/* FIXME - After table is updated in Bspec */
>> -/* Voltage Swing Programming for VccIO 0.95V for eDP */
>> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
>> - /* Voltage mV db */
>> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
>> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
>> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
>> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
>> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
>> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
>> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
>> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
>> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
>> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
>> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
>> + /* NT mV Trans mV db */
>> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
>> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
>> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
>> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
>> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
>> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
>> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
>> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
>> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
>> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
>> };
>>
>> -/* Voltage Swing Programming for VccIO 1.05V for DP */
>> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
>> - /* Voltage mV db */
>> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
>> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
>> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
>> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
>> - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
>> - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
>> - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
>> - { 0x5, 0x71, 0x0018 }, /* 800 0.0 */
>> - { 0x5, 0x71, 0x3015 }, /* 800 3.5 */
>> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
>> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
>> + /* NT mV Trans mV db */
>> + { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
>> + { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
>> + { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
>> + { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
>> + { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
>> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
>> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
>> };
>>
>> -/* FIXME - After table is updated in Bspec */
>> -/* Voltage Swing Programming for VccIO 1.05V for eDP */
>> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
>> - /* Voltage mV db */
>> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
>> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
>> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
>> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
>> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
>> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
>> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
>> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
>> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
>> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
>> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_mipi[] = {
>> + /* NT mV Trans mV db */
>> + { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
>> };
>>
>> struct icl_mg_phy_ddi_buf_trans {
>> @@ -870,43 +830,27 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries)
>> }
>> }
>>
>> -static const struct icl_combo_phy_ddi_buf_trans *
>> +static const struct cnl_ddi_buf_trans *
>> icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
>> int type, int *n_entries)
>> {
>> - u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
>>
>> if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
>> - switch (voltage) {
>> - case VOLTAGE_INFO_0_85V:
>> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
>> - return icl_combo_phy_ddi_translations_edp_0_85V;
>> - case VOLTAGE_INFO_0_95V:
>> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
>> - return icl_combo_phy_ddi_translations_edp_0_95V;
>> - case VOLTAGE_INFO_1_05V:
>> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
>> - return icl_combo_phy_ddi_translations_edp_1_05V;
>> - default:
>> - MISSING_CASE(voltage);
>> - return NULL;
>> - }
>> - } else {
>> - switch (voltage) {
>> - case VOLTAGE_INFO_0_85V:
>> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
>> - return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
>> - case VOLTAGE_INFO_0_95V:
>> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
>> - return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
>> - case VOLTAGE_INFO_1_05V:
>> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
>> - return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
>> - default:
>> - MISSING_CASE(voltage);
>> - return NULL;
>> - }
>> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_lowswing);
>> + return icl_combo_phy_ddi_translations_edp_lowswing;
>> + } else if (type == INTEL_OUTPUT_EDP) {
>> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
>> + return icl_combo_phy_ddi_translations_edp_hbr3;
>> + } else if ((type == INTEL_OUTPUT_DP) || (type == INTEL_OUTPUT_DDI) ||
>> + (type == INTEL_OUTPUT_DP_MST)) {
> I would move the hdmi case first to match how most other platforms do
> it, and to eliminate this complicated DP check.
Agreed.
>
>> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp);
>> + return icl_combo_phy_ddi_translations_dp;
>> + } else if (type == INTEL_OUTPUT_HDMI) {
>> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
>> + return icl_combo_phy_ddi_translations_hdmi;
>> }
>> +
>> + return NULL;
>> }
>>
>> static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
>> @@ -2463,7 +2407,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
>> static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
>> u32 level, enum port port, int type)
>> {
>> - const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
>> + const struct cnl_ddi_buf_trans *ddi_translations = NULL;
>> u32 n_entries, val;
>> int ln;
>>
>> @@ -2477,34 +2421,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
>> level = n_entries - 1;
>> }
>>
>> - /* Set PORT_TX_DW5 Rterm Sel to 110b. */
>> + /* Set PORT_TX_DW5 */
>> val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>> - val &= ~RTERM_SELECT_MASK;
>> + val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
>> + TAP2_DISABLE | TAP3_DISABLE);
>> + val |= SCALING_MODE_SEL(0x2);
>> val |= RTERM_SELECT(0x6);
>> - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
>> -
>> - /* Program PORT_TX_DW5 */
>> - val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>> - /* Set DisableTap2 and DisableTap3 if MIPI DSI
>> - * Clear DisableTap2 and DisableTap3 for all other Ports
>> - */
>> - if (type == INTEL_OUTPUT_DSI) {
>> - val |= TAP2_DISABLE;
>> - val |= TAP3_DISABLE;
>> - } else {
>> - val &= ~TAP2_DISABLE;
>> - val &= ~TAP3_DISABLE;
>> - }
>> + val |= TAP3_DISABLE;
>> I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
>>
>> /* Program PORT_TX_DW2 */
>> val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
>> val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
>> RCOMP_SCALAR_MASK);
>> - val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
>> - val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
>> + val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
>> + val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
>> /* Program Rcomp scalar for every table entry */
>> - val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
>> + val |= RCOMP_SCALAR(0x98);
>> I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
>>
>> /* Program PORT_TX_DW4 */
>> @@ -2513,9 +2446,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
>> val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
>> val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
>> CURSOR_COEFF_MASK);
>> - val |= ddi_translations[level].dw4_scaling;
>> + val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
>> + val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
>> + val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
>> I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
>> }
>> +
>> + /* Program PORT_TX_DW7 */
> The comment is redundant.
It's consistent with the other comments in the function. The CNL
function also has the exact same comment. Are you sure you want me to
remove this comment?
-Clint
>
>> + val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
>> + val &= ~N_SCALAR_MASK;
>> + val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
>> + I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
>> }
>>
>> static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 789f647bd..6c125ae 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -15435,9 +15435,6 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
>>
>> /* notify opregion of the sanitized encoder state */
>> intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
>> -
>> - if (INTEL_GEN(dev_priv) >= 11)
>> - icl_sanitize_encoder_pll_mapping(encoder);
>> }
>>
>> void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
>> --
>> 1.9.1
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* Re: [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC
2018-12-03 19:34 ` Clint Taylor
@ 2018-12-03 19:53 ` Ville Syrjälä
0 siblings, 0 replies; 26+ messages in thread
From: Ville Syrjälä @ 2018-12-03 19:53 UTC (permalink / raw)
To: Clint Taylor; +Cc: Intel-gfx, Rodrigo Vivi
On Mon, Dec 03, 2018 at 11:34:16AM -0800, Clint Taylor wrote:
>
>
> On 12/03/2018 04:19 AM, Ville Syrjälä wrote:
> > On Fri, Nov 30, 2018 at 02:58:01PM -0800, clinton.a.taylor@intel.com wrote:
> >> From: Clint Taylor <clinton.a.taylor@intel.com>
> >>
> >> In August 2018 the BSPEC changed the ICL port programming sequence to
> >> closely resemble earlier gen programming sequence.
> >>
> >> BSpec: 21257
> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> Cc: Imre Deak <imre.deak@intel.com>
> >> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/i915_reg.h | 4 +
> >> drivers/gpu/drm/i915/intel_ddi.c | 223 +++++++++++++----------------------
> >> drivers/gpu/drm/i915/intel_display.c | 3 -
> >> 3 files changed, 86 insertions(+), 144 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index d3ef979..e632e99 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -1866,6 +1866,10 @@ enum i915_power_well_id {
> >>
> >> #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
> >> #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
> >> +#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
> >> +#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
> >> +#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
> >> +#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
> >> #define N_SCALAR(x) ((x) << 24)
> >> #define N_SCALAR_MASK (0x7F << 24)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> >> index 61d7145..219464e9 100644
> >> --- a/drivers/gpu/drm/i915/intel_ddi.c
> >> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> >> @@ -493,103 +493,63 @@ struct cnl_ddi_buf_trans {
> >> { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
> >> };
> >>
> >> -struct icl_combo_phy_ddi_buf_trans {
> >> - u32 dw2_swing_select;
> >> - u32 dw2_swing_scalar;
> >> - u32 dw4_scaling;
> >> -};
> >> -
> >> -/* Voltage Swing Programming for VccIO 0.85V for DP */
> >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
> >> - /* Voltage mV db */
> >> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> >> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> >> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> >> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> >> - { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
> >> - { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
> >> - { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
> >> - { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
> >> - { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
> >> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> >> -};
> >> -
> >> -/* FIXME - After table is updated in Bspec */
> >> -/* Voltage Swing Programming for VccIO 0.85V for eDP */
> >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
> >> - /* Voltage mV db */
> >> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> >> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> >> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> >> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> >> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> >> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> >> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> >> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> >> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> >> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> >> +/* icl_combo_phy_ddi_translations */
> >> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp[] = {
> >> + /* NT mV Trans mV db */
> >> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> >> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
> >> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> >> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
> >> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> >> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
> >> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
> >> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 705 0.6 */
> >> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> >> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> >> };
> >>
> >> -/* Voltage Swing Programming for VccIO 0.95V for DP */
> >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
> >> - /* Voltage mV db */
> >> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> >> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> >> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> >> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> >> - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
> >> - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
> >> - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
> >> - { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
> >> - { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
> >> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> >> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_lowswing[] = {
> >> + /* NT mV Trans mV db */
> >> + { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
> >> + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
> >> + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
> >> + { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
> >> + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
> >> + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
> >> + { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
> >> + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
> >> + { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
> >> + { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> >> };
> >>
> >> -/* FIXME - After table is updated in Bspec */
> >> -/* Voltage Swing Programming for VccIO 0.95V for eDP */
> >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
> >> - /* Voltage mV db */
> >> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> >> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> >> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> >> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> >> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> >> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> >> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> >> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> >> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> >> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> >> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
> >> + /* NT mV Trans mV db */
> >> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> >> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
> >> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> >> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
> >> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> >> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
> >> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
> >> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
> >> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> >> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> >> };
> >>
> >> -/* Voltage Swing Programming for VccIO 1.05V for DP */
> >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
> >> - /* Voltage mV db */
> >> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> >> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> >> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> >> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> >> - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
> >> - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
> >> - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
> >> - { 0x5, 0x71, 0x0018 }, /* 800 0.0 */
> >> - { 0x5, 0x71, 0x3015 }, /* 800 3.5 */
> >> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> >> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
> >> + /* NT mV Trans mV db */
> >> + { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
> >> + { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
> >> + { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
> >> + { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
> >> + { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
> >> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
> >> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
> >> };
> >>
> >> -/* FIXME - After table is updated in Bspec */
> >> -/* Voltage Swing Programming for VccIO 1.05V for eDP */
> >> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
> >> - /* Voltage mV db */
> >> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> >> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> >> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> >> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> >> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> >> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> >> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> >> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> >> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> >> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> >> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_mipi[] = {
> >> + /* NT mV Trans mV db */
> >> + { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
> >> };
> >>
> >> struct icl_mg_phy_ddi_buf_trans {
> >> @@ -870,43 +830,27 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries)
> >> }
> >> }
> >>
> >> -static const struct icl_combo_phy_ddi_buf_trans *
> >> +static const struct cnl_ddi_buf_trans *
> >> icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
> >> int type, int *n_entries)
> >> {
> >> - u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
> >>
> >> if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
> >> - switch (voltage) {
> >> - case VOLTAGE_INFO_0_85V:
> >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
> >> - return icl_combo_phy_ddi_translations_edp_0_85V;
> >> - case VOLTAGE_INFO_0_95V:
> >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
> >> - return icl_combo_phy_ddi_translations_edp_0_95V;
> >> - case VOLTAGE_INFO_1_05V:
> >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
> >> - return icl_combo_phy_ddi_translations_edp_1_05V;
> >> - default:
> >> - MISSING_CASE(voltage);
> >> - return NULL;
> >> - }
> >> - } else {
> >> - switch (voltage) {
> >> - case VOLTAGE_INFO_0_85V:
> >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
> >> - return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
> >> - case VOLTAGE_INFO_0_95V:
> >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
> >> - return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
> >> - case VOLTAGE_INFO_1_05V:
> >> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
> >> - return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
> >> - default:
> >> - MISSING_CASE(voltage);
> >> - return NULL;
> >> - }
> >> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_lowswing);
> >> + return icl_combo_phy_ddi_translations_edp_lowswing;
> >> + } else if (type == INTEL_OUTPUT_EDP) {
> >> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> >> + return icl_combo_phy_ddi_translations_edp_hbr3;
> >> + } else if ((type == INTEL_OUTPUT_DP) || (type == INTEL_OUTPUT_DDI) ||
> >> + (type == INTEL_OUTPUT_DP_MST)) {
> > I would move the hdmi case first to match how most other platforms do
> > it, and to eliminate this complicated DP check.
> Agreed.
> >
> >> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp);
> >> + return icl_combo_phy_ddi_translations_dp;
> >> + } else if (type == INTEL_OUTPUT_HDMI) {
> >> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> >> + return icl_combo_phy_ddi_translations_hdmi;
> >> }
> >> +
> >> + return NULL;
> >> }
> >>
> >> static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
> >> @@ -2463,7 +2407,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
> >> static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> >> u32 level, enum port port, int type)
> >> {
> >> - const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
> >> + const struct cnl_ddi_buf_trans *ddi_translations = NULL;
> >> u32 n_entries, val;
> >> int ln;
> >>
> >> @@ -2477,34 +2421,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> >> level = n_entries - 1;
> >> }
> >>
> >> - /* Set PORT_TX_DW5 Rterm Sel to 110b. */
> >> + /* Set PORT_TX_DW5 */
> >> val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> >> - val &= ~RTERM_SELECT_MASK;
> >> + val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
> >> + TAP2_DISABLE | TAP3_DISABLE);
> >> + val |= SCALING_MODE_SEL(0x2);
> >> val |= RTERM_SELECT(0x6);
> >> - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
> >> -
> >> - /* Program PORT_TX_DW5 */
> >> - val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> >> - /* Set DisableTap2 and DisableTap3 if MIPI DSI
> >> - * Clear DisableTap2 and DisableTap3 for all other Ports
> >> - */
> >> - if (type == INTEL_OUTPUT_DSI) {
> >> - val |= TAP2_DISABLE;
> >> - val |= TAP3_DISABLE;
> >> - } else {
> >> - val &= ~TAP2_DISABLE;
> >> - val &= ~TAP3_DISABLE;
> >> - }
> >> + val |= TAP3_DISABLE;
> >> I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
> >>
> >> /* Program PORT_TX_DW2 */
> >> val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> >> val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> >> RCOMP_SCALAR_MASK);
> >> - val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
> >> - val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
> >> + val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
> >> + val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
> >> /* Program Rcomp scalar for every table entry */
> >> - val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
> >> + val |= RCOMP_SCALAR(0x98);
> >> I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
> >>
> >> /* Program PORT_TX_DW4 */
> >> @@ -2513,9 +2446,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> >> val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
> >> val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> >> CURSOR_COEFF_MASK);
> >> - val |= ddi_translations[level].dw4_scaling;
> >> + val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
> >> + val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
> >> + val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
> >> I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
> >> }
> >> +
> >> + /* Program PORT_TX_DW7 */
> > The comment is redundant.
> It's consistent with the other comments in the function. The CNL
> function also has the exact same comment. Are you sure you want me to
> remove this comment?
Meh. I guess keep it it it's consistent with the rest. Or send a patch
to nuke all the redundant comments.
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3] drm/i915/icl: combo port vswing programming changes per BSPEC
2018-11-30 22:58 [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC clinton.a.taylor
` (5 preceding siblings ...)
2018-12-03 12:19 ` [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC Ville Syrjälä
@ 2018-12-04 23:41 ` clinton.a.taylor
2018-12-05 16:32 ` Imre Deak
` (2 more replies)
2018-12-04 23:47 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: combo port vswing programming changes per BSPEC (rev3) Patchwork
` (6 subsequent siblings)
13 siblings, 3 replies; 26+ messages in thread
From: clinton.a.taylor @ 2018-12-04 23:41 UTC (permalink / raw)
To: Intel-gfx; +Cc: Rodrigo Vivi
From: Clint Taylor <clinton.a.taylor@intel.com>
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence.
v2: remove debug code that Imre found
v3: simplify translation table if-else
BSpec: 21257
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 +
drivers/gpu/drm/i915/intel_ddi.c | 224 ++++++++++++++-------------------------
2 files changed, 85 insertions(+), 143 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a7d605..29acdb9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1866,6 +1866,10 @@ enum i915_power_well_id {
#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
+#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
+#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
+#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
+#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
#define N_SCALAR(x) ((x) << 24)
#define N_SCALAR_MASK (0x7F << 24)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f3e1d6a..d78ec17 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -494,103 +494,63 @@ struct cnl_ddi_buf_trans {
{ 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
};
-struct icl_combo_phy_ddi_buf_trans {
- u32 dw2_swing_select;
- u32 dw2_swing_scalar;
- u32 dw4_scaling;
-};
-
-/* Voltage Swing Programming for VccIO 0.85V for DP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
- /* Voltage mV db */
- { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
- { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
- { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
- { 0x2, 0x98, 0x900F }, /* 400 9.5 */
- { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
- { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
- { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
- { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
- { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
- { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
-};
-
-/* FIXME - After table is updated in Bspec */
-/* Voltage Swing Programming for VccIO 0.85V for eDP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
- /* Voltage mV db */
- { 0x0, 0x00, 0x00 }, /* 200 0.0 */
- { 0x0, 0x00, 0x00 }, /* 200 1.5 */
- { 0x0, 0x00, 0x00 }, /* 200 4.0 */
- { 0x0, 0x00, 0x00 }, /* 200 6.0 */
- { 0x0, 0x00, 0x00 }, /* 250 0.0 */
- { 0x0, 0x00, 0x00 }, /* 250 1.5 */
- { 0x0, 0x00, 0x00 }, /* 250 4.0 */
- { 0x0, 0x00, 0x00 }, /* 300 0.0 */
- { 0x0, 0x00, 0x00 }, /* 300 1.5 */
- { 0x0, 0x00, 0x00 }, /* 350 0.0 */
+/* icl_combo_phy_ddi_translations */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
+ { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
+ { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
+ { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 705 0.6 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
};
-/* Voltage Swing Programming for VccIO 0.95V for DP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
- /* Voltage mV db */
- { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
- { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
- { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
- { 0x2, 0x98, 0x900F }, /* 400 9.5 */
- { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
- { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
- { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
- { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
- { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
- { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_lowswing[] = {
+ /* NT mV Trans mV db */
+ { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
+ { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
+ { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
+ { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
+ { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
+ { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
+ { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
+ { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
+ { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
+ { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
};
-/* FIXME - After table is updated in Bspec */
-/* Voltage Swing Programming for VccIO 0.95V for eDP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
- /* Voltage mV db */
- { 0x0, 0x00, 0x00 }, /* 200 0.0 */
- { 0x0, 0x00, 0x00 }, /* 200 1.5 */
- { 0x0, 0x00, 0x00 }, /* 200 4.0 */
- { 0x0, 0x00, 0x00 }, /* 200 6.0 */
- { 0x0, 0x00, 0x00 }, /* 250 0.0 */
- { 0x0, 0x00, 0x00 }, /* 250 1.5 */
- { 0x0, 0x00, 0x00 }, /* 250 4.0 */
- { 0x0, 0x00, 0x00 }, /* 300 0.0 */
- { 0x0, 0x00, 0x00 }, /* 300 1.5 */
- { 0x0, 0x00, 0x00 }, /* 350 0.0 */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
+ { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
+ { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
+ { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
};
-/* Voltage Swing Programming for VccIO 1.05V for DP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
- /* Voltage mV db */
- { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
- { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
- { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
- { 0x2, 0x98, 0x900F }, /* 400 9.5 */
- { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
- { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
- { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
- { 0x5, 0x71, 0x0018 }, /* 800 0.0 */
- { 0x5, 0x71, 0x3015 }, /* 800 3.5 */
- { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
+ { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
+ { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
+ { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
+ { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
};
-/* FIXME - After table is updated in Bspec */
-/* Voltage Swing Programming for VccIO 1.05V for eDP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
- /* Voltage mV db */
- { 0x0, 0x00, 0x00 }, /* 200 0.0 */
- { 0x0, 0x00, 0x00 }, /* 200 1.5 */
- { 0x0, 0x00, 0x00 }, /* 200 4.0 */
- { 0x0, 0x00, 0x00 }, /* 200 6.0 */
- { 0x0, 0x00, 0x00 }, /* 250 0.0 */
- { 0x0, 0x00, 0x00 }, /* 250 1.5 */
- { 0x0, 0x00, 0x00 }, /* 250 4.0 */
- { 0x0, 0x00, 0x00 }, /* 300 0.0 */
- { 0x0, 0x00, 0x00 }, /* 300 1.5 */
- { 0x0, 0x00, 0x00 }, /* 350 0.0 */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_mipi[] = {
+ /* NT mV Trans mV db */
+ { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
};
struct icl_mg_phy_ddi_buf_trans {
@@ -871,43 +831,24 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries)
}
}
-static const struct icl_combo_phy_ddi_buf_trans *
+static const struct cnl_ddi_buf_trans *
icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
int type, int *n_entries)
{
- u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
-
- if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
- switch (voltage) {
- case VOLTAGE_INFO_0_85V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
- return icl_combo_phy_ddi_translations_edp_0_85V;
- case VOLTAGE_INFO_0_95V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
- return icl_combo_phy_ddi_translations_edp_0_95V;
- case VOLTAGE_INFO_1_05V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
- return icl_combo_phy_ddi_translations_edp_1_05V;
- default:
- MISSING_CASE(voltage);
- return NULL;
- }
- } else {
- switch (voltage) {
- case VOLTAGE_INFO_0_85V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
- return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
- case VOLTAGE_INFO_0_95V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
- return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
- case VOLTAGE_INFO_1_05V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
- return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
- default:
- MISSING_CASE(voltage);
- return NULL;
- }
+
+ if (type == INTEL_OUTPUT_HDMI) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+ return icl_combo_phy_ddi_translations_hdmi;
+ } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_lowswing);
+ return icl_combo_phy_ddi_translations_edp_lowswing;
+ } else if (type == INTEL_OUTPUT_EDP) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
+ return icl_combo_phy_ddi_translations_edp_hbr3;
}
+
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp);
+ return icl_combo_phy_ddi_translations_dp;
}
static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
@@ -2464,7 +2405,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
u32 level, enum port port, int type)
{
- const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
+ const struct cnl_ddi_buf_trans *ddi_translations = NULL;
u32 n_entries, val;
int ln;
@@ -2478,34 +2419,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
level = n_entries - 1;
}
- /* Set PORT_TX_DW5 Rterm Sel to 110b. */
+ /* Set PORT_TX_DW5 */
val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
- val &= ~RTERM_SELECT_MASK;
+ val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
+ TAP2_DISABLE | TAP3_DISABLE);
+ val |= SCALING_MODE_SEL(0x2);
val |= RTERM_SELECT(0x6);
- I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
-
- /* Program PORT_TX_DW5 */
- val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
- /* Set DisableTap2 and DisableTap3 if MIPI DSI
- * Clear DisableTap2 and DisableTap3 for all other Ports
- */
- if (type == INTEL_OUTPUT_DSI) {
- val |= TAP2_DISABLE;
- val |= TAP3_DISABLE;
- } else {
- val &= ~TAP2_DISABLE;
- val &= ~TAP3_DISABLE;
- }
+ val |= TAP3_DISABLE;
I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
/* Program PORT_TX_DW2 */
val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
RCOMP_SCALAR_MASK);
- val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
- val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
+ val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
+ val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
/* Program Rcomp scalar for every table entry */
- val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
+ val |= RCOMP_SCALAR(0x98);
I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
/* Program PORT_TX_DW4 */
@@ -2514,9 +2444,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
CURSOR_COEFF_MASK);
- val |= ddi_translations[level].dw4_scaling;
+ val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
+ val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
+ val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
}
+
+ /* Program PORT_TX_DW7 */
+ val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
+ val &= ~N_SCALAR_MASK;
+ val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
+ I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
}
static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: combo port vswing programming changes per BSPEC (rev3)
2018-11-30 22:58 [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC clinton.a.taylor
` (6 preceding siblings ...)
2018-12-04 23:41 ` [PATCH v3] " clinton.a.taylor
@ 2018-12-04 23:47 ` Patchwork
2018-12-05 0:09 ` ✗ Fi.CI.BAT: failure " Patchwork
` (5 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2018-12-04 23:47 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: combo port vswing programming changes per BSPEC (rev3)
URL : https://patchwork.freedesktop.org/series/53340/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9a181831a873 drm/i915/icl: combo port vswing programming changes per BSPEC
-:234: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#234: FILE: drivers/gpu/drm/i915/intel_ddi.c:838:
{
+
total: 0 errors, 0 warnings, 1 checks, 287 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/icl: combo port vswing programming changes per BSPEC (rev3)
2018-11-30 22:58 [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC clinton.a.taylor
` (7 preceding siblings ...)
2018-12-04 23:47 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: combo port vswing programming changes per BSPEC (rev3) Patchwork
@ 2018-12-05 0:09 ` Patchwork
2018-12-11 21:38 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: combo port vswing programming changes per BSPEC (rev4) Patchwork
` (4 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2018-12-05 0:09 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: combo port vswing programming changes per BSPEC (rev3)
URL : https://patchwork.freedesktop.org/series/53340/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5263 -> Patchwork_11015
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_11015 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11015, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/53340/revisions/3/mbox/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_11015:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_sanitycheck:
- fi-bxt-dsi: PASS -> DMESG-WARN
* {igt@runner@aborted}:
- fi-bxt-dsi: NOTRUN -> FAIL
#### Warnings ####
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
- {fi-kbl-7567u}: SKIP -> PASS +33
Known issues
------------
Here are the changes found in Patchwork_11015 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-ivb-3520m: PASS -> FAIL [fdo#108880]
* igt@i915_selftest@live_hangcheck:
- fi-skl-iommu: PASS -> INCOMPLETE [fdo#108602] / [fdo#108744]
- {fi-icl-u3}: NOTRUN -> INCOMPLETE [fdo#108315]
* {igt@runner@aborted}:
- {fi-icl-u3}: NOTRUN -> FAIL [fdo#108315] / [fdo#108928]
- fi-skl-iommu: NOTRUN -> FAIL [fdo#108602]
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
* igt@i915_module_load@reload-with-fault-injection:
- fi-skl-6770hq: DMESG-WARN [fdo#105541] -> PASS
- {fi-kbl-7567u}: DMESG-WARN [fdo#105602] / [fdo#108529] -> PASS +1
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u3}: FAIL [fdo#103167] -> PASS
* igt@pm_rpm@module-reload:
- {fi-kbl-7567u}: DMESG-WARN [fdo#108529] -> PASS
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: FAIL [fdo#104008] -> PASS
#### Warnings ####
* igt@i915_selftest@live_contexts:
- {fi-icl-u3}: INCOMPLETE [fdo#108315] -> DMESG-FAIL [fdo#108569]
* igt@kms_chamelium@common-hpd-after-suspend:
- {fi-kbl-7567u}: DMESG-FAIL [fdo#105079] -> DMESG-WARN [fdo#108473]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008
[fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
[fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108315]: https://bugs.freedesktop.org/show_bug.cgi?id=108315
[fdo#108473]: https://bugs.freedesktop.org/show_bug.cgi?id=108473
[fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#108880]: https://bugs.freedesktop.org/show_bug.cgi?id=108880
[fdo#108928]: https://bugs.freedesktop.org/show_bug.cgi?id=108928
Participating hosts (50 -> 44)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-y
Build changes
-------------
* Linux: CI_DRM_5263 -> Patchwork_11015
CI_DRM_5263: 823664600f1dc6b351612283cd13836b0d768251 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4740: dd8de0efa64e50bc06c2882a0028d98ad870e752 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11015: 9a181831a873a8941ed83fcf199cde9da04af292 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9a181831a873 drm/i915/icl: combo port vswing programming changes per BSPEC
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11015/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3] drm/i915/icl: combo port vswing programming changes per BSPEC
2018-12-04 23:41 ` [PATCH v3] " clinton.a.taylor
@ 2018-12-05 16:32 ` Imre Deak
2018-12-11 9:40 ` Imre Deak
2018-12-11 21:31 ` [PATCH v4] " clinton.a.taylor
2018-12-17 22:13 ` [PATCH v5] " clinton.a.taylor
2 siblings, 1 reply; 26+ messages in thread
From: Imre Deak @ 2018-12-05 16:32 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: Intel-gfx, Rodrigo Vivi
On Tue, Dec 04, 2018 at 03:41:09PM -0800, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> In August 2018 the BSPEC changed the ICL port programming sequence to
> closely resemble earlier gen programming sequence.
>
> v2: remove debug code that Imre found
> v3: simplify translation table if-else
>
> BSpec: 21257
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 +
> drivers/gpu/drm/i915/intel_ddi.c | 224 ++++++++++++++-------------------------
> 2 files changed, 85 insertions(+), 143 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0a7d605..29acdb9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1866,6 +1866,10 @@ enum i915_power_well_id {
>
> #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
> #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
> +#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
> +#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
> +#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
> +#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
Looks like _CNL_PORT_TX_DW_GRP() is inconsistent with the ICL
counterpart and CNL_PORT_TX_DW2_* / CNL_PORT_TX_DW5_* are broken atm,
they need to be fixed as a follow-up.
> #define N_SCALAR(x) ((x) << 24)
> #define N_SCALAR_MASK (0x7F << 24)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index f3e1d6a..d78ec17 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -494,103 +494,63 @@ struct cnl_ddi_buf_trans {
> { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
> };
>
> -struct icl_combo_phy_ddi_buf_trans {
> - u32 dw2_swing_select;
> - u32 dw2_swing_scalar;
> - u32 dw4_scaling;
> -};
> -
> -/* Voltage Swing Programming for VccIO 0.85V for DP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
> - /* Voltage mV db */
> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> - { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
> - { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
> - { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
> - { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
> - { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> -};
> -
> -/* FIXME - After table is updated in Bspec */
> -/* Voltage Swing Programming for VccIO 0.85V for eDP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
> - /* Voltage mV db */
> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> +/* icl_combo_phy_ddi_translations */
> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp[] = {
> + /* NT mV Trans mV db */
> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 705 0.6 */
----^ 700
> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> };
>
> -/* Voltage Swing Programming for VccIO 0.95V for DP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
> - /* Voltage mV db */
> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
> - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
> - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
> - { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
> - { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_lowswing[] = {
> + /* NT mV Trans mV db */
> + { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
> + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
> + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
> + { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
> + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
> + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
> + { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
> + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
> + { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
> + { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> };
>
> -/* FIXME - After table is updated in Bspec */
> -/* Voltage Swing Programming for VccIO 0.95V for eDP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
> - /* Voltage mV db */
> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
> + /* NT mV Trans mV db */
> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> };
>
> -/* Voltage Swing Programming for VccIO 1.05V for DP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
> - /* Voltage mV db */
> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
> - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
> - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
> - { 0x5, 0x71, 0x0018 }, /* 800 0.0 */
> - { 0x5, 0x71, 0x3015 }, /* 800 3.5 */
> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
> + /* NT mV Trans mV db */
> + { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
> + { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
> + { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
> + { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
> + { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
> };
>
> -/* FIXME - After table is updated in Bspec */
> -/* Voltage Swing Programming for VccIO 1.05V for eDP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
> - /* Voltage mV db */
> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_mipi[] = {
> + /* NT mV Trans mV db */
> + { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
The DSI code has its own PHY programming atm, and this table here is
unused so no need adding it.
Unrelated but looks like the DSI code doesn't program ICL_PORT_TX_DW7,
that should be fixed as a follow-up.
> };
>
> struct icl_mg_phy_ddi_buf_trans {
> @@ -871,43 +831,24 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries)
> }
> }
>
> -static const struct icl_combo_phy_ddi_buf_trans *
> +static const struct cnl_ddi_buf_trans *
> icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
> int type, int *n_entries)
> {
> - u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
> -
> - if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
> - switch (voltage) {
> - case VOLTAGE_INFO_0_85V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
> - return icl_combo_phy_ddi_translations_edp_0_85V;
> - case VOLTAGE_INFO_0_95V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
> - return icl_combo_phy_ddi_translations_edp_0_95V;
> - case VOLTAGE_INFO_1_05V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
> - return icl_combo_phy_ddi_translations_edp_1_05V;
> - default:
> - MISSING_CASE(voltage);
> - return NULL;
> - }
> - } else {
> - switch (voltage) {
> - case VOLTAGE_INFO_0_85V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
> - return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
> - case VOLTAGE_INFO_0_95V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
> - return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
> - case VOLTAGE_INFO_1_05V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
> - return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
> - default:
> - MISSING_CASE(voltage);
> - return NULL;
> - }
> +
> + if (type == INTEL_OUTPUT_HDMI) {
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> + return icl_combo_phy_ddi_translations_hdmi;
> + } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_lowswing);
> + return icl_combo_phy_ddi_translations_edp_lowswing;
Hm, both in the CNL and this ICL code, not sure why we would use the
HBR2 table when the low_vswing param is set. It would be more logical to
me that HBR2 is to be used when the actual link rate is HBR2, else we'd
use the HBR3 table. BXT, ICL still defined these low vswing tables but
CNL and ICL don't. We should at least ask for clarification about this
in BSpec.
Other than the above the patch looks ok, but I'd wait for the BSpec
clarification until adding R-b.
> + } else if (type == INTEL_OUTPUT_EDP) {
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> + return icl_combo_phy_ddi_translations_edp_hbr3;
> }
> +
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp);
> + return icl_combo_phy_ddi_translations_dp;
> }
>
> static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
> @@ -2464,7 +2405,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
> static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> u32 level, enum port port, int type)
> {
> - const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
> + const struct cnl_ddi_buf_trans *ddi_translations = NULL;
> u32 n_entries, val;
> int ln;
>
> @@ -2478,34 +2419,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> level = n_entries - 1;
> }
>
> - /* Set PORT_TX_DW5 Rterm Sel to 110b. */
> + /* Set PORT_TX_DW5 */
> val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> - val &= ~RTERM_SELECT_MASK;
> + val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
> + TAP2_DISABLE | TAP3_DISABLE);
> + val |= SCALING_MODE_SEL(0x2);
> val |= RTERM_SELECT(0x6);
> - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
> -
> - /* Program PORT_TX_DW5 */
> - val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> - /* Set DisableTap2 and DisableTap3 if MIPI DSI
> - * Clear DisableTap2 and DisableTap3 for all other Ports
> - */
> - if (type == INTEL_OUTPUT_DSI) {
> - val |= TAP2_DISABLE;
> - val |= TAP3_DISABLE;
> - } else {
> - val &= ~TAP2_DISABLE;
> - val &= ~TAP3_DISABLE;
> - }
> + val |= TAP3_DISABLE;
> I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
>
> /* Program PORT_TX_DW2 */
> val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> RCOMP_SCALAR_MASK);
> - val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
> - val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
> + val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
> + val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
> /* Program Rcomp scalar for every table entry */
> - val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
> + val |= RCOMP_SCALAR(0x98);
> I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
>
> /* Program PORT_TX_DW4 */
> @@ -2514,9 +2444,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
> val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> CURSOR_COEFF_MASK);
> - val |= ddi_translations[level].dw4_scaling;
> + val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
> + val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
> + val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
> I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
> }
> +
> + /* Program PORT_TX_DW7 */
> + val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
> + val &= ~N_SCALAR_MASK;
> + val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
> + I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
> }
>
> static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> --
> 1.9.1
>
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3] drm/i915/icl: combo port vswing programming changes per BSPEC
2018-12-05 16:32 ` Imre Deak
@ 2018-12-11 9:40 ` Imre Deak
2018-12-11 14:18 ` Ville Syrjälä
0 siblings, 1 reply; 26+ messages in thread
From: Imre Deak @ 2018-12-11 9:40 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: Intel-gfx, Rodrigo Vivi
On Wed, Dec 05, 2018 at 06:32:22PM +0200, Imre Deak wrote:
> On Tue, Dec 04, 2018 at 03:41:09PM -0800, clinton.a.taylor@intel.com wrote:
> > From: Clint Taylor <clinton.a.taylor@intel.com>
> >
> > In August 2018 the BSPEC changed the ICL port programming sequence to
> > closely resemble earlier gen programming sequence.
> >
> > v2: remove debug code that Imre found
> > v3: simplify translation table if-else
> >
> > BSpec: 21257
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 4 +
> > drivers/gpu/drm/i915/intel_ddi.c | 224 ++++++++++++++-------------------------
> > 2 files changed, 85 insertions(+), 143 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 0a7d605..29acdb9 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1866,6 +1866,10 @@ enum i915_power_well_id {
> >
> > #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
> > #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
> > +#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
> > +#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
> > +#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
> > +#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
>
> Looks like _CNL_PORT_TX_DW_GRP() is inconsistent with the ICL
> counterpart and CNL_PORT_TX_DW2_* / CNL_PORT_TX_DW5_* are broken atm,
> they need to be fixed as a follow-up.
>
> > #define N_SCALAR(x) ((x) << 24)
> > #define N_SCALAR_MASK (0x7F << 24)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index f3e1d6a..d78ec17 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -494,103 +494,63 @@ struct cnl_ddi_buf_trans {
> > { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
> > };
> >
> > -struct icl_combo_phy_ddi_buf_trans {
> > - u32 dw2_swing_select;
> > - u32 dw2_swing_scalar;
> > - u32 dw4_scaling;
> > -};
> > -
> > -/* Voltage Swing Programming for VccIO 0.85V for DP */
> > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
> > - /* Voltage mV db */
> > - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> > - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> > - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> > - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> > - { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
> > - { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
> > - { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
> > - { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
> > - { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
> > - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> > -};
> > -
> > -/* FIXME - After table is updated in Bspec */
> > -/* Voltage Swing Programming for VccIO 0.85V for eDP */
> > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
> > - /* Voltage mV db */
> > - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> > - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> > - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> > - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> > - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> > - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> > - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> > - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> > - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> > - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> > +/* icl_combo_phy_ddi_translations */
> > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp[] = {
> > + /* NT mV Trans mV db */
> > + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> > + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
> > + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> > + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
> > + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> > + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
> > + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
> > + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 705 0.6 */
> ----^ 700
>
> > + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> > + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> > };
> >
> > -/* Voltage Swing Programming for VccIO 0.95V for DP */
> > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
> > - /* Voltage mV db */
> > - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> > - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> > - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> > - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> > - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
> > - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
> > - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
> > - { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
> > - { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
> > - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_lowswing[] = {
> > + /* NT mV Trans mV db */
> > + { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
> > + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
> > + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
> > + { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
> > + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
> > + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
> > + { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
> > + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
> > + { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
> > + { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> > };
> >
> > -/* FIXME - After table is updated in Bspec */
> > -/* Voltage Swing Programming for VccIO 0.95V for eDP */
> > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
> > - /* Voltage mV db */
> > - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> > - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> > - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> > - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> > - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> > - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> > - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> > - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> > - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> > - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
> > + /* NT mV Trans mV db */
> > + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> > + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
> > + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> > + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
> > + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> > + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
> > + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
> > + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
> > + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> > + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> > };
> >
> > -/* Voltage Swing Programming for VccIO 1.05V for DP */
> > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
> > - /* Voltage mV db */
> > - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> > - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> > - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> > - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> > - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
> > - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
> > - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
> > - { 0x5, 0x71, 0x0018 }, /* 800 0.0 */
> > - { 0x5, 0x71, 0x3015 }, /* 800 3.5 */
> > - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
> > + /* NT mV Trans mV db */
> > + { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
> > + { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
> > + { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
> > + { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
> > + { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
> > + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
> > + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
> > };
> >
> > -/* FIXME - After table is updated in Bspec */
> > -/* Voltage Swing Programming for VccIO 1.05V for eDP */
> > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
> > - /* Voltage mV db */
> > - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> > - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> > - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> > - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> > - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> > - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> > - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> > - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> > - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> > - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_mipi[] = {
> > + /* NT mV Trans mV db */
> > + { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
>
> The DSI code has its own PHY programming atm, and this table here is
> unused so no need adding it.
>
> Unrelated but looks like the DSI code doesn't program ICL_PORT_TX_DW7,
> that should be fixed as a follow-up.
>
> > };
> >
> > struct icl_mg_phy_ddi_buf_trans {
> > @@ -871,43 +831,24 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries)
> > }
> > }
> >
> > -static const struct icl_combo_phy_ddi_buf_trans *
> > +static const struct cnl_ddi_buf_trans *
> > icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
> > int type, int *n_entries)
> > {
> > - u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
> > -
> > - if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
> > - switch (voltage) {
> > - case VOLTAGE_INFO_0_85V:
> > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
> > - return icl_combo_phy_ddi_translations_edp_0_85V;
> > - case VOLTAGE_INFO_0_95V:
> > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
> > - return icl_combo_phy_ddi_translations_edp_0_95V;
> > - case VOLTAGE_INFO_1_05V:
> > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
> > - return icl_combo_phy_ddi_translations_edp_1_05V;
> > - default:
> > - MISSING_CASE(voltage);
> > - return NULL;
> > - }
> > - } else {
> > - switch (voltage) {
> > - case VOLTAGE_INFO_0_85V:
> > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
> > - return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
> > - case VOLTAGE_INFO_0_95V:
> > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
> > - return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
> > - case VOLTAGE_INFO_1_05V:
> > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
> > - return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
> > - default:
> > - MISSING_CASE(voltage);
> > - return NULL;
> > - }
> > +
> > + if (type == INTEL_OUTPUT_HDMI) {
> > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> > + return icl_combo_phy_ddi_translations_hdmi;
> > + } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
> > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_lowswing);
> > + return icl_combo_phy_ddi_translations_edp_lowswing;
>
> Hm, both in the CNL and this ICL code, not sure why we would use the
> HBR2 table when the low_vswing param is set. It would be more logical to
> me that HBR2 is to be used when the actual link rate is HBR2, else we'd
> use the HBR3 table. BXT, ICL still defined these low vswing tables but
> CNL and ICL don't. We should at least ask for clarification about this
> in BSpec.
Based on the recent BSpec update, we should just ignore
dev_priv->vbt.edp.low_vswing and use the "edp up to HBR2" table if the
link rate is <= HBR2 and the "edp HBR3" table otherwise.
Could you resend the patch with that changed (and the 2 other issues
above addressed)?
Thanks,
Imre
>
> Other than the above the patch looks ok, but I'd wait for the BSpec
> clarification until adding R-b.
>
> > + } else if (type == INTEL_OUTPUT_EDP) {
> > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> > + return icl_combo_phy_ddi_translations_edp_hbr3;
> > }
> > +
> > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp);
> > + return icl_combo_phy_ddi_translations_dp;
> > }
> >
> > static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
> > @@ -2464,7 +2405,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
> > static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> > u32 level, enum port port, int type)
> > {
> > - const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
> > + const struct cnl_ddi_buf_trans *ddi_translations = NULL;
> > u32 n_entries, val;
> > int ln;
> >
> > @@ -2478,34 +2419,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> > level = n_entries - 1;
> > }
> >
> > - /* Set PORT_TX_DW5 Rterm Sel to 110b. */
> > + /* Set PORT_TX_DW5 */
> > val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> > - val &= ~RTERM_SELECT_MASK;
> > + val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
> > + TAP2_DISABLE | TAP3_DISABLE);
> > + val |= SCALING_MODE_SEL(0x2);
> > val |= RTERM_SELECT(0x6);
> > - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
> > -
> > - /* Program PORT_TX_DW5 */
> > - val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> > - /* Set DisableTap2 and DisableTap3 if MIPI DSI
> > - * Clear DisableTap2 and DisableTap3 for all other Ports
> > - */
> > - if (type == INTEL_OUTPUT_DSI) {
> > - val |= TAP2_DISABLE;
> > - val |= TAP3_DISABLE;
> > - } else {
> > - val &= ~TAP2_DISABLE;
> > - val &= ~TAP3_DISABLE;
> > - }
> > + val |= TAP3_DISABLE;
> > I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
> >
> > /* Program PORT_TX_DW2 */
> > val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> > val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> > RCOMP_SCALAR_MASK);
> > - val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
> > - val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
> > + val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
> > + val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
> > /* Program Rcomp scalar for every table entry */
> > - val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
> > + val |= RCOMP_SCALAR(0x98);
> > I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
> >
> > /* Program PORT_TX_DW4 */
> > @@ -2514,9 +2444,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> > val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
> > val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> > CURSOR_COEFF_MASK);
> > - val |= ddi_translations[level].dw4_scaling;
> > + val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
> > + val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
> > + val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
> > I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
> > }
> > +
> > + /* Program PORT_TX_DW7 */
> > + val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
> > + val &= ~N_SCALAR_MASK;
> > + val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
> > + I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
> > }
> >
> > static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> > --
> > 1.9.1
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3] drm/i915/icl: combo port vswing programming changes per BSPEC
2018-12-11 9:40 ` Imre Deak
@ 2018-12-11 14:18 ` Ville Syrjälä
2018-12-11 14:25 ` Imre Deak
0 siblings, 1 reply; 26+ messages in thread
From: Ville Syrjälä @ 2018-12-11 14:18 UTC (permalink / raw)
To: Imre Deak; +Cc: Intel-gfx, Rodrigo Vivi
On Tue, Dec 11, 2018 at 11:40:43AM +0200, Imre Deak wrote:
> On Wed, Dec 05, 2018 at 06:32:22PM +0200, Imre Deak wrote:
> > On Tue, Dec 04, 2018 at 03:41:09PM -0800, clinton.a.taylor@intel.com wrote:
> > > From: Clint Taylor <clinton.a.taylor@intel.com>
> > >
> > > In August 2018 the BSPEC changed the ICL port programming sequence to
> > > closely resemble earlier gen programming sequence.
> > >
> > > v2: remove debug code that Imre found
> > > v3: simplify translation table if-else
> > >
> > > BSpec: 21257
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Cc: Imre Deak <imre.deak@intel.com>
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h | 4 +
> > > drivers/gpu/drm/i915/intel_ddi.c | 224 ++++++++++++++-------------------------
> > > 2 files changed, 85 insertions(+), 143 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 0a7d605..29acdb9 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -1866,6 +1866,10 @@ enum i915_power_well_id {
> > >
> > > #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
> > > #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
> > > +#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
> > > +#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
> > > +#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
> > > +#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
> >
> > Looks like _CNL_PORT_TX_DW_GRP() is inconsistent with the ICL
> > counterpart and CNL_PORT_TX_DW2_* / CNL_PORT_TX_DW5_* are broken atm,
> > they need to be fixed as a follow-up.
> >
> > > #define N_SCALAR(x) ((x) << 24)
> > > #define N_SCALAR_MASK (0x7F << 24)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > > index f3e1d6a..d78ec17 100644
> > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > @@ -494,103 +494,63 @@ struct cnl_ddi_buf_trans {
> > > { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
> > > };
> > >
> > > -struct icl_combo_phy_ddi_buf_trans {
> > > - u32 dw2_swing_select;
> > > - u32 dw2_swing_scalar;
> > > - u32 dw4_scaling;
> > > -};
> > > -
> > > -/* Voltage Swing Programming for VccIO 0.85V for DP */
> > > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
> > > - /* Voltage mV db */
> > > - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> > > - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> > > - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> > > - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> > > - { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
> > > - { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
> > > - { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
> > > - { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
> > > - { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
> > > - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> > > -};
> > > -
> > > -/* FIXME - After table is updated in Bspec */
> > > -/* Voltage Swing Programming for VccIO 0.85V for eDP */
> > > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
> > > - /* Voltage mV db */
> > > - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> > > - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> > > - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> > > - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> > > - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> > > - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> > > - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> > > - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> > > - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> > > - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> > > +/* icl_combo_phy_ddi_translations */
> > > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp[] = {
> > > + /* NT mV Trans mV db */
> > > + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> > > + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
> > > + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> > > + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
> > > + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> > > + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
> > > + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
> > > + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 705 0.6 */
> > ----^ 700
> >
> > > + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> > > + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> > > };
> > >
> > > -/* Voltage Swing Programming for VccIO 0.95V for DP */
> > > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
> > > - /* Voltage mV db */
> > > - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> > > - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> > > - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> > > - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> > > - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
> > > - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
> > > - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
> > > - { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
> > > - { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
> > > - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> > > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_lowswing[] = {
> > > + /* NT mV Trans mV db */
> > > + { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
> > > + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
> > > + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
> > > + { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
> > > + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
> > > + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
> > > + { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
> > > + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
> > > + { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
> > > + { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> > > };
> > >
> > > -/* FIXME - After table is updated in Bspec */
> > > -/* Voltage Swing Programming for VccIO 0.95V for eDP */
> > > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
> > > - /* Voltage mV db */
> > > - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> > > - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> > > - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> > > - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> > > - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> > > - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> > > - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> > > - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> > > - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> > > - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> > > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
> > > + /* NT mV Trans mV db */
> > > + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> > > + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
> > > + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> > > + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
> > > + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> > > + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
> > > + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
> > > + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
> > > + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> > > + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> > > };
> > >
> > > -/* Voltage Swing Programming for VccIO 1.05V for DP */
> > > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
> > > - /* Voltage mV db */
> > > - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> > > - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> > > - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> > > - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> > > - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
> > > - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
> > > - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
> > > - { 0x5, 0x71, 0x0018 }, /* 800 0.0 */
> > > - { 0x5, 0x71, 0x3015 }, /* 800 3.5 */
> > > - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> > > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
> > > + /* NT mV Trans mV db */
> > > + { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
> > > + { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
> > > + { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
> > > + { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
> > > + { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
> > > + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
> > > + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
> > > };
> > >
> > > -/* FIXME - After table is updated in Bspec */
> > > -/* Voltage Swing Programming for VccIO 1.05V for eDP */
> > > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
> > > - /* Voltage mV db */
> > > - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> > > - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> > > - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> > > - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> > > - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> > > - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> > > - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> > > - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> > > - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> > > - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> > > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_mipi[] = {
> > > + /* NT mV Trans mV db */
> > > + { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
> >
> > The DSI code has its own PHY programming atm, and this table here is
> > unused so no need adding it.
> >
> > Unrelated but looks like the DSI code doesn't program ICL_PORT_TX_DW7,
> > that should be fixed as a follow-up.
> >
> > > };
> > >
> > > struct icl_mg_phy_ddi_buf_trans {
> > > @@ -871,43 +831,24 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries)
> > > }
> > > }
> > >
> > > -static const struct icl_combo_phy_ddi_buf_trans *
> > > +static const struct cnl_ddi_buf_trans *
> > > icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
> > > int type, int *n_entries)
> > > {
> > > - u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
> > > -
> > > - if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
> > > - switch (voltage) {
> > > - case VOLTAGE_INFO_0_85V:
> > > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
> > > - return icl_combo_phy_ddi_translations_edp_0_85V;
> > > - case VOLTAGE_INFO_0_95V:
> > > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
> > > - return icl_combo_phy_ddi_translations_edp_0_95V;
> > > - case VOLTAGE_INFO_1_05V:
> > > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
> > > - return icl_combo_phy_ddi_translations_edp_1_05V;
> > > - default:
> > > - MISSING_CASE(voltage);
> > > - return NULL;
> > > - }
> > > - } else {
> > > - switch (voltage) {
> > > - case VOLTAGE_INFO_0_85V:
> > > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
> > > - return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
> > > - case VOLTAGE_INFO_0_95V:
> > > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
> > > - return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
> > > - case VOLTAGE_INFO_1_05V:
> > > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
> > > - return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
> > > - default:
> > > - MISSING_CASE(voltage);
> > > - return NULL;
> > > - }
> > > +
> > > + if (type == INTEL_OUTPUT_HDMI) {
> > > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> > > + return icl_combo_phy_ddi_translations_hdmi;
> > > + } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
> > > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_lowswing);
> > > + return icl_combo_phy_ddi_translations_edp_lowswing;
> >
> > Hm, both in the CNL and this ICL code, not sure why we would use the
> > HBR2 table when the low_vswing param is set. It would be more logical to
> > me that HBR2 is to be used when the actual link rate is HBR2, else we'd
> > use the HBR3 table. BXT, ICL still defined these low vswing tables but
> > CNL and ICL don't. We should at least ask for clarification about this
> > in BSpec.
>
> Based on the recent BSpec update, we should just ignore
> dev_priv->vbt.edp.low_vswing and use the "edp up to HBR2" table if the
> link rate is <= HBR2 and the "edp HBR3" table otherwise.
After Art's clarification I think the correct logic will be:
if (hdmi) {
return ...;
else if (rate == 8.1) // could check for edp too here i suppose
return icl_combo_phy_ddi_translations_edp_hbr3;
else if (edp && low_vswing)
return icl_combo_phy_ddi_translations_edp_hbr2;
else
return icl_combo_phy_ddi_translations_dp_hbr2;
And I believe icl_max_source_rate() needs to be changed to
something like:
if (is_combo_phy() && !edp)
return 5.4;
return 8.1;
>
> Could you resend the patch with that changed (and the 2 other issues
> above addressed)?
>
> Thanks,
> Imre
>
> >
> > Other than the above the patch looks ok, but I'd wait for the BSpec
> > clarification until adding R-b.
> >
> > > + } else if (type == INTEL_OUTPUT_EDP) {
> > > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> > > + return icl_combo_phy_ddi_translations_edp_hbr3;
> > > }
> > > +
> > > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp);
> > > + return icl_combo_phy_ddi_translations_dp;
> > > }
> > >
> > > static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
> > > @@ -2464,7 +2405,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
> > > static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> > > u32 level, enum port port, int type)
> > > {
> > > - const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
> > > + const struct cnl_ddi_buf_trans *ddi_translations = NULL;
> > > u32 n_entries, val;
> > > int ln;
> > >
> > > @@ -2478,34 +2419,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> > > level = n_entries - 1;
> > > }
> > >
> > > - /* Set PORT_TX_DW5 Rterm Sel to 110b. */
> > > + /* Set PORT_TX_DW5 */
> > > val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> > > - val &= ~RTERM_SELECT_MASK;
> > > + val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
> > > + TAP2_DISABLE | TAP3_DISABLE);
> > > + val |= SCALING_MODE_SEL(0x2);
> > > val |= RTERM_SELECT(0x6);
> > > - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
> > > -
> > > - /* Program PORT_TX_DW5 */
> > > - val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> > > - /* Set DisableTap2 and DisableTap3 if MIPI DSI
> > > - * Clear DisableTap2 and DisableTap3 for all other Ports
> > > - */
> > > - if (type == INTEL_OUTPUT_DSI) {
> > > - val |= TAP2_DISABLE;
> > > - val |= TAP3_DISABLE;
> > > - } else {
> > > - val &= ~TAP2_DISABLE;
> > > - val &= ~TAP3_DISABLE;
> > > - }
> > > + val |= TAP3_DISABLE;
> > > I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
> > >
> > > /* Program PORT_TX_DW2 */
> > > val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> > > val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> > > RCOMP_SCALAR_MASK);
> > > - val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
> > > - val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
> > > + val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
> > > + val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
> > > /* Program Rcomp scalar for every table entry */
> > > - val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
> > > + val |= RCOMP_SCALAR(0x98);
> > > I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
> > >
> > > /* Program PORT_TX_DW4 */
> > > @@ -2514,9 +2444,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> > > val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
> > > val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> > > CURSOR_COEFF_MASK);
> > > - val |= ddi_translations[level].dw4_scaling;
> > > + val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
> > > + val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
> > > + val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
> > > I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
> > > }
> > > +
> > > + /* Program PORT_TX_DW7 */
> > > + val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
> > > + val &= ~N_SCALAR_MASK;
> > > + val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
> > > + I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
> > > }
> > >
> > > static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> > > --
> > > 1.9.1
> > >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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* Re: [PATCH v3] drm/i915/icl: combo port vswing programming changes per BSPEC
2018-12-11 14:18 ` Ville Syrjälä
@ 2018-12-11 14:25 ` Imre Deak
0 siblings, 0 replies; 26+ messages in thread
From: Imre Deak @ 2018-12-11 14:25 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Intel-gfx, Rodrigo Vivi
On Tue, Dec 11, 2018 at 04:18:47PM +0200, Ville Syrjälä wrote:
> On Tue, Dec 11, 2018 at 11:40:43AM +0200, Imre Deak wrote:
> > On Wed, Dec 05, 2018 at 06:32:22PM +0200, Imre Deak wrote:
> > > On Tue, Dec 04, 2018 at 03:41:09PM -0800, clinton.a.taylor@intel.com wrote:
> > > > From: Clint Taylor <clinton.a.taylor@intel.com>
> > > >
> > > > In August 2018 the BSPEC changed the ICL port programming sequence to
> > > > closely resemble earlier gen programming sequence.
> > > >
> > > > v2: remove debug code that Imre found
> > > > v3: simplify translation table if-else
> > > >
> > > > BSpec: 21257
> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > Cc: Imre Deak <imre.deak@intel.com>
> > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/i915_reg.h | 4 +
> > > > drivers/gpu/drm/i915/intel_ddi.c | 224 ++++++++++++++-------------------------
> > > > 2 files changed, 85 insertions(+), 143 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 0a7d605..29acdb9 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -1866,6 +1866,10 @@ enum i915_power_well_id {
> > > >
> > > > #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
> > > > #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
> > > > +#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
> > > > +#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
> > > > +#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
> > > > +#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
> > >
> > > Looks like _CNL_PORT_TX_DW_GRP() is inconsistent with the ICL
> > > counterpart and CNL_PORT_TX_DW2_* / CNL_PORT_TX_DW5_* are broken atm,
> > > they need to be fixed as a follow-up.
> > >
> > > > #define N_SCALAR(x) ((x) << 24)
> > > > #define N_SCALAR_MASK (0x7F << 24)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > > > index f3e1d6a..d78ec17 100644
> > > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > > @@ -494,103 +494,63 @@ struct cnl_ddi_buf_trans {
> > > > { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
> > > > };
> > > >
> > > > -struct icl_combo_phy_ddi_buf_trans {
> > > > - u32 dw2_swing_select;
> > > > - u32 dw2_swing_scalar;
> > > > - u32 dw4_scaling;
> > > > -};
> > > > -
> > > > -/* Voltage Swing Programming for VccIO 0.85V for DP */
> > > > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
> > > > - /* Voltage mV db */
> > > > - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> > > > - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> > > > - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> > > > - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> > > > - { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
> > > > - { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
> > > > - { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
> > > > - { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
> > > > - { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
> > > > - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> > > > -};
> > > > -
> > > > -/* FIXME - After table is updated in Bspec */
> > > > -/* Voltage Swing Programming for VccIO 0.85V for eDP */
> > > > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
> > > > - /* Voltage mV db */
> > > > - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> > > > - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> > > > - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> > > > - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> > > > - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> > > > - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> > > > - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> > > > - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> > > > - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> > > > - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> > > > +/* icl_combo_phy_ddi_translations */
> > > > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp[] = {
> > > > + /* NT mV Trans mV db */
> > > > + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> > > > + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
> > > > + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> > > > + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
> > > > + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> > > > + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
> > > > + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
> > > > + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 705 0.6 */
> > > ----^ 700
> > >
> > > > + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> > > > + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> > > > };
> > > >
> > > > -/* Voltage Swing Programming for VccIO 0.95V for DP */
> > > > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
> > > > - /* Voltage mV db */
> > > > - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> > > > - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> > > > - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> > > > - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> > > > - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
> > > > - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
> > > > - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
> > > > - { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
> > > > - { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
> > > > - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> > > > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_lowswing[] = {
> > > > + /* NT mV Trans mV db */
> > > > + { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
> > > > + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
> > > > + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
> > > > + { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
> > > > + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
> > > > + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
> > > > + { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
> > > > + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
> > > > + { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
> > > > + { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> > > > };
> > > >
> > > > -/* FIXME - After table is updated in Bspec */
> > > > -/* Voltage Swing Programming for VccIO 0.95V for eDP */
> > > > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
> > > > - /* Voltage mV db */
> > > > - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> > > > - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> > > > - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> > > > - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> > > > - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> > > > - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> > > > - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> > > > - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> > > > - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> > > > - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> > > > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
> > > > + /* NT mV Trans mV db */
> > > > + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> > > > + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
> > > > + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> > > > + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
> > > > + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> > > > + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
> > > > + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
> > > > + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
> > > > + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> > > > + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> > > > };
> > > >
> > > > -/* Voltage Swing Programming for VccIO 1.05V for DP */
> > > > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
> > > > - /* Voltage mV db */
> > > > - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> > > > - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> > > > - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> > > > - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> > > > - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
> > > > - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
> > > > - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
> > > > - { 0x5, 0x71, 0x0018 }, /* 800 0.0 */
> > > > - { 0x5, 0x71, 0x3015 }, /* 800 3.5 */
> > > > - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> > > > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
> > > > + /* NT mV Trans mV db */
> > > > + { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
> > > > + { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
> > > > + { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
> > > > + { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
> > > > + { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
> > > > + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
> > > > + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
> > > > };
> > > >
> > > > -/* FIXME - After table is updated in Bspec */
> > > > -/* Voltage Swing Programming for VccIO 1.05V for eDP */
> > > > -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
> > > > - /* Voltage mV db */
> > > > - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> > > > - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> > > > - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> > > > - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> > > > - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> > > > - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> > > > - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> > > > - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> > > > - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> > > > - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> > > > +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_mipi[] = {
> > > > + /* NT mV Trans mV db */
> > > > + { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
> > >
> > > The DSI code has its own PHY programming atm, and this table here is
> > > unused so no need adding it.
> > >
> > > Unrelated but looks like the DSI code doesn't program ICL_PORT_TX_DW7,
> > > that should be fixed as a follow-up.
> > >
> > > > };
> > > >
> > > > struct icl_mg_phy_ddi_buf_trans {
> > > > @@ -871,43 +831,24 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries)
> > > > }
> > > > }
> > > >
> > > > -static const struct icl_combo_phy_ddi_buf_trans *
> > > > +static const struct cnl_ddi_buf_trans *
> > > > icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
> > > > int type, int *n_entries)
> > > > {
> > > > - u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
> > > > -
> > > > - if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
> > > > - switch (voltage) {
> > > > - case VOLTAGE_INFO_0_85V:
> > > > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
> > > > - return icl_combo_phy_ddi_translations_edp_0_85V;
> > > > - case VOLTAGE_INFO_0_95V:
> > > > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
> > > > - return icl_combo_phy_ddi_translations_edp_0_95V;
> > > > - case VOLTAGE_INFO_1_05V:
> > > > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
> > > > - return icl_combo_phy_ddi_translations_edp_1_05V;
> > > > - default:
> > > > - MISSING_CASE(voltage);
> > > > - return NULL;
> > > > - }
> > > > - } else {
> > > > - switch (voltage) {
> > > > - case VOLTAGE_INFO_0_85V:
> > > > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
> > > > - return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
> > > > - case VOLTAGE_INFO_0_95V:
> > > > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
> > > > - return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
> > > > - case VOLTAGE_INFO_1_05V:
> > > > - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
> > > > - return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
> > > > - default:
> > > > - MISSING_CASE(voltage);
> > > > - return NULL;
> > > > - }
> > > > +
> > > > + if (type == INTEL_OUTPUT_HDMI) {
> > > > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> > > > + return icl_combo_phy_ddi_translations_hdmi;
> > > > + } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
> > > > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_lowswing);
> > > > + return icl_combo_phy_ddi_translations_edp_lowswing;
> > >
> > > Hm, both in the CNL and this ICL code, not sure why we would use the
> > > HBR2 table when the low_vswing param is set. It would be more logical to
> > > me that HBR2 is to be used when the actual link rate is HBR2, else we'd
> > > use the HBR3 table. BXT, ICL still defined these low vswing tables but
> > > CNL and ICL don't. We should at least ask for clarification about this
> > > in BSpec.
> >
> > Based on the recent BSpec update, we should just ignore
> > dev_priv->vbt.edp.low_vswing and use the "edp up to HBR2" table if the
> > link rate is <= HBR2 and the "edp HBR3" table otherwise.
>
> After Art's clarification I think the correct logic will be:
>
> if (hdmi) {
> return ...;
> else if (rate == 8.1) // could check for edp too here i suppose
> return icl_combo_phy_ddi_translations_edp_hbr3;
> else if (edp && low_vswing)
> return icl_combo_phy_ddi_translations_edp_hbr2;
> else
> return icl_combo_phy_ddi_translations_dp_hbr2;
>
>
> And I believe icl_max_source_rate() needs to be changed to
> something like:
>
> if (is_combo_phy() && !edp)
> return 5.4;
> return 8.1;
Yep, correct, I misread in his comment thinking 'DP up to HBR2' is
'eDP up to HBR2'. The above logic you describe seems correct to me.
>
> >
> > Could you resend the patch with that changed (and the 2 other issues
> > above addressed)?
> >
> > Thanks,
> > Imre
> >
> > >
> > > Other than the above the patch looks ok, but I'd wait for the BSpec
> > > clarification until adding R-b.
> > >
> > > > + } else if (type == INTEL_OUTPUT_EDP) {
> > > > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> > > > + return icl_combo_phy_ddi_translations_edp_hbr3;
> > > > }
> > > > +
> > > > + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp);
> > > > + return icl_combo_phy_ddi_translations_dp;
> > > > }
> > > >
> > > > static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
> > > > @@ -2464,7 +2405,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
> > > > static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> > > > u32 level, enum port port, int type)
> > > > {
> > > > - const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
> > > > + const struct cnl_ddi_buf_trans *ddi_translations = NULL;
> > > > u32 n_entries, val;
> > > > int ln;
> > > >
> > > > @@ -2478,34 +2419,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> > > > level = n_entries - 1;
> > > > }
> > > >
> > > > - /* Set PORT_TX_DW5 Rterm Sel to 110b. */
> > > > + /* Set PORT_TX_DW5 */
> > > > val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> > > > - val &= ~RTERM_SELECT_MASK;
> > > > + val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
> > > > + TAP2_DISABLE | TAP3_DISABLE);
> > > > + val |= SCALING_MODE_SEL(0x2);
> > > > val |= RTERM_SELECT(0x6);
> > > > - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
> > > > -
> > > > - /* Program PORT_TX_DW5 */
> > > > - val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> > > > - /* Set DisableTap2 and DisableTap3 if MIPI DSI
> > > > - * Clear DisableTap2 and DisableTap3 for all other Ports
> > > > - */
> > > > - if (type == INTEL_OUTPUT_DSI) {
> > > > - val |= TAP2_DISABLE;
> > > > - val |= TAP3_DISABLE;
> > > > - } else {
> > > > - val &= ~TAP2_DISABLE;
> > > > - val &= ~TAP3_DISABLE;
> > > > - }
> > > > + val |= TAP3_DISABLE;
> > > > I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
> > > >
> > > > /* Program PORT_TX_DW2 */
> > > > val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> > > > val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> > > > RCOMP_SCALAR_MASK);
> > > > - val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
> > > > - val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
> > > > + val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
> > > > + val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
> > > > /* Program Rcomp scalar for every table entry */
> > > > - val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
> > > > + val |= RCOMP_SCALAR(0x98);
> > > > I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
> > > >
> > > > /* Program PORT_TX_DW4 */
> > > > @@ -2514,9 +2444,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> > > > val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
> > > > val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> > > > CURSOR_COEFF_MASK);
> > > > - val |= ddi_translations[level].dw4_scaling;
> > > > + val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
> > > > + val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
> > > > + val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
> > > > I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
> > > > }
> > > > +
> > > > + /* Program PORT_TX_DW7 */
> > > > + val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
> > > > + val &= ~N_SCALAR_MASK;
> > > > + val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
> > > > + I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
> > > > }
> > > >
> > > > static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> > > > --
> > > > 1.9.1
> > > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v4] drm/i915/icl: combo port vswing programming changes per BSPEC
2018-12-04 23:41 ` [PATCH v3] " clinton.a.taylor
2018-12-05 16:32 ` Imre Deak
@ 2018-12-11 21:31 ` clinton.a.taylor
2018-12-17 15:23 ` Imre Deak
2018-12-17 22:13 ` [PATCH v5] " clinton.a.taylor
2 siblings, 1 reply; 26+ messages in thread
From: clinton.a.taylor @ 2018-12-11 21:31 UTC (permalink / raw)
To: Intel-gfx; +Cc: Rodrigo Vivi
From: Clint Taylor <clinton.a.taylor@intel.com>
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence. Restrict combo phy to
HBR max rate unless eDP panel is connected to port.
v2: remove debug code that Imre found
v3: simplify translation table if-else
v4: edp translation table now based on link rate and low_swing
BSpec: 21257
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 +
drivers/gpu/drm/i915/intel_ddi.c | 240 ++++++++++++++-------------------------
drivers/gpu/drm/i915/intel_dp.c | 4 +-
3 files changed, 95 insertions(+), 153 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a7d605..29acdb9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1866,6 +1866,10 @@ enum i915_power_well_id {
#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
+#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
+#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
+#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
+#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
#define N_SCALAR(x) ((x) << 24)
#define N_SCALAR_MASK (0x7F << 24)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f3e1d6a..33bf77b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -494,103 +494,58 @@ struct cnl_ddi_buf_trans {
{ 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
};
-struct icl_combo_phy_ddi_buf_trans {
- u32 dw2_swing_select;
- u32 dw2_swing_scalar;
- u32 dw4_scaling;
-};
-
-/* Voltage Swing Programming for VccIO 0.85V for DP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
- /* Voltage mV db */
- { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
- { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
- { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
- { 0x2, 0x98, 0x900F }, /* 400 9.5 */
- { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
- { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
- { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
- { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
- { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
- { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
-};
-
-/* FIXME - After table is updated in Bspec */
-/* Voltage Swing Programming for VccIO 0.85V for eDP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
- /* Voltage mV db */
- { 0x0, 0x00, 0x00 }, /* 200 0.0 */
- { 0x0, 0x00, 0x00 }, /* 200 1.5 */
- { 0x0, 0x00, 0x00 }, /* 200 4.0 */
- { 0x0, 0x00, 0x00 }, /* 200 6.0 */
- { 0x0, 0x00, 0x00 }, /* 250 0.0 */
- { 0x0, 0x00, 0x00 }, /* 250 1.5 */
- { 0x0, 0x00, 0x00 }, /* 250 4.0 */
- { 0x0, 0x00, 0x00 }, /* 300 0.0 */
- { 0x0, 0x00, 0x00 }, /* 300 1.5 */
- { 0x0, 0x00, 0x00 }, /* 350 0.0 */
-};
-
-/* Voltage Swing Programming for VccIO 0.95V for DP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
- /* Voltage mV db */
- { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
- { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
- { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
- { 0x2, 0x98, 0x900F }, /* 400 9.5 */
- { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
- { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
- { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
- { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
- { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
- { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
+/* icl_combo_phy_ddi_translations */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
+ { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
+ { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
+ { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 705 0.6 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
};
-/* FIXME - After table is updated in Bspec */
-/* Voltage Swing Programming for VccIO 0.95V for eDP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
- /* Voltage mV db */
- { 0x0, 0x00, 0x00 }, /* 200 0.0 */
- { 0x0, 0x00, 0x00 }, /* 200 1.5 */
- { 0x0, 0x00, 0x00 }, /* 200 4.0 */
- { 0x0, 0x00, 0x00 }, /* 200 6.0 */
- { 0x0, 0x00, 0x00 }, /* 250 0.0 */
- { 0x0, 0x00, 0x00 }, /* 250 1.5 */
- { 0x0, 0x00, 0x00 }, /* 250 4.0 */
- { 0x0, 0x00, 0x00 }, /* 300 0.0 */
- { 0x0, 0x00, 0x00 }, /* 300 1.5 */
- { 0x0, 0x00, 0x00 }, /* 350 0.0 */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
+ /* NT mV Trans mV db */
+ { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
+ { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
+ { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
+ { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
+ { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
+ { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
+ { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
+ { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
+ { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
+ { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
};
-/* Voltage Swing Programming for VccIO 1.05V for DP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
- /* Voltage mV db */
- { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
- { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
- { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
- { 0x2, 0x98, 0x900F }, /* 400 9.5 */
- { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
- { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
- { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
- { 0x5, 0x71, 0x0018 }, /* 800 0.0 */
- { 0x5, 0x71, 0x3015 }, /* 800 3.5 */
- { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
+ { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
+ { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
+ { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
};
-/* FIXME - After table is updated in Bspec */
-/* Voltage Swing Programming for VccIO 1.05V for eDP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
- /* Voltage mV db */
- { 0x0, 0x00, 0x00 }, /* 200 0.0 */
- { 0x0, 0x00, 0x00 }, /* 200 1.5 */
- { 0x0, 0x00, 0x00 }, /* 200 4.0 */
- { 0x0, 0x00, 0x00 }, /* 200 6.0 */
- { 0x0, 0x00, 0x00 }, /* 250 0.0 */
- { 0x0, 0x00, 0x00 }, /* 250 1.5 */
- { 0x0, 0x00, 0x00 }, /* 250 4.0 */
- { 0x0, 0x00, 0x00 }, /* 300 0.0 */
- { 0x0, 0x00, 0x00 }, /* 300 1.5 */
- { 0x0, 0x00, 0x00 }, /* 350 0.0 */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
+ { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
+ { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
+ { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
+ { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
};
struct icl_mg_phy_ddi_buf_trans {
@@ -871,43 +826,23 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries)
}
}
-static const struct icl_combo_phy_ddi_buf_trans *
+static const struct cnl_ddi_buf_trans *
icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
- int type, int *n_entries)
+ int type, int rate, int *n_entries)
{
- u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
-
- if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
- switch (voltage) {
- case VOLTAGE_INFO_0_85V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
- return icl_combo_phy_ddi_translations_edp_0_85V;
- case VOLTAGE_INFO_0_95V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
- return icl_combo_phy_ddi_translations_edp_0_95V;
- case VOLTAGE_INFO_1_05V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
- return icl_combo_phy_ddi_translations_edp_1_05V;
- default:
- MISSING_CASE(voltage);
- return NULL;
- }
- } else {
- switch (voltage) {
- case VOLTAGE_INFO_0_85V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
- return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
- case VOLTAGE_INFO_0_95V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
- return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
- case VOLTAGE_INFO_1_05V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
- return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
- default:
- MISSING_CASE(voltage);
- return NULL;
- }
+ if (type == INTEL_OUTPUT_HDMI) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+ return icl_combo_phy_ddi_translations_hdmi;
+ } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
+ return icl_combo_phy_ddi_translations_edp_hbr3;
+ } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
+ return icl_combo_phy_ddi_translations_edp_hbr2;
}
+
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
+ return icl_combo_phy_ddi_translations_dp_hbr2;
}
static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
@@ -918,8 +853,8 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
if (IS_ICELAKE(dev_priv)) {
if (intel_port_is_combophy(dev_priv, port))
- icl_get_combo_buf_trans(dev_priv, port,
- INTEL_OUTPUT_HDMI, &n_entries);
+ icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
+ 540000, &n_entries);
else
n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
default_entry = n_entries - 1;
@@ -2275,13 +2210,16 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
enum port port = encoder->port;
int n_entries;
+ int rate = 0;
if (IS_ICELAKE(dev_priv)) {
+ rate = intel_dp->link_rate;
if (intel_port_is_combophy(dev_priv, port))
icl_get_combo_buf_trans(dev_priv, port, encoder->type,
- &n_entries);
+ rate, &n_entries);
else
n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
} else if (IS_CANNONLAKE(dev_priv)) {
@@ -2462,14 +2400,15 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
}
static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
- u32 level, enum port port, int type)
+ u32 level, enum port port, int type,
+ int rate)
{
- const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
+ const struct cnl_ddi_buf_trans *ddi_translations = NULL;
u32 n_entries, val;
int ln;
ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
- &n_entries);
+ rate, &n_entries);
if (!ddi_translations)
return;
@@ -2478,34 +2417,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
level = n_entries - 1;
}
- /* Set PORT_TX_DW5 Rterm Sel to 110b. */
+ /* Set PORT_TX_DW5 */
val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
- val &= ~RTERM_SELECT_MASK;
+ val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
+ TAP2_DISABLE | TAP3_DISABLE);
+ val |= SCALING_MODE_SEL(0x2);
val |= RTERM_SELECT(0x6);
- I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
-
- /* Program PORT_TX_DW5 */
- val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
- /* Set DisableTap2 and DisableTap3 if MIPI DSI
- * Clear DisableTap2 and DisableTap3 for all other Ports
- */
- if (type == INTEL_OUTPUT_DSI) {
- val |= TAP2_DISABLE;
- val |= TAP3_DISABLE;
- } else {
- val &= ~TAP2_DISABLE;
- val &= ~TAP3_DISABLE;
- }
+ val |= TAP3_DISABLE;
I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
/* Program PORT_TX_DW2 */
val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
RCOMP_SCALAR_MASK);
- val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
- val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
+ val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
+ val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
/* Program Rcomp scalar for every table entry */
- val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
+ val |= RCOMP_SCALAR(0x98);
I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
/* Program PORT_TX_DW4 */
@@ -2514,9 +2442,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
CURSOR_COEFF_MASK);
- val |= ddi_translations[level].dw4_scaling;
+ val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
+ val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
+ val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
}
+
+ /* Program PORT_TX_DW7 */
+ val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
+ val &= ~N_SCALAR_MASK;
+ val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
+ I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
}
static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
@@ -2581,7 +2517,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
/* 5. Program swing and de-emphasis */
- icl_ddi_combo_vswing_program(dev_priv, level, port, type);
+ icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
/* 6. Set training enable to trigger update */
val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e94faa0..936fcfb 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -304,9 +304,11 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
static int icl_max_source_rate(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
enum port port = dig_port->base.port;
- if (port == PORT_B)
+ if (intel_port_is_combophy(dev_priv, port) &&
+ !intel_dp_is_edp(intel_dp))
return 540000;
return 810000;
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: combo port vswing programming changes per BSPEC (rev4)
2018-11-30 22:58 [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC clinton.a.taylor
` (8 preceding siblings ...)
2018-12-05 0:09 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2018-12-11 21:38 ` Patchwork
2018-12-11 21:53 ` ✓ Fi.CI.BAT: success " Patchwork
` (3 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2018-12-11 21:38 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: combo port vswing programming changes per BSPEC (rev4)
URL : https://patchwork.freedesktop.org/series/53340/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
cc1e8bb822a1 drm/i915/icl: combo port vswing programming changes per BSPEC
-:256: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#256: FILE: drivers/gpu/drm/i915/intel_ddi.c:857:
+ icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
+ 540000, &n_entries);
total: 0 errors, 0 warnings, 1 checks, 341 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/icl: combo port vswing programming changes per BSPEC (rev4)
2018-11-30 22:58 [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC clinton.a.taylor
` (9 preceding siblings ...)
2018-12-11 21:38 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: combo port vswing programming changes per BSPEC (rev4) Patchwork
@ 2018-12-11 21:53 ` Patchwork
2018-12-12 1:51 ` ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2018-12-11 21:53 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: combo port vswing programming changes per BSPEC (rev4)
URL : https://patchwork.freedesktop.org/series/53340/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296 -> Patchwork_11072
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/53340/revisions/4/mbox/
Known issues
------------
Here are the changes found in Patchwork_11072 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160: PASS -> DMESG-FAIL [fdo#108735]
[fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
Participating hosts (48 -> 44)
------------------------------
Additional (1): fi-byt-j1900
Missing (5): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-ctg-p8600
Build changes
-------------
* Linux: CI_DRM_5296 -> Patchwork_11072
CI_DRM_5296: 70751bd8a3f27b035d203ecafcad452f4d7c2c15 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4745: 3b52e8a5809a4e860350c59476a456745cd9fee0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11072: cc1e8bb822a1ecae4953f8f6a45517f59815f851 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cc1e8bb822a1 drm/i915/icl: combo port vswing programming changes per BSPEC
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11072/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/icl: combo port vswing programming changes per BSPEC (rev4)
2018-11-30 22:58 [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC clinton.a.taylor
` (10 preceding siblings ...)
2018-12-11 21:53 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-12-12 1:51 ` Patchwork
2018-12-17 23:13 ` ✓ Fi.CI.BAT: success for drm/i915/icl: combo port vswing programming changes per BSPEC (rev5) Patchwork
2018-12-18 0:35 ` ✓ Fi.CI.IGT: " Patchwork
13 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2018-12-12 1:51 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: combo port vswing programming changes per BSPEC (rev4)
URL : https://patchwork.freedesktop.org/series/53340/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5296_full -> Patchwork_11072_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_11072_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11072_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_11072_full:
### IGT changes ###
#### Warnings ####
* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: PASS -> SKIP
* igt@tools_test@tools_test:
- shard-skl: SKIP -> PASS
Known issues
------------
Here are the changes found in Patchwork_11072_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries_display_off:
- shard-skl: PASS -> INCOMPLETE [fdo#104108]
* igt@i915_selftest@live_contexts:
- {shard-iclb}: NOTRUN -> DMESG-FAIL [fdo#108569]
* igt@kms_atomic_transition@plane-toggle-modeset-transition:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] +12
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- {shard-iclb}: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-glk: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_chv_cursor_fail@pipe-b-256x256-right-edge:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +5
* igt@kms_color@pipe-a-ctm-max:
- shard-apl: PASS -> FAIL [fdo#108147]
* igt@kms_color@pipe-a-degamma:
- shard-apl: PASS -> FAIL [fdo#104782] / [fdo#108145]
* igt@kms_color@pipe-b-degamma:
- shard-apl: PASS -> FAIL [fdo#104782]
* igt@kms_cursor_crc@cursor-128x128-onscreen:
- shard-apl: PASS -> DMESG-FAIL [fdo#103232] / [fdo#103558] / [fdo#105602]
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232] +8
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
- shard-apl: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
- shard-apl: PASS -> DMESG-FAIL [fdo#103167] / [fdo#103558] / [fdo#105602]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-glk: PASS -> FAIL [fdo#103167] +4
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: PASS -> FAIL [fdo#103167] / [fdo#105682]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu:
- {shard-iclb}: PASS -> DMESG-FAIL [fdo#107724] +4
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt:
- {shard-iclb}: PASS -> FAIL [fdo#103167] +3
* igt@kms_plane@plane-position-covered-pipe-a-planes:
- shard-apl: PASS -> FAIL [fdo#103166] +3
* igt@kms_plane@plane-position-covered-pipe-b-planes:
- shard-glk: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-skl: NOTRUN -> FAIL [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
- {shard-iclb}: PASS -> FAIL [fdo#103166]
* igt@kms_psr@no_drrs:
- {shard-iclb}: PASS -> FAIL [fdo#108341]
* igt@kms_sysfs_edid_timing:
- shard-skl: NOTRUN -> FAIL [fdo#100047]
* igt@kms_vblank@pipe-c-query-busy:
- shard-apl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +15
* igt@pm_rpm@gem-execbuf-stress:
- {shard-iclb}: PASS -> DMESG-WARN [fdo#108654]
#### Possible fixes ####
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-skl: TIMEOUT [fdo#108039] -> PASS
* igt@kms_color@pipe-b-ctm-negative:
- shard-skl: FAIL [fdo#107361] -> PASS
* igt@kms_color@pipe-c-degamma:
- shard-apl: FAIL [fdo#104782] -> PASS
* igt@kms_cursor_crc@cursor-64x21-sliding:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled:
- shard-skl: FAIL [fdo#103184] -> PASS
* igt@kms_draw_crc@draw-method-rgb565-render-ytiled:
- {shard-iclb}: WARN [fdo#108336] -> PASS +1
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: FAIL [fdo#103833] / [fdo#105681] -> PASS
* igt@kms_flip@dpms-off-confusion:
- {shard-iclb}: DMESG-WARN [fdo#107724] -> PASS +17
* igt@kms_flip_tiling@flip-changes-tiling:
- {shard-iclb}: DMESG-WARN [fdo#107724] / [fdo#108336] -> PASS +6
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite:
- {shard-iclb}: DMESG-FAIL [fdo#107724] -> PASS +4
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- {shard-iclb}: FAIL [fdo#103167] -> PASS +1
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render:
- shard-glk: FAIL [fdo#103167] -> PASS +1
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS
* igt@kms_plane@pixel-format-pipe-c-planes:
- shard-apl: FAIL [fdo#103166] -> PASS +1
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: FAIL [fdo#107815] / [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: FAIL [fdo#107815] -> PASS +1
* {igt@kms_rotation_crc@multiplane-rotation-cropping-top}:
- shard-kbl: DMESG-FAIL [fdo#108950] -> PASS
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-glk: INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- {shard-iclb}: INCOMPLETE [fdo#107713] -> PASS
* igt@perf@blocking:
- shard-hsw: FAIL [fdo#102252] -> PASS
* igt@sw_sync@sync_busy_fork_unixsocket:
- {shard-iclb}: INCOMPLETE [fdo#108889] -> PASS
#### Warnings ####
* igt@kms_cursor_crc@cursor-128x128-random:
- {shard-iclb}: DMESG-WARN [fdo#107724] / [fdo#108336] -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-64x64-sliding:
- shard-apl: FAIL [fdo#103232] -> DMESG-FAIL [fdo#103232] / [fdo#103558] / [fdo#105602]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc:
- {shard-iclb}: DMESG-FAIL [fdo#107724] -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render:
- {shard-iclb}: DMESG-WARN [fdo#107724] / [fdo#108336] -> FAIL [fdo#103167]
* {igt@kms_plane@pixel-format-pipe-a-planes-source-clamping}:
- {shard-iclb}: DMESG-WARN [fdo#107724] / [fdo#108336] -> FAIL [fdo#108948]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#102252]: https://bugs.freedesktop.org/show_bug.cgi?id=102252
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#103833]: https://bugs.freedesktop.org/show_bug.cgi?id=103833
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#105681]: https://bugs.freedesktop.org/show_bug.cgi?id=105681
[fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
[fdo#107361]: https://bugs.freedesktop.org/show_bug.cgi?id=107361
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108039]: https://bugs.freedesktop.org/show_bug.cgi?id=108039
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
[fdo#108889]: https://bugs.freedesktop.org/show_bug.cgi?id=108889
[fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
[fdo#108950]: https://bugs.freedesktop.org/show_bug.cgi?id=108950
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_5296 -> Patchwork_11072
CI_DRM_5296: 70751bd8a3f27b035d203ecafcad452f4d7c2c15 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4745: 3b52e8a5809a4e860350c59476a456745cd9fee0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11072: cc1e8bb822a1ecae4953f8f6a45517f59815f851 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11072/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v4] drm/i915/icl: combo port vswing programming changes per BSPEC
2018-12-11 21:31 ` [PATCH v4] " clinton.a.taylor
@ 2018-12-17 15:23 ` Imre Deak
0 siblings, 0 replies; 26+ messages in thread
From: Imre Deak @ 2018-12-17 15:23 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: Intel-gfx, Rodrigo Vivi
On Tue, Dec 11, 2018 at 01:31:12PM -0800, clinton.a.taylor@intel.com wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> In August 2018 the BSPEC changed the ICL port programming sequence to
> closely resemble earlier gen programming sequence. Restrict combo phy to
> HBR max rate unless eDP panel is connected to port.
>
> v2: remove debug code that Imre found
> v3: simplify translation table if-else
> v4: edp translation table now based on link rate and low_swing
> BSpec: 21257
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 +
> drivers/gpu/drm/i915/intel_ddi.c | 240 ++++++++++++++-------------------------
> drivers/gpu/drm/i915/intel_dp.c | 4 +-
> 3 files changed, 95 insertions(+), 153 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0a7d605..29acdb9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1866,6 +1866,10 @@ enum i915_power_well_id {
>
> #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
> #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
> +#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
> +#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
> +#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
> +#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
> #define N_SCALAR(x) ((x) << 24)
> #define N_SCALAR_MASK (0x7F << 24)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index f3e1d6a..33bf77b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -494,103 +494,58 @@ struct cnl_ddi_buf_trans {
> { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
> };
>
> -struct icl_combo_phy_ddi_buf_trans {
> - u32 dw2_swing_select;
> - u32 dw2_swing_scalar;
> - u32 dw4_scaling;
> -};
> -
> -/* Voltage Swing Programming for VccIO 0.85V for DP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
> - /* Voltage mV db */
> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> - { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
> - { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
> - { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
> - { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
> - { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> -};
> -
> -/* FIXME - After table is updated in Bspec */
> -/* Voltage Swing Programming for VccIO 0.85V for eDP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
> - /* Voltage mV db */
> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> -};
> -
> -/* Voltage Swing Programming for VccIO 0.95V for DP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
> - /* Voltage mV db */
> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
> - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
> - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
> - { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
> - { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> +/* icl_combo_phy_ddi_translations */
> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
> + /* NT mV Trans mV db */
> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 705 0.6 */
you missed my comment for the previous version ^700
> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> };
>
> -/* FIXME - After table is updated in Bspec */
> -/* Voltage Swing Programming for VccIO 0.95V for eDP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
> - /* Voltage mV db */
> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
> + /* NT mV Trans mV db */
> + { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
> + { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
> + { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
> + { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
> + { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
> + { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
> + { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
> + { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
> + { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
> + { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> };
>
> -/* Voltage Swing Programming for VccIO 1.05V for DP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
> - /* Voltage mV db */
> - { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
> - { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
> - { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
> - { 0x2, 0x98, 0x900F }, /* 400 9.5 */
> - { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
> - { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
> - { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
> - { 0x5, 0x71, 0x0018 }, /* 800 0.0 */
> - { 0x5, 0x71, 0x3015 }, /* 800 3.5 */
> - { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
> + /* NT mV Trans mV db */
> + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
> + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
> + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
> + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
> + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> };
>
> -/* FIXME - After table is updated in Bspec */
> -/* Voltage Swing Programming for VccIO 1.05V for eDP */
> -static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
> - /* Voltage mV db */
> - { 0x0, 0x00, 0x00 }, /* 200 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 200 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 200 6.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 250 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 250 4.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 0.0 */
> - { 0x0, 0x00, 0x00 }, /* 300 1.5 */
> - { 0x0, 0x00, 0x00 }, /* 350 0.0 */
> +static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
> + /* NT mV Trans mV db */
> + { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
> + { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
> + { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
> + { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
> + { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
> };
>
> struct icl_mg_phy_ddi_buf_trans {
> @@ -871,43 +826,23 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries)
> }
> }
>
> -static const struct icl_combo_phy_ddi_buf_trans *
> +static const struct cnl_ddi_buf_trans *
> icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
> - int type, int *n_entries)
> + int type, int rate, int *n_entries)
> {
> - u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
> -
> - if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
> - switch (voltage) {
> - case VOLTAGE_INFO_0_85V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
> - return icl_combo_phy_ddi_translations_edp_0_85V;
> - case VOLTAGE_INFO_0_95V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
> - return icl_combo_phy_ddi_translations_edp_0_95V;
> - case VOLTAGE_INFO_1_05V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
> - return icl_combo_phy_ddi_translations_edp_1_05V;
> - default:
> - MISSING_CASE(voltage);
> - return NULL;
> - }
> - } else {
> - switch (voltage) {
> - case VOLTAGE_INFO_0_85V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
> - return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
> - case VOLTAGE_INFO_0_95V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
> - return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
> - case VOLTAGE_INFO_1_05V:
> - *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
> - return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
> - default:
> - MISSING_CASE(voltage);
> - return NULL;
> - }
> + if (type == INTEL_OUTPUT_HDMI) {
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> + return icl_combo_phy_ddi_translations_hdmi;
> + } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
> + return icl_combo_phy_ddi_translations_edp_hbr3;
> + } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
> + return icl_combo_phy_ddi_translations_edp_hbr2;
> }
> +
> + *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
> + return icl_combo_phy_ddi_translations_dp_hbr2;
> }
>
> static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
> @@ -918,8 +853,8 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
>
> if (IS_ICELAKE(dev_priv)) {
> if (intel_port_is_combophy(dev_priv, port))
> - icl_get_combo_buf_trans(dev_priv, port,
> - INTEL_OUTPUT_HDMI, &n_entries);
> + icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
> + 540000, &n_entries);
I take 540000 is completely arbitrary?:) Just pass 0. As a follow-up we
should unify the buf_trans table selection for all DDI platforms, so
here we'll just call a function something like icl_get_buf_trans_hdmi(),
without the need to pass any rate.
Also there is an alignment issue here reported by checkpatch.
> else
> n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
> default_entry = n_entries - 1;
> @@ -2275,13 +2210,16 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
> u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
This can be moved local to the only block using it.
> enum port port = encoder->port;
> int n_entries;
> + int rate = 0;
No need for a separate var for this, rather ..
>
> if (IS_ICELAKE(dev_priv)) {
> + rate = intel_dp->link_rate;
> if (intel_port_is_combophy(dev_priv, port))
> icl_get_combo_buf_trans(dev_priv, port, encoder->type,
> - &n_entries);
> + rate, &n_entries);
.. pass here intel_dp->link_rate directly.
With the above fixed, the patch looks ok:
Reviewed-by: Imre Deak <imre.deak@intel.com>
> else
> n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
> } else if (IS_CANNONLAKE(dev_priv)) {
> @@ -2462,14 +2400,15 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
> }
>
> static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> - u32 level, enum port port, int type)
> + u32 level, enum port port, int type,
> + int rate)
> {
> - const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
> + const struct cnl_ddi_buf_trans *ddi_translations = NULL;
> u32 n_entries, val;
> int ln;
>
> ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
> - &n_entries);
> + rate, &n_entries);
> if (!ddi_translations)
> return;
>
> @@ -2478,34 +2417,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> level = n_entries - 1;
> }
>
> - /* Set PORT_TX_DW5 Rterm Sel to 110b. */
> + /* Set PORT_TX_DW5 */
> val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> - val &= ~RTERM_SELECT_MASK;
> + val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
> + TAP2_DISABLE | TAP3_DISABLE);
> + val |= SCALING_MODE_SEL(0x2);
> val |= RTERM_SELECT(0x6);
> - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
> -
> - /* Program PORT_TX_DW5 */
> - val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> - /* Set DisableTap2 and DisableTap3 if MIPI DSI
> - * Clear DisableTap2 and DisableTap3 for all other Ports
> - */
> - if (type == INTEL_OUTPUT_DSI) {
> - val |= TAP2_DISABLE;
> - val |= TAP3_DISABLE;
> - } else {
> - val &= ~TAP2_DISABLE;
> - val &= ~TAP3_DISABLE;
> - }
> + val |= TAP3_DISABLE;
> I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
>
> /* Program PORT_TX_DW2 */
> val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> RCOMP_SCALAR_MASK);
> - val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
> - val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
> + val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
> + val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
> /* Program Rcomp scalar for every table entry */
> - val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
> + val |= RCOMP_SCALAR(0x98);
> I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
>
> /* Program PORT_TX_DW4 */
> @@ -2514,9 +2442,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
> val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> CURSOR_COEFF_MASK);
> - val |= ddi_translations[level].dw4_scaling;
> + val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
> + val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
> + val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
> I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
> }
> +
> + /* Program PORT_TX_DW7 */
> + val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
> + val &= ~N_SCALAR_MASK;
> + val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
> + I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
> }
>
> static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> @@ -2581,7 +2517,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
>
> /* 5. Program swing and de-emphasis */
> - icl_ddi_combo_vswing_program(dev_priv, level, port, type);
> + icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
>
> /* 6. Set training enable to trigger update */
> val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index e94faa0..936fcfb 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -304,9 +304,11 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
> static int icl_max_source_rate(struct intel_dp *intel_dp)
> {
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> enum port port = dig_port->base.port;
>
> - if (port == PORT_B)
> + if (intel_port_is_combophy(dev_priv, port) &&
> + !intel_dp_is_edp(intel_dp))
> return 540000;
>
> return 810000;
> --
> 1.9.1
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v5] drm/i915/icl: combo port vswing programming changes per BSPEC
2018-12-04 23:41 ` [PATCH v3] " clinton.a.taylor
2018-12-05 16:32 ` Imre Deak
2018-12-11 21:31 ` [PATCH v4] " clinton.a.taylor
@ 2018-12-17 22:13 ` clinton.a.taylor
2 siblings, 0 replies; 26+ messages in thread
From: clinton.a.taylor @ 2018-12-17 22:13 UTC (permalink / raw)
To: Intel-gfx; +Cc: Rodrigo Vivi
From: Clint Taylor <clinton.a.taylor@intel.com>
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence. Restrict combo phy to
HBR max rate unless eDP panel is connected to port.
v2: remove debug code that Imre found
v3: simplify translation table if-else
v4: edp translation table now based on link rate and low_swing
v5: Misc review comments + r-b
BSpec: 21257
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 +
drivers/gpu/drm/i915/intel_ddi.c | 238 ++++++++++++++-------------------------
drivers/gpu/drm/i915/intel_dp.c | 4 +-
3 files changed, 93 insertions(+), 153 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0796526..02af9b5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1884,6 +1884,10 @@ enum i915_power_well_id {
#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7))
#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7))
+#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
+#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
+#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
+#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
#define N_SCALAR(x) ((x) << 24)
#define N_SCALAR_MASK (0x7F << 24)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 92c0bf7..dfd3582 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -494,103 +494,58 @@ struct cnl_ddi_buf_trans {
{ 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
};
-struct icl_combo_phy_ddi_buf_trans {
- u32 dw2_swing_select;
- u32 dw2_swing_scalar;
- u32 dw4_scaling;
-};
-
-/* Voltage Swing Programming for VccIO 0.85V for DP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = {
- /* Voltage mV db */
- { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
- { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
- { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
- { 0x2, 0x98, 0x900F }, /* 400 9.5 */
- { 0xB, 0x70, 0x0018 }, /* 600 0.0 */
- { 0xB, 0x70, 0x3015 }, /* 600 3.5 */
- { 0xB, 0x70, 0x6012 }, /* 600 6.0 */
- { 0x5, 0x00, 0x0018 }, /* 800 0.0 */
- { 0x5, 0x00, 0x3015 }, /* 800 3.5 */
- { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
-};
-
-/* FIXME - After table is updated in Bspec */
-/* Voltage Swing Programming for VccIO 0.85V for eDP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
- /* Voltage mV db */
- { 0x0, 0x00, 0x00 }, /* 200 0.0 */
- { 0x0, 0x00, 0x00 }, /* 200 1.5 */
- { 0x0, 0x00, 0x00 }, /* 200 4.0 */
- { 0x0, 0x00, 0x00 }, /* 200 6.0 */
- { 0x0, 0x00, 0x00 }, /* 250 0.0 */
- { 0x0, 0x00, 0x00 }, /* 250 1.5 */
- { 0x0, 0x00, 0x00 }, /* 250 4.0 */
- { 0x0, 0x00, 0x00 }, /* 300 0.0 */
- { 0x0, 0x00, 0x00 }, /* 300 1.5 */
- { 0x0, 0x00, 0x00 }, /* 350 0.0 */
-};
-
-/* Voltage Swing Programming for VccIO 0.95V for DP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
- /* Voltage mV db */
- { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
- { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
- { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
- { 0x2, 0x98, 0x900F }, /* 400 9.5 */
- { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
- { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
- { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
- { 0x5, 0x76, 0x0018 }, /* 800 0.0 */
- { 0x5, 0x76, 0x3015 }, /* 800 3.5 */
- { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
+/* icl_combo_phy_ddi_translations */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
+ { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
+ { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
+ { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
};
-/* FIXME - After table is updated in Bspec */
-/* Voltage Swing Programming for VccIO 0.95V for eDP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = {
- /* Voltage mV db */
- { 0x0, 0x00, 0x00 }, /* 200 0.0 */
- { 0x0, 0x00, 0x00 }, /* 200 1.5 */
- { 0x0, 0x00, 0x00 }, /* 200 4.0 */
- { 0x0, 0x00, 0x00 }, /* 200 6.0 */
- { 0x0, 0x00, 0x00 }, /* 250 0.0 */
- { 0x0, 0x00, 0x00 }, /* 250 1.5 */
- { 0x0, 0x00, 0x00 }, /* 250 4.0 */
- { 0x0, 0x00, 0x00 }, /* 300 0.0 */
- { 0x0, 0x00, 0x00 }, /* 300 1.5 */
- { 0x0, 0x00, 0x00 }, /* 350 0.0 */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
+ /* NT mV Trans mV db */
+ { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
+ { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
+ { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
+ { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
+ { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
+ { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
+ { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
+ { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
+ { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
+ { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
};
-/* Voltage Swing Programming for VccIO 1.05V for DP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = {
- /* Voltage mV db */
- { 0x2, 0x98, 0x0018 }, /* 400 0.0 */
- { 0x2, 0x98, 0x3015 }, /* 400 3.5 */
- { 0x2, 0x98, 0x6012 }, /* 400 6.0 */
- { 0x2, 0x98, 0x900F }, /* 400 9.5 */
- { 0x4, 0x98, 0x0018 }, /* 600 0.0 */
- { 0x4, 0x98, 0x3015 }, /* 600 3.5 */
- { 0x4, 0x98, 0x6012 }, /* 600 6.0 */
- { 0x5, 0x71, 0x0018 }, /* 800 0.0 */
- { 0x5, 0x71, 0x3015 }, /* 800 3.5 */
- { 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
+ { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
+ { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
+ { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
+ { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
+ { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
+ { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
+ { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
};
-/* FIXME - After table is updated in Bspec */
-/* Voltage Swing Programming for VccIO 1.05V for eDP */
-static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = {
- /* Voltage mV db */
- { 0x0, 0x00, 0x00 }, /* 200 0.0 */
- { 0x0, 0x00, 0x00 }, /* 200 1.5 */
- { 0x0, 0x00, 0x00 }, /* 200 4.0 */
- { 0x0, 0x00, 0x00 }, /* 200 6.0 */
- { 0x0, 0x00, 0x00 }, /* 250 0.0 */
- { 0x0, 0x00, 0x00 }, /* 250 1.5 */
- { 0x0, 0x00, 0x00 }, /* 250 4.0 */
- { 0x0, 0x00, 0x00 }, /* 300 0.0 */
- { 0x0, 0x00, 0x00 }, /* 300 1.5 */
- { 0x0, 0x00, 0x00 }, /* 350 0.0 */
+static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
+ /* NT mV Trans mV db */
+ { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
+ { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
+ { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
+ { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
+ { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
+ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
+ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
};
struct icl_mg_phy_ddi_buf_trans {
@@ -871,43 +826,23 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries)
}
}
-static const struct icl_combo_phy_ddi_buf_trans *
+static const struct cnl_ddi_buf_trans *
icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
- int type, int *n_entries)
+ int type, int rate, int *n_entries)
{
- u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK;
-
- if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
- switch (voltage) {
- case VOLTAGE_INFO_0_85V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V);
- return icl_combo_phy_ddi_translations_edp_0_85V;
- case VOLTAGE_INFO_0_95V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V);
- return icl_combo_phy_ddi_translations_edp_0_95V;
- case VOLTAGE_INFO_1_05V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
- return icl_combo_phy_ddi_translations_edp_1_05V;
- default:
- MISSING_CASE(voltage);
- return NULL;
- }
- } else {
- switch (voltage) {
- case VOLTAGE_INFO_0_85V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
- return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
- case VOLTAGE_INFO_0_95V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
- return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
- case VOLTAGE_INFO_1_05V:
- *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
- return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
- default:
- MISSING_CASE(voltage);
- return NULL;
- }
+ if (type == INTEL_OUTPUT_HDMI) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+ return icl_combo_phy_ddi_translations_hdmi;
+ } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
+ return icl_combo_phy_ddi_translations_edp_hbr3;
+ } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
+ return icl_combo_phy_ddi_translations_edp_hbr2;
}
+
+ *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
+ return icl_combo_phy_ddi_translations_dp_hbr2;
}
static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
@@ -918,8 +853,8 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
if (IS_ICELAKE(dev_priv)) {
if (intel_port_is_combophy(dev_priv, port))
- icl_get_combo_buf_trans(dev_priv, port,
- INTEL_OUTPUT_HDMI, &n_entries);
+ icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
+ 0, &n_entries);
else
n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
default_entry = n_entries - 1;
@@ -2275,13 +2210,14 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
enum port port = encoder->port;
int n_entries;
if (IS_ICELAKE(dev_priv)) {
if (intel_port_is_combophy(dev_priv, port))
icl_get_combo_buf_trans(dev_priv, port, encoder->type,
- &n_entries);
+ intel_dp->link_rate, &n_entries);
else
n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
} else if (IS_CANNONLAKE(dev_priv)) {
@@ -2462,14 +2398,15 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
}
static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
- u32 level, enum port port, int type)
+ u32 level, enum port port, int type,
+ int rate)
{
- const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL;
+ const struct cnl_ddi_buf_trans *ddi_translations = NULL;
u32 n_entries, val;
int ln;
ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
- &n_entries);
+ rate, &n_entries);
if (!ddi_translations)
return;
@@ -2478,34 +2415,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
level = n_entries - 1;
}
- /* Set PORT_TX_DW5 Rterm Sel to 110b. */
+ /* Set PORT_TX_DW5 */
val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
- val &= ~RTERM_SELECT_MASK;
+ val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
+ TAP2_DISABLE | TAP3_DISABLE);
+ val |= SCALING_MODE_SEL(0x2);
val |= RTERM_SELECT(0x6);
- I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
-
- /* Program PORT_TX_DW5 */
- val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
- /* Set DisableTap2 and DisableTap3 if MIPI DSI
- * Clear DisableTap2 and DisableTap3 for all other Ports
- */
- if (type == INTEL_OUTPUT_DSI) {
- val |= TAP2_DISABLE;
- val |= TAP3_DISABLE;
- } else {
- val &= ~TAP2_DISABLE;
- val &= ~TAP3_DISABLE;
- }
+ val |= TAP3_DISABLE;
I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
/* Program PORT_TX_DW2 */
val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
RCOMP_SCALAR_MASK);
- val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select);
- val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select);
+ val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
+ val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
/* Program Rcomp scalar for every table entry */
- val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar);
+ val |= RCOMP_SCALAR(0x98);
I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
/* Program PORT_TX_DW4 */
@@ -2514,9 +2440,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
CURSOR_COEFF_MASK);
- val |= ddi_translations[level].dw4_scaling;
+ val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
+ val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
+ val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
}
+
+ /* Program PORT_TX_DW7 */
+ val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
+ val &= ~N_SCALAR_MASK;
+ val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
+ I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
}
static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
@@ -2581,7 +2515,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
/* 5. Program swing and de-emphasis */
- icl_ddi_combo_vswing_program(dev_priv, level, port, type);
+ icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
/* 6. Set training enable to trigger update */
val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 62484e1..9b76c23 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -304,9 +304,11 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
static int icl_max_source_rate(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
enum port port = dig_port->base.port;
- if (port == PORT_B)
+ if (intel_port_is_combophy(dev_priv, port) &&
+ !intel_dp_is_edp(intel_dp))
return 540000;
return 810000;
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/icl: combo port vswing programming changes per BSPEC (rev5)
2018-11-30 22:58 [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC clinton.a.taylor
` (11 preceding siblings ...)
2018-12-12 1:51 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-12-17 23:13 ` Patchwork
2018-12-18 0:35 ` ✓ Fi.CI.IGT: " Patchwork
13 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2018-12-17 23:13 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: combo port vswing programming changes per BSPEC (rev5)
URL : https://patchwork.freedesktop.org/series/53340/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5325 -> Patchwork_11110
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_11110 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11110, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/53340/revisions/5/mbox/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_11110:
### IGT changes ###
#### Warnings ####
* igt@kms_flip@basic-flip-vs-dpms:
- fi-skl-6770hq: PASS -> SKIP +36
Known issues
------------
Here are the changes found in Patchwork_11110 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_hangcheck:
- fi-bwr-2160: PASS -> DMESG-FAIL [fdo#108735]
#### Possible fixes ####
* igt@gem_mmap_gtt@basic-small-copy-xy:
- fi-glk-dsi: INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS
* igt@kms_flip@basic-flip-vs-dpms:
- fi-icl-u3: DMESG-WARN [fdo#108924] / [fdo#109044] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
- fi-byt-clapper: FAIL [fdo#107362] -> PASS
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#108735]: https://bugs.freedesktop.org/show_bug.cgi?id=108735
[fdo#108924]: https://bugs.freedesktop.org/show_bug.cgi?id=108924
[fdo#109044]: https://bugs.freedesktop.org/show_bug.cgi?id=109044
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (49 -> 45)
------------------------------
Additional (1): fi-cfl-8109u
Missing (5): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-icl-y
Build changes
-------------
* Linux: CI_DRM_5325 -> Patchwork_11110
CI_DRM_5325: d1085cddae920b9a0c326e3cc3e342cfee14aed2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4749: 270da20849db4d170db09673c6b67712c90ec9fe @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11110: 2a15cd7c794ae90e2d6de66015665e9a985a2467 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2a15cd7c794a drm/i915/icl: combo port vswing programming changes per BSPEC
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11110/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/icl: combo port vswing programming changes per BSPEC (rev5)
2018-11-30 22:58 [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC clinton.a.taylor
` (12 preceding siblings ...)
2018-12-17 23:13 ` ✓ Fi.CI.BAT: success for drm/i915/icl: combo port vswing programming changes per BSPEC (rev5) Patchwork
@ 2018-12-18 0:35 ` Patchwork
2018-12-18 14:06 ` Imre Deak
13 siblings, 1 reply; 26+ messages in thread
From: Patchwork @ 2018-12-18 0:35 UTC (permalink / raw)
To: clinton.a.taylor; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: combo port vswing programming changes per BSPEC (rev5)
URL : https://patchwork.freedesktop.org/series/53340/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5325_full -> Patchwork_11110_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_11110_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11110_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_11110_full:
### IGT changes ###
#### Warnings ####
* igt@pm_rc6_residency@rc6-accuracy:
- shard-snb: SKIP -> PASS
Known issues
------------
Here are the changes found in Patchwork_11110_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_schedule@pi-ringfull-blt:
- shard-skl: NOTRUN -> FAIL [fdo#103158] +1
* igt@gem_exec_schedule@pi-ringfull-vebox:
- shard-iclb: NOTRUN -> FAIL [fdo#103158]
* igt@gem_softpin@noreloc-s3:
- shard-iclb: PASS -> INCOMPLETE [fdo#107713]
* igt@gem_userptr_blits@readonly-unsync:
- shard-skl: NOTRUN -> TIMEOUT [fdo#108887]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-glk: PASS -> FAIL [fdo#108145]
* igt@kms_cursor_crc@cursor-128x42-onscreen:
- shard-iclb: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-256x256-sliding:
- shard-glk: PASS -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-64x21-random:
- shard-apl: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x64-offscreen:
- shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +1
* igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-xtiled:
- shard-iclb: PASS -> WARN [fdo#108336]
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-kbl: PASS -> FAIL [fdo#102887] / [fdo#105363]
* igt@kms_flip@flip-vs-rmfb-interruptible:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-iclb: NOTRUN -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
- shard-apl: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#106978] / [fdo#107773]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
- shard-iclb: PASS -> FAIL [fdo#103167] +2
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885]
* igt@kms_plane@pixel-format-pipe-c-planes:
- shard-apl: PASS -> FAIL [fdo#103166]
- shard-glk: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb:
- shard-iclb: PASS -> DMESG-FAIL [fdo#107724]
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-apl: PASS -> FAIL [fdo#108145]
* igt@kms_psr@primary_render:
- shard-iclb: PASS -> DMESG-WARN [fdo#107724] +3
* igt@kms_setmode@basic:
- shard-kbl: PASS -> FAIL [fdo#99912]
* igt@kms_sysfs_edid_timing:
- shard-skl: NOTRUN -> FAIL [fdo#100047]
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- shard-kbl: PASS -> INCOMPLETE [fdo#103665]
* {igt@runner@aborted}:
- shard-iclb: NOTRUN -> FAIL [fdo#108866]
#### Possible fixes ####
* igt@gem_eio@in-flight-contexts-immediate:
- shard-glk: FAIL [fdo#107799] -> PASS
* igt@gem_workarounds@suspend-resume-fd:
- shard-iclb: INCOMPLETE [fdo#107713] -> PASS +1
* igt@kms_cursor_crc@cursor-256x256-onscreen:
- shard-skl: FAIL [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-256x256-random:
- shard-glk: FAIL [fdo#103232] -> PASS +2
- shard-apl: FAIL [fdo#103232] -> PASS +3
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: FAIL [fdo#105363] -> PASS
* igt@kms_flip@modeset-vs-vblank-race-interruptible:
- shard-apl: FAIL [fdo#103060] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-apl: FAIL [fdo#103167] -> PASS +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
- shard-glk: FAIL [fdo#103167] -> PASS +2
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-iclb: FAIL [fdo#103167] -> PASS +6
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
- shard-skl: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-apl: FAIL [fdo#108948] -> PASS
* igt@kms_plane@plane-position-covered-pipe-c-planes:
- shard-glk: FAIL [fdo#103166] -> PASS +1
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: FAIL [fdo#107815] / [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: FAIL [fdo#107815] -> PASS
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-apl: FAIL [fdo#103166] -> PASS +2
- shard-iclb: FAIL [fdo#103166] -> PASS
* igt@pm_rpm@debugfs-read:
- shard-iclb: DMESG-WARN [fdo#108654] -> PASS
* igt@pm_rpm@dpms-lpsp:
- shard-iclb: DMESG-WARN [fdo#107724] -> PASS
* igt@pm_rpm@gem-execbuf-stress-extra-wait:
- shard-skl: INCOMPLETE [fdo#107803] / [fdo#107807] -> PASS
* igt@pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-iclb: INCOMPLETE [fdo#108840] -> SKIP
#### Warnings ####
* igt@i915_selftest@live_contexts:
- shard-iclb: DMESG-FAIL [fdo#108569] -> INCOMPLETE [fdo#108315]
* igt@kms_ccs@pipe-a-crc-primary-basic:
- shard-iclb: FAIL [fdo#107725] -> DMESG-WARN [fdo#107724] / [fdo#108336]
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-kbl: DMESG-WARN [fdo#105604] -> DMESG-FAIL [fdo#108950]
- shard-glk: DMESG-WARN [fdo#105763] / [fdo#106538] -> DMESG-FAIL [fdo#105763] / [fdo#106538]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105604]: https://bugs.freedesktop.org/show_bug.cgi?id=105604
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
[fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
[fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107799]: https://bugs.freedesktop.org/show_bug.cgi?id=107799
[fdo#107803]: https://bugs.freedesktop.org/show_bug.cgi?id=107803
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108315]: https://bugs.freedesktop.org/show_bug.cgi?id=108315
[fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#108866]: https://bugs.freedesktop.org/show_bug.cgi?id=108866
[fdo#108887]: https://bugs.freedesktop.org/show_bug.cgi?id=108887
[fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
[fdo#108950]: https://bugs.freedesktop.org/show_bug.cgi?id=108950
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_5325 -> Patchwork_11110
CI_DRM_5325: d1085cddae920b9a0c326e3cc3e342cfee14aed2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4749: 270da20849db4d170db09673c6b67712c90ec9fe @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11110: 2a15cd7c794ae90e2d6de66015665e9a985a2467 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11110/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: ✓ Fi.CI.IGT: success for drm/i915/icl: combo port vswing programming changes per BSPEC (rev5)
2018-12-18 0:35 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-12-18 14:06 ` Imre Deak
0 siblings, 0 replies; 26+ messages in thread
From: Imre Deak @ 2018-12-18 14:06 UTC (permalink / raw)
To: intel-gfx, Clint A Taylor, Ville Syrjälä
On Tue, Dec 18, 2018 at 12:35:30AM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/icl: combo port vswing programming changes per BSPEC (rev5)
> URL : https://patchwork.freedesktop.org/series/53340/
> State : success
Pushed to -dinq, thanks for the patch and review.
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5325_full -> Patchwork_11110_full
> ====================================================
>
> Summary
> -------
>
> **WARNING**
>
> Minor unknown changes coming with Patchwork_11110_full need to be verified
> manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_11110_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_11110_full:
>
> ### IGT changes ###
>
> #### Warnings ####
>
> * igt@pm_rc6_residency@rc6-accuracy:
> - shard-snb: SKIP -> PASS
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_11110_full that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_exec_schedule@pi-ringfull-blt:
> - shard-skl: NOTRUN -> FAIL [fdo#103158] +1
>
> * igt@gem_exec_schedule@pi-ringfull-vebox:
> - shard-iclb: NOTRUN -> FAIL [fdo#103158]
>
> * igt@gem_softpin@noreloc-s3:
> - shard-iclb: PASS -> INCOMPLETE [fdo#107713]
>
> * igt@gem_userptr_blits@readonly-unsync:
> - shard-skl: NOTRUN -> TIMEOUT [fdo#108887]
>
> * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
> - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
>
> * igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
> - shard-glk: PASS -> FAIL [fdo#108145]
>
> * igt@kms_cursor_crc@cursor-128x42-onscreen:
> - shard-iclb: NOTRUN -> FAIL [fdo#103232]
>
> * igt@kms_cursor_crc@cursor-256x256-sliding:
> - shard-glk: PASS -> FAIL [fdo#103232] +1
>
> * igt@kms_cursor_crc@cursor-64x21-random:
> - shard-apl: PASS -> FAIL [fdo#103232]
>
> * igt@kms_cursor_crc@cursor-64x64-offscreen:
> - shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +1
>
> * igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-xtiled:
> - shard-iclb: PASS -> WARN [fdo#108336]
>
> * igt@kms_flip@flip-vs-expired-vblank-interruptible:
> - shard-kbl: PASS -> FAIL [fdo#102887] / [fdo#105363]
>
> * igt@kms_flip@flip-vs-rmfb-interruptible:
> - shard-apl: PASS -> INCOMPLETE [fdo#103927]
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
> - shard-iclb: NOTRUN -> FAIL [fdo#103167]
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
> - shard-apl: PASS -> FAIL [fdo#103167] +2
>
> * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
> - shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#106978] / [fdo#107773]
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
> - shard-iclb: PASS -> FAIL [fdo#103167] +2
>
> * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
> - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885]
>
> * igt@kms_plane@pixel-format-pipe-c-planes:
> - shard-apl: PASS -> FAIL [fdo#103166]
> - shard-glk: PASS -> FAIL [fdo#103166] +1
>
> * igt@kms_plane_alpha_blend@pipe-a-alpha-transparant-fb:
> - shard-iclb: PASS -> DMESG-FAIL [fdo#107724]
>
> * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
> - shard-apl: PASS -> FAIL [fdo#108145]
>
> * igt@kms_psr@primary_render:
> - shard-iclb: PASS -> DMESG-WARN [fdo#107724] +3
>
> * igt@kms_setmode@basic:
> - shard-kbl: PASS -> FAIL [fdo#99912]
>
> * igt@kms_sysfs_edid_timing:
> - shard-skl: NOTRUN -> FAIL [fdo#100047]
>
> * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
> - shard-kbl: PASS -> INCOMPLETE [fdo#103665]
>
> * {igt@runner@aborted}:
> - shard-iclb: NOTRUN -> FAIL [fdo#108866]
>
>
> #### Possible fixes ####
>
> * igt@gem_eio@in-flight-contexts-immediate:
> - shard-glk: FAIL [fdo#107799] -> PASS
>
> * igt@gem_workarounds@suspend-resume-fd:
> - shard-iclb: INCOMPLETE [fdo#107713] -> PASS +1
>
> * igt@kms_cursor_crc@cursor-256x256-onscreen:
> - shard-skl: FAIL [fdo#103232] -> PASS
>
> * igt@kms_cursor_crc@cursor-256x256-random:
> - shard-glk: FAIL [fdo#103232] -> PASS +2
> - shard-apl: FAIL [fdo#103232] -> PASS +3
>
> * igt@kms_flip@flip-vs-expired-vblank:
> - shard-skl: FAIL [fdo#105363] -> PASS
>
> * igt@kms_flip@modeset-vs-vblank-race-interruptible:
> - shard-apl: FAIL [fdo#103060] -> PASS
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
> - shard-apl: FAIL [fdo#103167] -> PASS +2
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
> - shard-glk: FAIL [fdo#103167] -> PASS +2
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
> - shard-iclb: FAIL [fdo#103167] -> PASS +6
>
> * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
> - shard-skl: FAIL [fdo#103191] / [fdo#107362] -> PASS
>
> * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
> - shard-apl: FAIL [fdo#108948] -> PASS
>
> * igt@kms_plane@plane-position-covered-pipe-c-planes:
> - shard-glk: FAIL [fdo#103166] -> PASS +1
>
> * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
> - shard-skl: FAIL [fdo#107815] / [fdo#108145] -> PASS
>
> * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
> - shard-skl: FAIL [fdo#107815] -> PASS
>
> * igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
> - shard-apl: FAIL [fdo#103166] -> PASS +2
> - shard-iclb: FAIL [fdo#103166] -> PASS
>
> * igt@pm_rpm@debugfs-read:
> - shard-iclb: DMESG-WARN [fdo#108654] -> PASS
>
> * igt@pm_rpm@dpms-lpsp:
> - shard-iclb: DMESG-WARN [fdo#107724] -> PASS
>
> * igt@pm_rpm@gem-execbuf-stress-extra-wait:
> - shard-skl: INCOMPLETE [fdo#107803] / [fdo#107807] -> PASS
>
> * igt@pm_rpm@modeset-non-lpsp-stress-no-wait:
> - shard-iclb: INCOMPLETE [fdo#108840] -> SKIP
>
>
> #### Warnings ####
>
> * igt@i915_selftest@live_contexts:
> - shard-iclb: DMESG-FAIL [fdo#108569] -> INCOMPLETE [fdo#108315]
>
> * igt@kms_ccs@pipe-a-crc-primary-basic:
> - shard-iclb: FAIL [fdo#107725] -> DMESG-WARN [fdo#107724] / [fdo#108336]
>
> * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
> - shard-kbl: DMESG-WARN [fdo#105604] -> DMESG-FAIL [fdo#108950]
> - shard-glk: DMESG-WARN [fdo#105763] / [fdo#106538] -> DMESG-FAIL [fdo#105763] / [fdo#106538]
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
> [fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
> [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
> [fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
> [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
> [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
> [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
> [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
> [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
> [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
> [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
> [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
> [fdo#105604]: https://bugs.freedesktop.org/show_bug.cgi?id=105604
> [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
> [fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
> [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
> [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
> [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
> [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
> [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
> [fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
> [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
> [fdo#107799]: https://bugs.freedesktop.org/show_bug.cgi?id=107799
> [fdo#107803]: https://bugs.freedesktop.org/show_bug.cgi?id=107803
> [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
> [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
> [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
> [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
> [fdo#108315]: https://bugs.freedesktop.org/show_bug.cgi?id=108315
> [fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336
> [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
> [fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
> [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
> [fdo#108866]: https://bugs.freedesktop.org/show_bug.cgi?id=108866
> [fdo#108887]: https://bugs.freedesktop.org/show_bug.cgi?id=108887
> [fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
> [fdo#108950]: https://bugs.freedesktop.org/show_bug.cgi?id=108950
> [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
>
>
> Participating hosts (7 -> 7)
> ------------------------------
>
> No changes in participating hosts
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_5325 -> Patchwork_11110
>
> CI_DRM_5325: d1085cddae920b9a0c326e3cc3e342cfee14aed2 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_4749: 270da20849db4d170db09673c6b67712c90ec9fe @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_11110: 2a15cd7c794ae90e2d6de66015665e9a985a2467 @ git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11110/
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2018-12-18 14:06 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-11-30 22:58 [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC clinton.a.taylor
2018-11-30 23:08 ` ✗ Fi.CI.BAT: failure for " Patchwork
2018-11-30 23:15 ` [PATCH] " Imre Deak
2018-11-30 23:22 ` Clint Taylor
2018-11-30 23:46 ` [PATCH v2] " clinton.a.taylor
2018-12-01 0:33 ` ✓ Fi.CI.BAT: success for drm/i915/icl: combo port vswing programming changes per BSPEC (rev2) Patchwork
2018-12-01 20:09 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-12-03 12:19 ` [PATCH] drm/i915/icl: combo port vswing programming changes per BSPEC Ville Syrjälä
2018-12-03 19:34 ` Clint Taylor
2018-12-03 19:53 ` Ville Syrjälä
2018-12-04 23:41 ` [PATCH v3] " clinton.a.taylor
2018-12-05 16:32 ` Imre Deak
2018-12-11 9:40 ` Imre Deak
2018-12-11 14:18 ` Ville Syrjälä
2018-12-11 14:25 ` Imre Deak
2018-12-11 21:31 ` [PATCH v4] " clinton.a.taylor
2018-12-17 15:23 ` Imre Deak
2018-12-17 22:13 ` [PATCH v5] " clinton.a.taylor
2018-12-04 23:47 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: combo port vswing programming changes per BSPEC (rev3) Patchwork
2018-12-05 0:09 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-12-11 21:38 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: combo port vswing programming changes per BSPEC (rev4) Patchwork
2018-12-11 21:53 ` ✓ Fi.CI.BAT: success " Patchwork
2018-12-12 1:51 ` ✓ Fi.CI.IGT: " Patchwork
2018-12-17 23:13 ` ✓ Fi.CI.BAT: success for drm/i915/icl: combo port vswing programming changes per BSPEC (rev5) Patchwork
2018-12-18 0:35 ` ✓ Fi.CI.IGT: " Patchwork
2018-12-18 14:06 ` Imre Deak
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